vertigo_vhdl 0.8.5 → 0.8.10

data/tests/parser_tests/test_microwatt_icache_pp.vhd

@@ -1,337 +0,0 @@
--- generated by Vertigo VHDL tool
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-library work;
-use work.utils.all;
-use work.common.all;
-use work.wishbone_types.all;
- 
-entity icache is
-  generic(
-    sim : booleanfalse := false;
-    line_size : positive64 := 64;
-    num_lines : positive32 := 32;
-    num_ways : positive4 := 4);
-  port(
-    clk : in std_ulogic;
-    rst : in std_ulogic;
-    i_in : in fetch1toicachetype;
-    i_out : out icachetofetch2type;
-    stall_out : out std_ulogic;
-    flush_in : in std_ulogic;
-    wishbone_out : out wishbone_master_out;
-    wishbone_in : in wishbone_slave_out);
-end entity icache;
- 
-architecture rtl of icache is
-  constant row_size : natural := wishbone_data_bits / 8;
-  constant row_per_line : natural := line_size / row_size;
-  constant bram_rows : natural := num_lines * row_per_line;
-  constant insn_per_row : natural := wishbone_data_bits / 32;
-  constant insn_bits : natural := log2(insn_per_row);
-  constant row_bits : natural := log2(bram_rows);
-  constant row_linebits : natural := log2(row_per_line);
-  constant line_off_bits : natural := log2(line_size);
-  constant row_off_bits : natural := log2(row_size);
-  constant index_bits : natural := log2(num_lines);
-  constant tag_bits : natural := 64 - line_off_bits - index_bits;
-  constant way_bits : natural := log2(num_ways);
-   
-  subtype row_t is integer range 0 to bram_rows - 1;
-   
-  subtype index_t is integer range 0 to num_lines - 1;
-   
-  subtype way_t is integer range 0 to num_ways - 1;
-   
-  subtype cache_row_t is std_ulogic_vector(wishbone_data_bits - 1 downto 0);
-   
-  subtype cache_tag_t is std_logic_vector(tag_bits - 1 downto 0);
-  constant tag_ram_width : natural := tag_bits * num_ways;
-   
-  subtype cache_tags_set_t is std_logic_vector(tag_ram_width - 1 downto 0);
-   
-  type cache_tags_array_t is array(range index_t) of cache_tags_set_t;
-   
-  subtype cache_way_valids_t is std_ulogic_vector(num_ways - 1 downto 0);
-   
-  type cache_valids_t is array(range index_t) of cache_way_valids_t;
-  signal cache_tags : cache_tags_array_t;
-  signal cache_valids : cache_valids_t;
-  attribute ram_style : string;
-  attribute ram_style of cache_tags : signal is "distributed";
-   
-  type state_t is (idle,wait_ack);
-   
-  type reg_internal_t is record
-    hit_way : way_t;
-    hit_nia : std_ulogic_vector(63 downto 0);
-    hit_smark : std_ulogic;
-    hit_valid : std_ulogic;
-    state : state_t;
-    wb : wishbone_master_out;
-    store_way : way_t;
-    store_index : index_t;
-    store_row : row_t;
-  end record;
-  signal r : reg_internal_t;
-  signal req_index : index_t;
-  signal req_row : row_t;
-  signal req_hit_way : way_t;
-  signal req_tag : cache_tag_t;
-  signal req_is_hit : std_ulogic;
-  signal req_is_miss : std_ulogic;
-  signal req_laddr : std_ulogic_vector(63 downto 0);
-   
-  type cache_ram_out_t is array(range way_t) of cache_row_t;
-  signal cache_out : cache_ram_out_t;
-   
-  type plru_out_t is array(range index_t) of std_ulogic_vector(way_bits - 1 downto 0);
-  signal plru_victim : plru_out_t;
-  signal replace_way : way_t;
-   
-  function get_index(addr : std_ulogic_vector(63 downto 0)) return index_t is
-  begin
-    return to_integer(unsigned(addr(63 - tag_bits downto line_off_bits)));
-  end function get_index;
-   
-  function get_row(addr : std_ulogic_vector(63 downto 0)) return row_t is
-  begin
-    return to_integer(unsigned(addr(63 - tag_bits downto row_off_bits)));
-  end function get_row;
-   
-  function is_last_row_addr(addr : wishbone_addr_type) return boolean is
-    constant ones : std_ulogic_vector(row_linebits - 1 downto 0) := (others => '1');
-  begin
-    return addr(line_off_bits - 1 downto row_off_bits) = ones;
-  end function is_last_row_addr;
-   
-  function is_last_row(row : row_t) return boolean is
-    variable row_v : std_ulogic_vector(row_bits - 1 downto 0);
-    constant ones : std_ulogic_vector(row_linebits - 1 downto 0) := (others => '1');
-  begin
-    row_v := std_ulogic_vector(to_unsigned(row,row_bits));
-    return row_v(row_linebits - 1 downto 0) = ones;
-  end function is_last_row;
-   
-  function next_row_addr(addr : wishbone_addr_type) return std_ulogic_vector is
-    variable row_idx : std_ulogic_vector(row_linebits - 1 downto 0);
-    variable result : wishbone_addr_type;
-  begin
-    row_idx := addr(line_off_bits - 1 downto row_off_bits);
-    row_idx := std_ulogic_vector(unsigned(row_idx) + 1);
-    result := addr;
-    result(line_off_bits - 1 downto row_off_bits) := row_idx;
-    return result;
-  end function next_row_addr;
-   
-  function next_row(row : row_t) return row_t is
-    variable row_v : std_ulogic_vector(row_bits - 1 downto 0);
-    variable row_idx : std_ulogic_vector(row_linebits - 1 downto 0);
-    variable result : std_ulogic_vector(row_bits - 1 downto 0);
-  begin
-    row_v := std_ulogic_vector(to_unsigned(row,row_bits));
-    row_idx := row_v(row_linebits - 1 downto 0);
-    row_v(row_linebits - 1 downto 0) := std_ulogic_vector(unsigned(row_idx) + 1);
-    return to_integer(unsigned(row_v));
-  end function next_row;
-   
-  function read_insn_word(addr : std_ulogic_vector(63 downto 0);data : cache_row_t) return std_ulogic_vector is
-    variable word : integer range 0 to insn_per_row - 1;
-  begin
-    word := to_integer(unsigned(addr(insn_bits + 2 - 1 downto 2)));
-    return data(31 + word * 32 downto word * 32);
-  end function read_insn_word;
-   
-  function get_tag(addr : std_ulogic_vector(63 downto 0)) return cache_tag_t is
-  begin
-    return addr(63 downto 64 - tag_bits);
-  end function get_tag;
-   
-  function read_tag(way : way_t;tagset : cache_tags_set_t) return cache_tag_t is
-  begin
-    return tagset((way + 1) * tag_bits - 1 downto way * tag_bits);
-  end function read_tag;
-   
-  procedure write_tag(
-    way : in way_t;
-    tagset : inout cache_tags_set_t;
-    tag : cache_tag_t) is
-  begin
-    tagset((way + 1) * tag_bits - 1 downto way * tag_bits) := tag;
-  end write_tag;
-begin
- 
-  assert line_size mod row_size = 0;
-  assert ispow2(line_size)
-    report "line_size not power of 2" severity failure;
-  assert ispow2(num_lines)
-    report "num_lines not power of 2" severity failure;
-  assert ispow2(row_per_line)
-    report "row_per_line not power of 2" severity failure;
-  assert ispow2(insn_per_row)
-    report "insn_per_row not power of 2" severity failure;
-  assert (row_bits = index_bits + row_linebits)
-    report "geometry bits don't add up" severity failure;
-  assert (line_off_bits = row_off_bits + row_linebits)
-    report "geometry bits don't add up" severity failure;
-  assert (64 = tag_bits + index_bits + line_off_bits)
-    report "geometry bits don't add up" severity failure;
-  assert (64 = tag_bits + row_bits + row_off_bits)
-    report "geometry bits don't add up" severity failure;
-  if sim generate
-     
-    debug : process
-    begin
-      report "row_size      = " & natural'image(row_size);
-      report "row_per_line  = " & natural'image(row_per_line);
-      report "bram_rows     = " & natural'image(bram_rows);
-      report "insn_per_row  = " & natural'image(insn_per_row);
-      report "insn_bits     = " & natural'image(insn_bits);
-      report "row_bits      = " & natural'image(row_bits);
-      report "row_linebits  = " & natural'image(row_linebits);
-      report "line_off_bits = " & natural'image(line_off_bits);
-      report "row_off_bits  = " & natural'image(row_off_bits);
-      report "index_bits    = " & natural'image(index_bits);
-      report "tag_bits      = " & natural'image(tag_bits);
-      report "way_bits      = " & natural'image(way_bits);
-      wait ;
-    end process;
-  end generate;
-  for i in 0 to num_ways - 1 generate
-    way : entity work.cache_ram
-      port map(
-        clk => clk,
-        rd_en => do_read,
-        rd_addr => rd_addr,
-        rd_data => dout,
-        wr_en => do_write,
-        wr_sel => (others => '1'),
-        wr_addr => wr_addr,
-        wr_data => wishbone_in.dat);
-     
-     
-    process(all)
-    begin
-      do_read <= '1';
-      do_write <= '0';
-      if wishbone_in.ack = '1' and r.store_way = i then
-        do_write <= '1';
-      end if;
-      cache_out(i) <= dout;
-      rd_addr <= std_ulogic_vector(to_unsigned(req_row,row_bits));
-      wr_addr <= std_ulogic_vector(to_unsigned(r.store_row,row_bits));
-    end process;
-  end generate;
-  if num_ways > 1 generate
-    for i in 0 to num_lines - 1 generate
-      plru : entity work.plru
-        port map(
-          clk => clk,
-          rst => rst,
-          acc => plru_acc,
-          acc_en => plru_acc_en,
-          lru => plru_out);
-       
-       
-      process(req_index,req_is_hit,req_hit_way,req_is_hit,plru_out)
-      begin
-        if req_is_hit = '1' and req_index = i then
-          plru_acc_en <= req_is_hit;
-        else
-          plru_acc_en <= '0';
-        end if;
-        plru_acc <= std_ulogic_vector(to_unsigned(req_hit_way,way_bits));
-        plru_victim(i) <= plru_out;
-      end process;
-    end generate;
-  end generate;
-   
-  icache_comb : process(all)
-    variable is_hit : std_ulogic;
-    variable hit_way : way_t;
-  begin
-    req_index <= get_index(i_in.nia);
-    req_row <= get_row(i_in.nia);
-    req_tag <= get_tag(i_in.nia);
-    req_laddr <= i_in.nia(63 downto line_off_bits) & (line_off_bits - 1 downto 0 => '0');
-    hit_way := 0;
-    is_hit := '0';
-    req_is_hit <= i_in.req and is_hit and flush_in;
-    req_is_miss <= i_in.req and is_hit and flush_in;
-    req_hit_way <= hit_way;
-    replace_way <= to_integer(unsigned(plru_victim(req_index)));
-    i_out.insn <= read_insn_word(r.hit_nia,cache_out(r.hit_way));
-    i_out.valid <= r.hit_valid;
-    i_out.nia <= r.hit_nia;
-    i_out.stop_mark <= r.hit_smark;
-    stall_out <= is_hit;
-    wishbone_out <= r.wb;
-  end process;
-   
-  icache_hit : process(clk)
-  begin
-    if rising_edge(clk) then
-      if req_is_hit = '1' then
-        r.hit_way <= req_hit_way;
-        r.hit_nia <= i_in.nia;
-        r.hit_smark <= i_in.stop_mark;
-        r.hit_valid <= '1';
-        report "cache hit nia:" & to_hstring(i_in.nia) & " sm:" & std_ulogic'image(i_in.stop_mark) & " idx:" & integer'image(req_index) & " tag:" & to_hstring(req_tag) & " way: " & integer'image(req_hit_way);
-      else
-        r.hit_valid <= '0';
-        r.hit_smark <= i_in.stop_mark;
-      end if;
-    end if;
-  end process;
-   
-  icache_miss : process(clk)
-    variable tagset : cache_tags_set_t;
-    variable stbs_done : boolean;
-  begin
-    if rising_edge(clk) then
-      if rst = '1' then
-        ;
-        r.state <= idle;
-        r.wb.cyc <= '0';
-        r.wb.stb <= '0';
-        r.wb.dat <= (others => '0');
-        r.wb.sel <= "11111111";
-        r.wb.we <= '0';
-        r.wb.adr <= (others => '0');
-      else
-        case r.state is
-          when idle =>
-            if req_is_miss = '1' then
-              report "cache miss nia:" & to_hstring(i_in.nia) & " sm:" & std_ulogic'image(i_in.stop_mark) & " idx:" & integer'image(req_index) & " way:" & integer'image(replace_way) & " tag:" & to_hstring(req_tag);
-              cache_valids(req_index)(replace_way) <= '0';
-              r.store_index <= req_index;
-              r.store_way <= replace_way;
-              r.store_row <= get_row(req_laddr);
-              r.wb.adr <= req_laddr(r.wb.adr'left downto 0);
-              r.wb.cyc <= '1';
-              r.wb.stb <= '1';
-              r.state <= wait_ack;
-            end if;
-          when wait_ack =>
-            stbs_done := r.wb.stb = '0';
-            if wishbone_in.stall = '0' and stbs_done then
-              if is_last_row_addr(r.wb.adr) then
-                r.wb.stb <= '0';
-                stbs_done := true;
-              end if;
-              r.wb.adr <= next_row_addr(r.wb.adr);
-            end if;
-            if wishbone_in.ack = '1' then
-              if stbs_done and is_last_row(r.store_row) then
-                r.wb.cyc <= '0';
-                cache_valids(r.store_index)(r.store_way) <= '1';
-                r.state <= idle;
-              end if;
-              r.store_row <= next_row(r.store_row);
-            end if;
-        end case;
-      end if;
-    end if;
-  end process;
-end rtl;

data/tests/parser_tests/test_microwatt_icache_tb_pp.vhd

@@ -1,104 +0,0 @@
--- generated by Vertigo VHDL tool
-library ieee;
-use ieee.std_logic_1164.all;
-library work;
-use work.common.all;
-use work.wishbone_types.all;
- 
-entity icache_tb is
-end entity icache_tb;
- 
-architecture behave of icache_tb is
-  signal clk : std_ulogic;
-  signal rst : std_ulogic;
-  signal i_out : fetch1toicachetype;
-  signal i_in : icachetofetch2type;
-  signal wb_bram_in : wishbone_master_out;
-  signal wb_bram_out : wishbone_slave_out;
-  constant clk_period : time := 10 ns;
-begin
- 
-  icache0 : entity work.icache
-    port map(
-      clk => clk,
-      rst => rst,
-      i_in => i_out,
-      i_out => i_in,
-      flush_in => '0',
-      wishbone_out => wb_bram_in,
-      wishbone_in => wb_bram_out);
-   
-  bram0 : entity work.wishbone_bram_wrapper
-    port map(
-      clk => clk,
-      rst => rst,
-      wishbone_in => wb_bram_in,
-      wishbone_out => wb_bram_out);
-   
-   
-  clk_process : process
-  begin
-    clk <= '0';
-    wait clk_period / 2;
-    clk <= '1';
-    wait clk_period / 2;
-  end process;
-   
-  rst_process : process
-  begin
-    rst <= '1';
-    wait 2 * clk_period;
-    rst <= '0';
-    wait ;
-  end process;
-   
-  stim : process
-  begin
-    i_out.req <= '0';
-    i_out.nia <= (others => '0');
-    i_out.stop_mark <= '0';
-    wait rising_edge(clk);
-    wait rising_edge(clk);
-    wait rising_edge(clk);
-    wait rising_edge(clk);
-    i_out.req <= '1';
-    i_out.nia <= x"0000000000000004";
-    wait 30 * clk_period;
-    wait rising_edge(clk);
-    assert i_in.valid = '1';
-    assert i_in.insn = x"00000001"
-      report "insn @" & to_hstring(i_out.nia) & "=" & to_hstring(i_in.insn) & " expected 00000001" severity failure;
-    i_out.req <= '0';
-    wait rising_edge(clk);
-    i_out.req <= '1';
-    i_out.nia <= x"0000000000000008";
-    wait rising_edge(clk);
-    wait rising_edge(clk);
-    assert i_in.valid = '1';
-    assert i_in.insn = x"00000002"
-      report "insn @" & to_hstring(i_out.nia) & "=" & to_hstring(i_in.insn) & " expected 00000002" severity failure;
-    wait rising_edge(clk);
-    i_out.req <= '1';
-    i_out.nia <= x"0000000000000040";
-    wait 30 * clk_period;
-    wait rising_edge(clk);
-    assert i_in.valid = '1';
-    assert i_in.insn = x"00000010"
-      report "insn @" & to_hstring(i_out.nia) & "=" & to_hstring(i_in.insn) & " expected 00000010" severity failure;
-    i_out.req <= '1';
-    i_out.nia <= x"0000000000000100";
-    wait rising_edge(clk);
-    wait rising_edge(clk);
-    assert i_in.valid = '0';
-    wait rising_edge(clk);
-    wait 30 * clk_period;
-    wait rising_edge(clk);
-    assert i_in.valid = '1';
-    assert i_in.insn = x"00000040"
-      report "insn @" & to_hstring(i_out.nia) & "=" & to_hstring(i_in.insn) & " expected 00000040" severity failure;
-    i_out.req <= '0';
-    assert false
-      report "end of test" severity failure;
-    wait ;
-  end process;
-end behave;

data/tests/parser_tests/test_microwatt_insn_helpers_pp.vhd

@@ -1,208 +0,0 @@
--- generated by Vertigo VHDL tool
-library ieee;
-use ieee.std_logic_1164.all;
- 
-package insn_helpers is
-  function insn_rs(insn_in : std_ulogic_vector) return std_ulogic_vector
-  function insn_rt(insn_in : std_ulogic_vector) return std_ulogic_vector
-  function insn_ra(insn_in : std_ulogic_vector) return std_ulogic_vector
-  function insn_rb(insn_in : std_ulogic_vector) return std_ulogic_vector
-  function insn_si(insn_in : std_ulogic_vector) return std_ulogic_vector
-  function insn_ui(insn_in : std_ulogic_vector) return std_ulogic_vector
-  function insn_l(insn_in : std_ulogic_vector) return std_ulogic
-  function insn_sh32(insn_in : std_ulogic_vector) return std_ulogic_vector
-  function insn_mb32(insn_in : std_ulogic_vector) return std_ulogic_vector
-  function insn_me32(insn_in : std_ulogic_vector) return std_ulogic_vector
-  function insn_li(insn_in : std_ulogic_vector) return std_ulogic_vector
-  function insn_lk(insn_in : std_ulogic_vector) return std_ulogic
-  function insn_aa(insn_in : std_ulogic_vector) return std_ulogic
-  function insn_rc(insn_in : std_ulogic_vector) return std_ulogic
-  function insn_oe(insn_in : std_ulogic_vector) return std_ulogic
-  function insn_bd(insn_in : std_ulogic_vector) return std_ulogic_vector
-  function insn_bf(insn_in : std_ulogic_vector) return std_ulogic_vector
-  function insn_bfa(insn_in : std_ulogic_vector) return std_ulogic_vector
-  function insn_cr(insn_in : std_ulogic_vector) return std_ulogic_vector
-  function insn_bt(insn_in : std_ulogic_vector) return std_ulogic_vector
-  function insn_ba(insn_in : std_ulogic_vector) return std_ulogic_vector
-  function insn_bb(insn_in : std_ulogic_vector) return std_ulogic_vector
-  function insn_fxm(insn_in : std_ulogic_vector) return std_ulogic_vector
-  function insn_bo(insn_in : std_ulogic_vector) return std_ulogic_vector
-  function insn_bi(insn_in : std_ulogic_vector) return std_ulogic_vector
-  function insn_bh(insn_in : std_ulogic_vector) return std_ulogic_vector
-  function insn_d(insn_in : std_ulogic_vector) return std_ulogic_vector
-  function insn_ds(insn_in : std_ulogic_vector) return std_ulogic_vector
-  function insn_to(insn_in : std_ulogic_vector) return std_ulogic_vector
-  function insn_bc(insn_in : std_ulogic_vector) return std_ulogic_vector
-  function insn_sh(insn_in : std_ulogic_vector) return std_ulogic_vector
-  function insn_me(insn_in : std_ulogic_vector) return std_ulogic_vector
-  function insn_mb(insn_in : std_ulogic_vector) return std_ulogic_vector
- 
-end insn_helpers;
- 
-package body insn_helpers is
-   
-  function insn_rs(insn_in : std_ulogic_vector) return std_ulogic_vector is
-  begin
-    return insn_in(25 downto 21);
-  end function insn_rs;
-   
-  function insn_rt(insn_in : std_ulogic_vector) return std_ulogic_vector is
-  begin
-    return insn_in(25 downto 21);
-  end function insn_rt;
-   
-  function insn_ra(insn_in : std_ulogic_vector) return std_ulogic_vector is
-  begin
-    return insn_in(20 downto 16);
-  end function insn_ra;
-   
-  function insn_rb(insn_in : std_ulogic_vector) return std_ulogic_vector is
-  begin
-    return insn_in(15 downto 11);
-  end function insn_rb;
-   
-  function insn_si(insn_in : std_ulogic_vector) return std_ulogic_vector is
-  begin
-    return insn_in(15 downto 0);
-  end function insn_si;
-   
-  function insn_ui(insn_in : std_ulogic_vector) return std_ulogic_vector is
-  begin
-    return insn_in(15 downto 0);
-  end function insn_ui;
-   
-  function insn_l(insn_in : std_ulogic_vector) return std_ulogic is
-  begin
-    return insn_in(21);
-  end function insn_l;
-   
-  function insn_sh32(insn_in : std_ulogic_vector) return std_ulogic_vector is
-  begin
-    return insn_in(15 downto 11);
-  end function insn_sh32;
-   
-  function insn_mb32(insn_in : std_ulogic_vector) return std_ulogic_vector is
-  begin
-    return insn_in(10 downto 6);
-  end function insn_mb32;
-   
-  function insn_me32(insn_in : std_ulogic_vector) return std_ulogic_vector is
-  begin
-    return insn_in(5 downto 1);
-  end function insn_me32;
-   
-  function insn_li(insn_in : std_ulogic_vector) return std_ulogic_vector is
-  begin
-    return insn_in(25 downto 2);
-  end function insn_li;
-   
-  function insn_lk(insn_in : std_ulogic_vector) return std_ulogic is
-  begin
-    return insn_in(0);
-  end function insn_lk;
-   
-  function insn_aa(insn_in : std_ulogic_vector) return std_ulogic is
-  begin
-    return insn_in(1);
-  end function insn_aa;
-   
-  function insn_rc(insn_in : std_ulogic_vector) return std_ulogic is
-  begin
-    return insn_in(0);
-  end function insn_rc;
-   
-  function insn_oe(insn_in : std_ulogic_vector) return std_ulogic is
-  begin
-    return insn_in(10);
-  end function insn_oe;
-   
-  function insn_bd(insn_in : std_ulogic_vector) return std_ulogic_vector is
-  begin
-    return insn_in(15 downto 2);
-  end function insn_bd;
-   
-  function insn_bf(insn_in : std_ulogic_vector) return std_ulogic_vector is
-  begin
-    return insn_in(25 downto 23);
-  end function insn_bf;
-   
-  function insn_bfa(insn_in : std_ulogic_vector) return std_ulogic_vector is
-  begin
-    return insn_in(20 downto 18);
-  end function insn_bfa;
-   
-  function insn_cr(insn_in : std_ulogic_vector) return std_ulogic_vector is
-  begin
-    return insn_in(10 downto 1);
-  end function insn_cr;
-   
-  function insn_bb(insn_in : std_ulogic_vector) return std_ulogic_vector is
-  begin
-    return insn_in(15 downto 11);
-  end function insn_bb;
-   
-  function insn_ba(insn_in : std_ulogic_vector) return std_ulogic_vector is
-  begin
-    return insn_in(20 downto 16);
-  end function insn_ba;
-   
-  function insn_bt(insn_in : std_ulogic_vector) return std_ulogic_vector is
-  begin
-    return insn_in(25 downto 21);
-  end function insn_bt;
-   
-  function insn_fxm(insn_in : std_ulogic_vector) return std_ulogic_vector is
-  begin
-    return insn_in(19 downto 12);
-  end function insn_fxm;
-   
-  function insn_bo(insn_in : std_ulogic_vector) return std_ulogic_vector is
-  begin
-    return insn_in(25 downto 21);
-  end function insn_bo;
-   
-  function insn_bi(insn_in : std_ulogic_vector) return std_ulogic_vector is
-  begin
-    return insn_in(20 downto 16);
-  end function insn_bi;
-   
-  function insn_bh(insn_in : std_ulogic_vector) return std_ulogic_vector is
-  begin
-    return insn_in(12 downto 11);
-  end function insn_bh;
-   
-  function insn_d(insn_in : std_ulogic_vector) return std_ulogic_vector is
-  begin
-    return insn_in(15 downto 0);
-  end function insn_d;
-   
-  function insn_ds(insn_in : std_ulogic_vector) return std_ulogic_vector is
-  begin
-    return insn_in(15 downto 2);
-  end function insn_ds;
-   
-  function insn_to(insn_in : std_ulogic_vector) return std_ulogic_vector is
-  begin
-    return insn_in(25 downto 21);
-  end function insn_to;
-   
-  function insn_bc(insn_in : std_ulogic_vector) return std_ulogic_vector is
-  begin
-    return insn_in(10 downto 6);
-  end function insn_bc;
-   
-  function insn_sh(insn_in : std_ulogic_vector) return std_ulogic_vector is
-  begin
-    return insn_in(1) & insn_in(15 downto 11);
-  end function insn_sh;
-   
-  function insn_me(insn_in : std_ulogic_vector) return std_ulogic_vector is
-  begin
-    return insn_in(5) & insn_in(10 downto 6);
-  end function insn_me;
-   
-  function insn_mb(insn_in : std_ulogic_vector) return std_ulogic_vector is
-  begin
-    return insn_in(5) & insn_in(10 downto 6);
-  end function insn_mb;
-end insn_helpers;