vertigo_vhdl 0.8.5 → 0.8.10
Sign up to get free protection for your applications and to get access to all the features.
- checksums.yaml +4 -4
- data/lib/vertigo/parser.rb +28 -5
- data/lib/vertigo/tb_generator.rb +20 -7
- data/lib/vertigo/version.rb +1 -1
- data/tests/parser_tests/test_adder_rca_vhdl93.vhd +37 -0
- metadata +4 -85
- data/tests/ghdl_tests/test_fsm.vhd +0 -162
- data/tests/parser_tests/else.vhd +0 -64
- data/tests/parser_tests/pingpong.vhd +0 -34
- data/tests/parser_tests/test_accelerator_pp.vhd +0 -144
- data/tests/parser_tests/test_aggregate_pp.vhd +0 -15
- data/tests/parser_tests/test_archi_1_pp.vhd +0 -41
- data/tests/parser_tests/test_array_array_00_pp.vhd +0 -25
- data/tests/parser_tests/test_array_urange_pp.vhd +0 -25
- data/tests/parser_tests/test_chu-1_pp.vhd +0 -104
- data/tests/parser_tests/test_concat_pp.vhd +0 -14
- data/tests/parser_tests/test_counter_pp.vhd +0 -35
- data/tests/parser_tests/test_de2_pp.vhd +0 -274
- data/tests/parser_tests/test_encode_pp.vhd +0 -2549
- data/tests/parser_tests/test_fsm_pp.vhd +0 -125
- data/tests/parser_tests/test_fsm_synth_pp.vhd +0 -197
- data/tests/parser_tests/test_function-01_pp.vhd +0 -18
- data/tests/parser_tests/test_lfsr_pp.vhd +0 -44
- data/tests/parser_tests/test_microwatt_cache_ram_pp.vhd +0 -68
- data/tests/parser_tests/test_microwatt_common_pp.vhd +0 -336
- data/tests/parser_tests/test_microwatt_control_pp.vhd +0 -187
- data/tests/parser_tests/test_microwatt_core_debug_pp.vhd +0 -104
- data/tests/parser_tests/test_microwatt_core_pp.vhd +0 -231
- data/tests/parser_tests/test_microwatt_core_tb_pp.vhd +0 -43
- data/tests/parser_tests/test_microwatt_countzero_pp.vhd +0 -120
- data/tests/parser_tests/test_microwatt_countzero_tb_pp.vhd +0 -70
- data/tests/parser_tests/test_microwatt_cr_file_pp.vhd +0 -74
- data/tests/parser_tests/test_microwatt_cr_hazard_pp.vhd +0 -51
- data/tests/parser_tests/test_microwatt_crhelpers_pp.vhd +0 -48
- data/tests/parser_tests/test_microwatt_dcache_pp.vhd +0 -481
- data/tests/parser_tests/test_microwatt_dcache_tb_pp.vhd +0 -98
- data/tests/parser_tests/test_microwatt_decode1_pp.vhd +0 -138
- data/tests/parser_tests/test_microwatt_decode2_pp.vhd +0 -300
- data/tests/parser_tests/test_microwatt_decode_types_pp.vhd +0 -67
- data/tests/parser_tests/test_microwatt_divider_pp.vhd +0 -132
- data/tests/parser_tests/test_microwatt_divider_tb_pp.vhd +0 -95
- data/tests/parser_tests/test_microwatt_dmi_dtm_dummy_pp.vhd +0 -29
- data/tests/parser_tests/test_microwatt_dmi_dtm_tb_pp.vhd +0 -197
- data/tests/parser_tests/test_microwatt_dmi_dtm_xilinx_pp.vhd +0 -139
- data/tests/parser_tests/test_microwatt_execute1_pp.vhd +0 -689
- data/tests/parser_tests/test_microwatt_fetch1_pp.vhd +0 -88
- data/tests/parser_tests/test_microwatt_fetch2_pp.vhd +0 -79
- data/tests/parser_tests/test_microwatt_glibc_random_helpers_pp.vhd +0 -25
- data/tests/parser_tests/test_microwatt_glibc_random_pp.vhd +0 -41
- data/tests/parser_tests/test_microwatt_gpr_hazard_pp.vhd +0 -68
- data/tests/parser_tests/test_microwatt_helpers_pp.vhd +0 -153
- data/tests/parser_tests/test_microwatt_icache_pp.vhd +0 -337
- data/tests/parser_tests/test_microwatt_icache_tb_pp.vhd +0 -104
- data/tests/parser_tests/test_microwatt_insn_helpers_pp.vhd +0 -208
- data/tests/parser_tests/test_microwatt_loadstore1_pp.vhd +0 -222
- data/tests/parser_tests/test_microwatt_logical_pp.vhd +0 -87
- data/tests/parser_tests/test_microwatt_multiply_pp.vhd +0 -84
- data/tests/parser_tests/test_microwatt_multiply_tb_pp.vhd +0 -75
- data/tests/parser_tests/test_microwatt_plru_pp.vhd +0 -46
- data/tests/parser_tests/test_microwatt_plru_tb_pp.vhd +0 -93
- data/tests/parser_tests/test_microwatt_ppc_fx_insns_pp.vhd +0 -665
- data/tests/parser_tests/test_microwatt_register_file_pp.vhd +0 -86
- data/tests/parser_tests/test_microwatt_rotator_pp.vhd +0 -149
- data/tests/parser_tests/test_microwatt_rotator_tb_pp.vhd +0 -134
- data/tests/parser_tests/test_microwatt_sim_bram_helpers_pp.vhd +0 -52
- data/tests/parser_tests/test_microwatt_sim_bram_pp.vhd +0 -53
- data/tests/parser_tests/test_microwatt_sim_console_pp.vhd +0 -43
- data/tests/parser_tests/test_microwatt_sim_jtag_pp.vhd +0 -64
- data/tests/parser_tests/test_microwatt_sim_jtag_socket_pp.vhd +0 -36
- data/tests/parser_tests/test_microwatt_sim_uart_pp.vhd +0 -90
- data/tests/parser_tests/test_microwatt_soc_pp.vhd +0 -195
- data/tests/parser_tests/test_microwatt_utils_pp.vhd +0 -39
- data/tests/parser_tests/test_microwatt_wishbone_arbiter_pp.vhd +0 -54
- data/tests/parser_tests/test_microwatt_wishbone_bram_tb_pp.vhd +0 -157
- data/tests/parser_tests/test_microwatt_wishbone_bram_wrapper_pp.vhd +0 -62
- data/tests/parser_tests/test_microwatt_wishbone_debug_master_pp.vhd +0 -124
- data/tests/parser_tests/test_microwatt_wishbone_types_pp.vhd +0 -38
- data/tests/parser_tests/test_microwatt_writeback_pp.vhd +0 -87
- data/tests/parser_tests/test_package-1_pp.vhd +0 -53
- data/tests/parser_tests/test_precedence_pp.vhd +0 -16
- data/tests/parser_tests/test_selected_sig_pp.vhd +0 -10
- data/tests/parser_tests/test_slice_pp.vhd +0 -16
- data/tests/parser_tests/test_tb-00_pp.vhd +0 -71
- data/tests/parser_tests/test_type_decl_02_pp.vhd +0 -11
- data/tests/parser_tests/test_use_pp.vhd +0 -10
- data/tests/parser_tests/test_while_1_pp.vhd +0 -26
- data/tests/parser_tests/test_with-00_pp.vhd +0 -12
- data/tests/tb_gen_tests/test_accelerator.vhd +0 -160
@@ -1,88 +0,0 @@
|
|
1
|
-
-- generated by Vertigo VHDL tool
|
2
|
-
library ieee;
|
3
|
-
use ieee.std_logic_1164.all;
|
4
|
-
use ieee.numeric_std.all;
|
5
|
-
library work;
|
6
|
-
use work.common.all;
|
7
|
-
|
8
|
-
entity fetch1 is
|
9
|
-
generic(
|
10
|
-
reset_address : std_logic_vector(63 downto 0)(others => '0') := (others => '0'));
|
11
|
-
port(
|
12
|
-
clk : in std_ulogic;
|
13
|
-
rst : in std_ulogic;
|
14
|
-
stall_in : in std_ulogic;
|
15
|
-
flush_in : in std_ulogic;
|
16
|
-
stop_in : in std_ulogic;
|
17
|
-
e_in : in execute1tofetch1type;
|
18
|
-
i_out : out fetch1toicachetype);
|
19
|
-
end entity fetch1;
|
20
|
-
|
21
|
-
architecture behaviour of fetch1 is
|
22
|
-
|
23
|
-
type stop_state_t is (running,stopped,restarting);
|
24
|
-
|
25
|
-
type reg_internal_t is record
|
26
|
-
stop_state : stop_state_t;
|
27
|
-
end record;
|
28
|
-
signal r : fetch1toicachetype;
|
29
|
-
signal r_next : fetch1toicachetype;
|
30
|
-
signal r_int : reg_internal_t;
|
31
|
-
signal r_next_int : reg_internal_t;
|
32
|
-
begin
|
33
|
-
|
34
|
-
|
35
|
-
regs : process(clk)
|
36
|
-
begin
|
37
|
-
if rising_edge(clk) then
|
38
|
-
if r /= r_next then
|
39
|
-
report "fetch1 rst:" & std_ulogic'image(rst) & " r:" & std_ulogic'image(e_in.redirect) & " s:" & std_ulogic'image(stall_in) & " t:" & std_ulogic'image(stop_in) & " nia:" & to_hstring(r_next.nia) & " sm:" & std_ulogic'image(r_next.stop_mark);
|
40
|
-
end if;
|
41
|
-
r <= r_next;
|
42
|
-
r_int <= r_next_int;
|
43
|
-
end if;
|
44
|
-
end process;
|
45
|
-
|
46
|
-
comb : process(all)
|
47
|
-
variable v : fetch1toicachetype;
|
48
|
-
variable v_int : reg_internal_t;
|
49
|
-
variable increment : boolean;
|
50
|
-
begin
|
51
|
-
v := r;
|
52
|
-
v_int := r_int;
|
53
|
-
if rst = '1' then
|
54
|
-
v.nia := reset_address;
|
55
|
-
v_int.stop_state := running;
|
56
|
-
elsif e_in.redirect = '1' then
|
57
|
-
v.nia := e_in.redirect_nia;
|
58
|
-
elsif stall_in = '0' then
|
59
|
-
increment := true;
|
60
|
-
case v_int.stop_state is
|
61
|
-
when running =>
|
62
|
-
if stop_in = '1' then
|
63
|
-
increment := false;
|
64
|
-
v_int.stop_state := stopped;
|
65
|
-
end if;
|
66
|
-
when stopped =>
|
67
|
-
increment := false;
|
68
|
-
if stop_in = '0' then
|
69
|
-
v_int.stop_state := restarting;
|
70
|
-
end if;
|
71
|
-
when restarting =>
|
72
|
-
if stop_in = '0' then
|
73
|
-
v_int.stop_state := running;
|
74
|
-
else
|
75
|
-
v_int.stop_state := stopped;
|
76
|
-
end if;
|
77
|
-
end case;
|
78
|
-
if increment then
|
79
|
-
v.nia := std_logic_vector(unsigned(v.nia) + 4);
|
80
|
-
end if;
|
81
|
-
end if;
|
82
|
-
v.req := rst;
|
83
|
-
v.stop_mark := stop_in;
|
84
|
-
r_next <= v;
|
85
|
-
r_next_int <= v_int;
|
86
|
-
i_out <= r;
|
87
|
-
end process;
|
88
|
-
end behaviour;
|
@@ -1,79 +0,0 @@
|
|
1
|
-
-- generated by Vertigo VHDL tool
|
2
|
-
library ieee;
|
3
|
-
use ieee.std_logic_1164.all;
|
4
|
-
use ieee.numeric_std.all;
|
5
|
-
library work;
|
6
|
-
use work.common.all;
|
7
|
-
use work.wishbone_types.all;
|
8
|
-
|
9
|
-
entity fetch2 is
|
10
|
-
port(
|
11
|
-
clk : in std_ulogic;
|
12
|
-
rst : in std_ulogic;
|
13
|
-
stall_in : in std_ulogic;
|
14
|
-
flush_in : in std_ulogic;
|
15
|
-
i_in : in icachetofetch2type;
|
16
|
-
f_out : out fetch2todecode1type);
|
17
|
-
end entity fetch2;
|
18
|
-
|
19
|
-
architecture behaviour of fetch2 is
|
20
|
-
|
21
|
-
type reg_internal_type is record
|
22
|
-
stash : icachetofetch2type;
|
23
|
-
stash_valid : std_ulogic;
|
24
|
-
stopped : std_ulogic;
|
25
|
-
end record;
|
26
|
-
signal r_int : reg_internal_type;
|
27
|
-
signal rin_int : reg_internal_type;
|
28
|
-
signal r : fetch2todecode1type;
|
29
|
-
signal rin : fetch2todecode1type;
|
30
|
-
begin
|
31
|
-
|
32
|
-
|
33
|
-
regs : process(clk)
|
34
|
-
begin
|
35
|
-
if rising_edge(clk) then
|
36
|
-
if (r /= rin) then
|
37
|
-
report "fetch2 rst:" & std_ulogic'image(rst) & " s:" & std_ulogic'image(stall_in) & " f:" & std_ulogic'image(flush_in) & " t:" & std_ulogic'image(rin.stop_mark) & " v:" & std_ulogic'image(rin.valid) & " nia:" & to_hstring(rin.nia);
|
38
|
-
end if;
|
39
|
-
if rst = '1' or flush_in = '1' or stall_in = '0' then
|
40
|
-
r <= rin;
|
41
|
-
end if;
|
42
|
-
r_int <= rin_int;
|
43
|
-
end if;
|
44
|
-
end process;
|
45
|
-
|
46
|
-
comb : process(all)
|
47
|
-
variable v : fetch2todecode1type;
|
48
|
-
variable v_int : reg_internal_type;
|
49
|
-
variable v_i_in : icachetofetch2type;
|
50
|
-
begin
|
51
|
-
v := r;
|
52
|
-
v_int := r_int;
|
53
|
-
if stall_in = '1' and v_int.stash_valid = '0' then
|
54
|
-
v_int.stash := i_in;
|
55
|
-
v_int.stash_valid := '1';
|
56
|
-
end if;
|
57
|
-
v_i_in := i_in;
|
58
|
-
if v_int.stash_valid = '1' and stall_in = '0' then
|
59
|
-
v_i_in := v_int.stash;
|
60
|
-
v_int.stash_valid := '0';
|
61
|
-
end if;
|
62
|
-
v.valid := v_i_in.valid;
|
63
|
-
v.stop_mark := v_i_in.stop_mark;
|
64
|
-
v.nia := v_i_in.nia;
|
65
|
-
v.insn := v_i_in.insn;
|
66
|
-
if flush_in = '1' then
|
67
|
-
v_int.stash.valid := '0';
|
68
|
-
end if;
|
69
|
-
if flush_in = '1' or v.stop_mark = '1' then
|
70
|
-
v.valid := '0';
|
71
|
-
end if;
|
72
|
-
if rst = '1' then
|
73
|
-
v_int.stash_valid := '0';
|
74
|
-
end if;
|
75
|
-
rin <= v;
|
76
|
-
rin_int <= v_int;
|
77
|
-
f_out <= r;
|
78
|
-
end process;
|
79
|
-
end behaviour;
|
@@ -1,25 +0,0 @@
|
|
1
|
-
-- generated by Vertigo VHDL tool
|
2
|
-
|
3
|
-
package glibc_random_helpers is
|
4
|
-
|
5
|
-
procedure srand(
|
6
|
-
v : integer);
|
7
|
-
attribute foreign of srand : procedure is "vhpidirect srand";
|
8
|
-
function random() return integer
|
9
|
-
attribute foreign of random : function is "vhpidirect random";
|
10
|
-
|
11
|
-
end glibc_random_helpers;
|
12
|
-
|
13
|
-
package body glibc_random_helpers is
|
14
|
-
|
15
|
-
procedure srand(
|
16
|
-
v : integer) is
|
17
|
-
begin
|
18
|
-
assert false;
|
19
|
-
end srand;
|
20
|
-
|
21
|
-
function random() return integer is
|
22
|
-
begin
|
23
|
-
assert false;
|
24
|
-
end function random;
|
25
|
-
end glibc_random_helpers;
|
@@ -1,41 +0,0 @@
|
|
1
|
-
-- generated by Vertigo VHDL tool
|
2
|
-
library ieee;
|
3
|
-
use ieee.std_logic_1164.all;
|
4
|
-
use ieee.numeric_std.all;
|
5
|
-
library work;
|
6
|
-
use work.glibc_random_helpers.all;
|
7
|
-
|
8
|
-
package glibc_random is
|
9
|
-
function pseudorand(a : integer) return std_ulogic_vector
|
10
|
-
function pseudorand1() return std_ulogic
|
11
|
-
|
12
|
-
end glibc_random;
|
13
|
-
|
14
|
-
package body glibc_random is
|
15
|
-
|
16
|
-
function pseudorand(a : integer) return std_ulogic_vector is
|
17
|
-
variable tmp1 : std_ulogic_vector(31 downto 0);
|
18
|
-
variable tmp2 : std_ulogic_vector(31 downto 0);
|
19
|
-
variable tmp3 : std_ulogic_vector(31 downto 0);
|
20
|
-
variable tmp4 : std_ulogic_vector(31 downto 0);
|
21
|
-
variable ret : std_ulogic_vector(63 downto 0);
|
22
|
-
begin
|
23
|
-
tmp1 := std_ulogic_vector(to_unsigned(random,32));
|
24
|
-
tmp2 := std_ulogic_vector(to_unsigned(random,32));
|
25
|
-
if a <= 32 then
|
26
|
-
ret := tmp1 & tmp2;
|
27
|
-
else
|
28
|
-
tmp3 := std_ulogic_vector(to_unsigned(random,32));
|
29
|
-
tmp4 := std_ulogic_vector(to_unsigned(random,32));
|
30
|
-
ret := tmp1(15 downto 0) & tmp2(15 downto 0) & tmp3(15 downto 0) & tmp4(15 downto 0);
|
31
|
-
end if;
|
32
|
-
return ret((a - 1) downto 0);
|
33
|
-
end function pseudorand;
|
34
|
-
|
35
|
-
function pseudorand1() return std_ulogic is
|
36
|
-
variable tmp : std_ulogic_vector(31 downto 0);
|
37
|
-
begin
|
38
|
-
tmp := std_ulogic_vector(to_unsigned(random,32));
|
39
|
-
return tmp(0);
|
40
|
-
end function pseudorand1;
|
41
|
-
end glibc_random;
|
@@ -1,68 +0,0 @@
|
|
1
|
-
-- generated by Vertigo VHDL tool
|
2
|
-
library ieee;
|
3
|
-
use ieee.std_logic_1164.all;
|
4
|
-
use ieee.numeric_std.all;
|
5
|
-
|
6
|
-
entity gpr_hazard is
|
7
|
-
generic(
|
8
|
-
pipeline_depth : natural2 := 2);
|
9
|
-
port(
|
10
|
-
clk : in std_ulogic;
|
11
|
-
stall_in : in std_ulogic;
|
12
|
-
gpr_write_valid_in : in std_ulogic;
|
13
|
-
gpr_write_in : in std_ulogic_vector(5 downto 0);
|
14
|
-
bypass_avail : in std_ulogic;
|
15
|
-
gpr_read_valid_in : in std_ulogic;
|
16
|
-
gpr_read_in : in std_ulogic_vector(5 downto 0);
|
17
|
-
stall_out : out std_ulogic;
|
18
|
-
use_bypass : out std_ulogic);
|
19
|
-
end entity gpr_hazard;
|
20
|
-
|
21
|
-
architecture behaviour of gpr_hazard is
|
22
|
-
|
23
|
-
type pipeline_entry_type is record
|
24
|
-
valid : std_ulogic;
|
25
|
-
bypass : std_ulogic;
|
26
|
-
gpr : std_ulogic_vector(5 downto 0);
|
27
|
-
end record;
|
28
|
-
constant pipeline_entry_init : pipeline_entry_type := (valid => '0',bypass => '0',gpr => (others => '0'));
|
29
|
-
|
30
|
-
type pipeline_t is array(range 0 to pipeline_depth - 1) of pipeline_entry_type;
|
31
|
-
constant pipeline_t_init : pipeline_t := (others => pipeline_entry_init);
|
32
|
-
signal r : pipeline_t;
|
33
|
-
signal rin : pipeline_t := pipeline_t_init;
|
34
|
-
begin
|
35
|
-
|
36
|
-
|
37
|
-
gpr_hazard0 : process(clk)
|
38
|
-
begin
|
39
|
-
if rising_edge(clk) then
|
40
|
-
r <= rin;
|
41
|
-
end if;
|
42
|
-
end process;
|
43
|
-
|
44
|
-
gpr_hazard1 : process(all)
|
45
|
-
variable v : pipeline_t;
|
46
|
-
begin
|
47
|
-
v := r;
|
48
|
-
stall_out <= '0';
|
49
|
-
use_bypass <= '0';
|
50
|
-
if gpr_read_valid_in = '1' then
|
51
|
-
if r(0).valid = '1' and r(0).gpr = gpr_read_in then
|
52
|
-
if r(0).bypass = '1' and stall_in = '0' then
|
53
|
-
use_bypass <= '1';
|
54
|
-
else
|
55
|
-
stall_out <= '1';
|
56
|
-
end if;
|
57
|
-
end if;
|
58
|
-
end if;
|
59
|
-
if stall_in = '0' then
|
60
|
-
v(0).valid := gpr_write_valid_in;
|
61
|
-
v(0).bypass := bypass_avail;
|
62
|
-
v(0).gpr := gpr_write_in;
|
63
|
-
else
|
64
|
-
;
|
65
|
-
end if;
|
66
|
-
rin <= v;
|
67
|
-
end process;
|
68
|
-
end behaviour;
|
@@ -1,153 +0,0 @@
|
|
1
|
-
-- generated by Vertigo VHDL tool
|
2
|
-
library ieee;
|
3
|
-
use ieee.std_logic_1164.all;
|
4
|
-
use ieee.numeric_std.all;
|
5
|
-
library work;
|
6
|
-
|
7
|
-
package helpers is
|
8
|
-
function fls_32(val : std_ulogic_vector(31 downto 0)) return integer
|
9
|
-
function ffs_32(val : std_ulogic_vector(31 downto 0)) return integer
|
10
|
-
function fls_64(val : std_ulogic_vector(63 downto 0)) return integer
|
11
|
-
function ffs_64(val : std_ulogic_vector(63 downto 0)) return integer
|
12
|
-
function popcnt8(val : std_ulogic_vector(7 downto 0)) return std_ulogic_vector
|
13
|
-
function popcnt32(val : std_ulogic_vector(31 downto 0)) return std_ulogic_vector
|
14
|
-
function popcnt64(val : std_ulogic_vector(63 downto 0)) return std_ulogic_vector
|
15
|
-
function cmp_one_byte(a : std_ulogic_vector(7 downto 0);b : std_ulogic_vector(7 downto 0)) return std_ulogic_vector
|
16
|
-
function ppc_signed_compare(a : signed(63 downto 0);b : signed(63 downto 0);so : std_ulogic) return std_ulogic_vector
|
17
|
-
function ppc_unsigned_compare(a : unsigned(63 downto 0);b : unsigned(63 downto 0);so : std_ulogic) return std_ulogic_vector
|
18
|
-
function ra_or_zero(ra : std_ulogic_vector(63 downto 0);reg : std_ulogic_vector(4 downto 0)) return std_ulogic_vector
|
19
|
-
function byte_reverse(val : std_ulogic_vector(63 downto 0);size : integer) return std_ulogic_vector
|
20
|
-
function sign_extend(val : std_ulogic_vector(63 downto 0);size : natural) return std_ulogic_vector
|
21
|
-
|
22
|
-
end helpers;
|
23
|
-
|
24
|
-
package body helpers is
|
25
|
-
|
26
|
-
function fls_32(val : std_ulogic_vector(31 downto 0)) return integer is
|
27
|
-
variable ret : integer;
|
28
|
-
begin
|
29
|
-
ret := 32;
|
30
|
-
return ret;
|
31
|
-
end function fls_32;
|
32
|
-
|
33
|
-
function ffs_32(val : std_ulogic_vector(31 downto 0)) return integer is
|
34
|
-
variable ret : integer;
|
35
|
-
begin
|
36
|
-
ret := 32;
|
37
|
-
return ret;
|
38
|
-
end function ffs_32;
|
39
|
-
|
40
|
-
function fls_64(val : std_ulogic_vector(63 downto 0)) return integer is
|
41
|
-
variable ret : integer;
|
42
|
-
begin
|
43
|
-
ret := 64;
|
44
|
-
return ret;
|
45
|
-
end function fls_64;
|
46
|
-
|
47
|
-
function ffs_64(val : std_ulogic_vector(63 downto 0)) return integer is
|
48
|
-
variable ret : integer;
|
49
|
-
begin
|
50
|
-
ret := 64;
|
51
|
-
return ret;
|
52
|
-
end function ffs_64;
|
53
|
-
|
54
|
-
function popcnt8(val : std_ulogic_vector(7 downto 0)) return std_ulogic_vector is
|
55
|
-
variable ret : unsigned(3 downto 0) := (others => '0');
|
56
|
-
begin
|
57
|
-
;
|
58
|
-
return std_ulogic_vector(resize(ret,val'length));
|
59
|
-
end function popcnt8;
|
60
|
-
|
61
|
-
function popcnt32(val : std_ulogic_vector(31 downto 0)) return std_ulogic_vector is
|
62
|
-
variable ret : unsigned(5 downto 0) := (others => '0');
|
63
|
-
begin
|
64
|
-
;
|
65
|
-
return std_ulogic_vector(resize(ret,val'length));
|
66
|
-
end function popcnt32;
|
67
|
-
|
68
|
-
function popcnt64(val : std_ulogic_vector(63 downto 0)) return std_ulogic_vector is
|
69
|
-
variable ret : unsigned(6 downto 0) := (others => '0');
|
70
|
-
begin
|
71
|
-
;
|
72
|
-
return std_ulogic_vector(resize(ret,val'length));
|
73
|
-
end function popcnt64;
|
74
|
-
|
75
|
-
function cmp_one_byte(a : std_ulogic_vector(7 downto 0);b : std_ulogic_vector(7 downto 0)) return std_ulogic_vector is
|
76
|
-
variable ret : std_ulogic_vector(7 downto 0);
|
77
|
-
begin
|
78
|
-
if a = b then
|
79
|
-
ret := x"ff";
|
80
|
-
else
|
81
|
-
ret := x"00";
|
82
|
-
end if;
|
83
|
-
return ret;
|
84
|
-
end function cmp_one_byte;
|
85
|
-
|
86
|
-
function ppc_signed_compare(a : signed(63 downto 0);b : signed(63 downto 0);so : std_ulogic) return std_ulogic_vector is
|
87
|
-
variable ret : std_ulogic_vector(2 downto 0);
|
88
|
-
begin
|
89
|
-
if a < b then
|
90
|
-
ret := "100";
|
91
|
-
elsif a > b then
|
92
|
-
ret := "010";
|
93
|
-
else
|
94
|
-
ret := "001";
|
95
|
-
end if;
|
96
|
-
return ret & so;
|
97
|
-
end function ppc_signed_compare;
|
98
|
-
|
99
|
-
function ppc_unsigned_compare(a : unsigned(63 downto 0);b : unsigned(63 downto 0);so : std_ulogic) return std_ulogic_vector is
|
100
|
-
variable ret : std_ulogic_vector(2 downto 0);
|
101
|
-
begin
|
102
|
-
if a < b then
|
103
|
-
ret := "100";
|
104
|
-
elsif a > b then
|
105
|
-
ret := "010";
|
106
|
-
else
|
107
|
-
ret := "001";
|
108
|
-
end if;
|
109
|
-
return ret & so;
|
110
|
-
end function ppc_unsigned_compare;
|
111
|
-
|
112
|
-
function ra_or_zero(ra : std_ulogic_vector(63 downto 0);reg : std_ulogic_vector(4 downto 0)) return std_ulogic_vector is
|
113
|
-
begin
|
114
|
-
if to_integer(unsigned(reg)) = 0 then
|
115
|
-
return x"0000000000000000";
|
116
|
-
else
|
117
|
-
return ra;
|
118
|
-
end if;
|
119
|
-
end function ra_or_zero;
|
120
|
-
|
121
|
-
function byte_reverse(val : std_ulogic_vector(63 downto 0);size : integer) return std_ulogic_vector is
|
122
|
-
variable ret : std_ulogic_vector(63 downto 0) := (others => '0');
|
123
|
-
begin
|
124
|
-
case size is
|
125
|
-
when 2 =>
|
126
|
-
;
|
127
|
-
when 4 =>
|
128
|
-
;
|
129
|
-
when 8 =>
|
130
|
-
;
|
131
|
-
when others =>
|
132
|
-
report "bad byte reverse length " & integer'image(size) severity failure;
|
133
|
-
end case;
|
134
|
-
return ret;
|
135
|
-
end function byte_reverse;
|
136
|
-
|
137
|
-
function sign_extend(val : std_ulogic_vector(63 downto 0);size : natural) return std_ulogic_vector is
|
138
|
-
variable ret : signed(63 downto 0) := (others => '0');
|
139
|
-
variable upper : integer := 0;
|
140
|
-
begin
|
141
|
-
case size is
|
142
|
-
when 2 =>
|
143
|
-
ret := resize(signed(val(15 downto 0)),64);
|
144
|
-
when 4 =>
|
145
|
-
ret := resize(signed(val(31 downto 0)),64);
|
146
|
-
when 8 =>
|
147
|
-
ret := resize(signed(val(63 downto 0)),64);
|
148
|
-
when others =>
|
149
|
-
report "bad byte reverse length " & integer'image(size) severity failure;
|
150
|
-
end case;
|
151
|
-
return std_ulogic_vector(ret);
|
152
|
-
end function sign_extend;
|
153
|
-
end helpers;
|