vertigo_vhdl 0.8.5 → 0.8.10

data/tests/parser_tests/test_fsm_pp.vhd

@@ -1,125 +0,0 @@
--- generated by Vertigo VHDL tool
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
- 
-entity fsm is
-  port(
-    reset_n : in std_logic;
-    clk : in std_logic;
-    switches : in std_logic_vector(7 downto 0);
-    leds : out std_logic_vector(7 downto 0));
-end entity fsm;
- 
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-architecture rtl of fsm is
-  signal wrap_reset_n : std_logic;
-  signal wrap_clk : std_logic;
-  signal wrap_switches : std_logic_vector(7 downto 0);
-  signal wrap_leds : std_logic_vector(7 downto 0);
-  signal state : std_logic_vector(2 downto 0);
-  signal state_c : std_logic_vector(2 downto 0);
-  signal n4_o : std_logic;
-  signal n9_q : std_logic_vector(2 downto 0);
-  signal n12_o : std_logic;
-  signal n14_o : std_logic_vector(2 downto 0);
-  signal n15_o : std_logic;
-  signal n17_o : std_logic_vector(2 downto 0);
-  signal n18_o : std_logic;
-  signal n20_o : std_logic_vector(2 downto 0);
-  signal n21_o : std_logic;
-  signal n23_o : std_logic_vector(2 downto 0);
-  signal n24_o : std_logic;
-  signal n26_o : std_logic_vector(2 downto 0);
-  signal n27_o : std_logic;
-  signal n29_o : std_logic_vector(2 downto 0);
-  signal n30_o : std_logic;
-  signal n32_o : std_logic_vector(2 downto 0);
-  signal n33_o : std_logic;
-  signal n35_o : std_logic_vector(2 downto 0);
-  signal n36_o : std_logic_vector(1 downto 0);
-  signal n37_o : std_logic_vector(2 downto 0);
-  signal n38_o : std_logic_vector(2 downto 0);
-  signal n39_o : std_logic;
-  signal n40_o : std_logic_vector(2 downto 0);
-  signal n44_o : std_logic;
-  signal n45_o : std_logic_vector(7 downto 0);
-  signal n48_o : std_logic;
-  signal n49_o : std_logic_vector(7 downto 0);
-  signal n52_o : std_logic;
-  signal n53_o : std_logic_vector(7 downto 0);
-  signal n56_o : std_logic;
-  signal n57_o : std_logic_vector(7 downto 0);
-  signal n60_o : std_logic;
-  signal n61_o : std_logic_vector(7 downto 0);
-  signal n64_o : std_logic;
-  signal n65_o : std_logic_vector(7 downto 0);
-  signal n68_o : std_logic;
-  signal n69_o : std_logic_vector(7 downto 0);
-begin
- 
-  wrap_reset_n <= reset_n;
-  wrap_clk <= clk;
-  wrap_switches <= switches;
-  leds <= wrap_leds;
-  wrap_leds <= n45_o;
-  state <= n9_q;
-  state_c <= n40_o;
-  n4_o <= wrap_reset_n;
-   
-  process(wrap_clk,n4_o)
-  begin
-    if n4_o = '1' then
-      n9_q <= "000";
-    elsif rising_edge(wrap_clk) then
-      n9_q <= state_c;
-    end if;
-  end process;
-  n12_o <= wrap_switches(0);
-  n14_o <= state when n12_o = '0' else  "001";
-  n15_o <= wrap_switches(1);
-  n17_o <= state when n15_o = '0' else  "010";
-  n18_o <= wrap_switches(2);
-  n20_o <= state when n18_o = '0' else  "011";
-  n21_o <= wrap_switches(3);
-  n23_o <= state when n21_o = '0' else  "100";
-  n24_o <= wrap_switches(4);
-  n26_o <= state when n24_o = '0' else  "101";
-  n27_o <= wrap_switches(5);
-  n29_o <= state when n27_o = '0' else  "110";
-  n30_o <= wrap_switches(6);
-  n32_o <= state when n30_o = '0' else  "111";
-  n33_o <= wrap_switches(7);
-  n35_o <= state when n33_o = '0' else  "000";
-  n36_o <= state(1 downto 0);
-  with n36_o select n37_o <=
-    n14_o when "00",
-    n17_o when "01",
-    n20_o when "10",
-    n23_o when "11",
-    "xxx" when others,;
-  with n36_o select n38_o <=
-    n26_o when "00",
-    n29_o when "01",
-    n32_o when "10",
-    n35_o when "11",
-    "xxx" when others,;
-  n39_o <= state(2);
-  n40_o <= n37_o when n39_o = '0' else  n38_o;
-  n44_o <= '1' when state = "000" else  '0';
-  n45_o <= n49_o when n44_o = '0' else  "00000000";
-  n48_o <= '1' when state = "001" else  '0';
-  n49_o <= n53_o when n48_o = '0' else  "00000001";
-  n52_o <= '1' when state = "010" else  '0';
-  n53_o <= n57_o when n52_o = '0' else  "00000010";
-  n56_o <= '1' when state = "011" else  '0';
-  n57_o <= n61_o when n56_o = '0' else  "00000011";
-  n60_o <= '1' when state = "100" else  '0';
-  n61_o <= n65_o when n60_o = '0' else  "00000100";
-  n64_o <= '1' when state = "101" else  '0';
-  n65_o <= n69_o when n64_o = '0' else  "00000101";
-  n68_o <= '1' when state = "110" else  '0';
-  n69_o <= "00000111" when n68_o = '0' else  "00000110";
-end rtl;

data/tests/parser_tests/test_fsm_synth_pp.vhd

@@ -1,197 +0,0 @@
--- generated by Vertigo VHDL tool
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
- 
-entity fsm is
-  port(
-    reset_n : in std_logic;
-    clk : in std_logic;
-    switches : in std_logic_vector(7 downto 0);
-    leds : out std_logic_vector(7 downto 0);
-    o1 : out std_logic;
-    o2 : out std_logic;
-    o3 : out unsigned(3 downto 0));
-end entity fsm;
- 
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-architecture rtl of fsm is
-  signal wrap_reset_n : std_logic;
-  signal wrap_clk : std_logic;
-  signal wrap_switches : std_logic_vector(7 downto 0);
-  signal wrap_leds : std_logic_vector(7 downto 0);
-  signal wrap_o1 : std_logic;
-  signal wrap_o2 : std_logic;
-  signal wrap_o3 : std_logic_vector(3 downto 0);
-  signal state : std_logic_vector(2 downto 0);
-  signal state_c : std_logic_vector(2 downto 0);
-  signal c3 : std_logic_vector(3 downto 0);
-  signal n7_o : std_logic;
-  signal n12_q : std_logic_vector(2 downto 0);
-  signal n17_o : std_logic;
-  signal n19_o : std_logic_vector(2 downto 0);
-  signal n20_o : std_logic;
-  signal n22_o : std_logic_vector(2 downto 0);
-  signal n23_o : std_logic;
-  signal n25_o : std_logic_vector(2 downto 0);
-  signal n26_o : std_logic;
-  signal n28_o : std_logic_vector(2 downto 0);
-  signal n29_o : std_logic;
-  signal n31_o : std_logic_vector(2 downto 0);
-  signal n32_o : std_logic;
-  signal n35_o : std_logic;
-  signal n36_o : std_logic_vector(2 downto 0);
-  signal n37_o : std_logic;
-  signal n40_o : std_logic;
-  signal n41_o : std_logic_vector(2 downto 0);
-  signal n42_o : std_logic;
-  signal n44_o : std_logic_vector(2 downto 0);
-  signal n45_o : std_logic_vector(1 downto 0);
-  signal n46_o : std_logic;
-  signal n47_o : std_logic;
-  signal n48_o : std_logic;
-  signal n49_o : std_logic;
-  signal n50_o : std_logic_vector(1 downto 0);
-  signal n51_o : std_logic;
-  signal n52_o : std_logic;
-  signal n53_o : std_logic;
-  signal n54_o : std_logic;
-  signal n55_o : std_logic_vector(1 downto 0);
-  signal n56_o : std_logic_vector(2 downto 0);
-  signal n57_o : std_logic_vector(2 downto 0);
-  signal n58_o : std_logic;
-  signal n59_o : std_logic_vector(2 downto 0);
-  signal n63_o : std_logic;
-  signal n64_o : std_logic_vector(7 downto 0);
-  signal n67_o : std_logic;
-  signal n68_o : std_logic_vector(7 downto 0);
-  signal n71_o : std_logic;
-  signal n72_o : std_logic_vector(7 downto 0);
-  signal n75_o : std_logic;
-  signal n76_o : std_logic_vector(7 downto 0);
-  signal n79_o : std_logic;
-  signal n80_o : std_logic_vector(7 downto 0);
-  signal n83_o : std_logic;
-  signal n84_o : std_logic_vector(7 downto 0);
-  signal n87_o : std_logic;
-  signal n88_o : std_logic_vector(7 downto 0);
-  signal n92_o : std_logic;
-  signal n96_o : std_logic_vector(3 downto 0);
-  signal n99_q : std_logic_vector(3 downto 0);
-begin
- 
-  wrap_reset_n <= reset_n;
-  wrap_clk <= clk;
-  wrap_switches <= switches;
-  leds <= wrap_leds;
-  o1 <= wrap_o1;
-  o2 <= wrap_o2;
-  o3 <= unsigned(wrap_o3);
-  wrap_leds <= n64_o;
-  wrap_o1 <= n49_o;
-  wrap_o2 <= n54_o;
-  wrap_o3 <= c3;
-  state <= n12_q;
-  state_c <= n59_o;
-  c3 <= n99_q;
-  n7_o <= wrap_reset_n;
-   
-  process(wrap_clk,n7_o)
-  begin
-    if n7_o = '1' then
-      n12_q <= "000";
-    elsif rising_edge(wrap_clk) then
-      n12_q <= state_c;
-    end if;
-  end process;
-  n17_o <= wrap_switches(0);
-  n19_o <= state when n17_o = '0' else  "001";
-  n20_o <= wrap_switches(1);
-  n22_o <= state when n20_o = '0' else  "010";
-  n23_o <= wrap_switches(2);
-  n25_o <= state when n23_o = '0' else  "011";
-  n26_o <= wrap_switches(3);
-  n28_o <= state when n26_o = '0' else  "100";
-  n29_o <= wrap_switches(4);
-  n31_o <= state when n29_o = '0' else  "101";
-  n32_o <= wrap_switches(5);
-  n35_o <= '0' when n32_o = '0' else  '1';
-  n36_o <= state when n32_o = '0' else  "110";
-  n37_o <= wrap_switches(6);
-  n40_o <= '1' when n37_o = '0' else  '1';
-  n41_o <= state when n37_o = '0' else  "111";
-  n42_o <= wrap_switches(7);
-  n44_o <= state when n42_o = '0' else  "000";
-  n45_o <= state(1 downto 0);
-  with n45_o select n46_o <=
-    '0' when "00",
-    '0' when "01",
-    '0' when "10",
-    '0' when "11",
-    'x' when others,;
-  with n45_o select n47_o <=
-    '0' when "00",
-    n35_o when "01",
-    '0' when "10",
-    '0' when "11",
-    'x' when others,;
-  n48_o <= state(2);
-  n49_o <= n46_o when n48_o = '0' else  n47_o;
-  n50_o <= state(1 downto 0);
-  with n50_o select n51_o <=
-    '1' when "00",
-    '1' when "01",
-    '1' when "10",
-    '1' when "11",
-    'x' when others,;
-  with n50_o select n52_o <=
-    '1' when "00",
-    '1' when "01",
-    n40_o when "10",
-    '1' when "11",
-    'x' when others,;
-  n53_o <= state(2);
-  n54_o <= n51_o when n53_o = '0' else  n52_o;
-  n55_o <= state(1 downto 0);
-  with n55_o select n56_o <=
-    n19_o when "00",
-    n22_o when "01",
-    n25_o when "10",
-    n28_o when "11",
-    "xxx" when others,;
-  with n55_o select n57_o <=
-    n31_o when "00",
-    n36_o when "01",
-    n41_o when "10",
-    n44_o when "11",
-    "xxx" when others,;
-  n58_o <= state(2);
-  n59_o <= n56_o when n58_o = '0' else  n57_o;
-  n63_o <= '1' when state = "000" else  '0';
-  n64_o <= n68_o when n63_o = '0' else  "00000000";
-  n67_o <= '1' when state = "001" else  '0';
-  n68_o <= n72_o when n67_o = '0' else  "00000001";
-  n71_o <= '1' when state = "010" else  '0';
-  n72_o <= n76_o when n71_o = '0' else  "00000010";
-  n75_o <= '1' when state = "011" else  '0';
-  n76_o <= n80_o when n75_o = '0' else  "00000011";
-  n79_o <= '1' when state = "100" else  '0';
-  n80_o <= n84_o when n79_o = '0' else  "00000100";
-  n83_o <= '1' when state = "101" else  '0';
-  n84_o <= n88_o when n83_o = '0' else  "00000101";
-  n87_o <= '1' when state = "110" else  '0';
-  n88_o <= "00000111" when n87_o = '0' else  "00000110";
-  n92_o <= wrap_reset_n;
-  n96_o <= std_logic_vector(unsigned(c3) + unsigned'("0001"));
-   
-  process(wrap_clk,n92_o)
-  begin
-    if n92_o = '1' then
-      n99_q <= "0000";
-    elsif rising_edge(wrap_clk) then
-      n99_q <= n96_o;
-    end if;
-  end process;
-end rtl;

data/tests/parser_tests/test_function-01_pp.vhd

@@ -1,18 +0,0 @@
--- generated by Vertigo VHDL tool
-package body lfsr_pkg is
-   
-  function many_to_one_fb(data : std_logic_vector;taps : std_logic_vector) return std_logic_vector is
-    variable xor_taps : std_logic;
-    variable all_0s : std_logic;
-    variable feedback : std_logic;
-  begin
-    if (data(data'length - 2 downto 0) = 0) then
-      all_0s := '1';
-    else
-      all_0s := '0';
-    end if;
-    xor_taps := '0';
-    feedback := xor_taps xor all_0s;
-    return data((data'length - 2) downto 0) & feedback;
-  end function many_to_one_fb;
-end lfsr_pkg;

data/tests/parser_tests/test_lfsr_pp.vhd

@@ -1,44 +0,0 @@
--- generated by Vertigo VHDL tool
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
- 
-package lfsr_pkg is
-  function many_to_one_fb(data : std_logic_vector;taps : std_logic_vector) return std_logic_vector
-  function one_to_many_fb(data : std_logic_vector;taps : std_logic_vector) return std_logic_vector
- 
-end lfsr_pkg;
- 
-package body lfsr_pkg is
-   
-  function many_to_one_fb(data : std_logic_vector;taps : std_logic_vector) return std_logic_vector is
-    variable xor_taps : std_logic;
-    variable all_0s : std_logic;
-    variable feedback : std_logic;
-  begin
-    if (data(data'length - 2 downto 0) = 0) then
-      all_0s := '1';
-    else
-      all_0s := '0';
-    end if;
-    xor_taps := '0';
-    feedback := xor_taps xor all_0s;
-    return data((data'length - 2) downto 0) & feedback;
-  end function many_to_one_fb;
-   
-  function one_to_many_fb(data : std_logic_vector;taps : std_logic_vector) return std_logic_vector is
-    variable xor_taps : std_logic;
-    variable all_0s : std_logic;
-    variable feedback : std_logic;
-    variable result : std_logic_vector(data'length - 1 downto 0);
-  begin
-    if (data(data'length - 2 downto 0) = 0) then
-      all_0s := '1';
-    else
-      all_0s := '0';
-    end if;
-    feedback := data(data'length - 1) xor all_0s;
-    result(0) := feedback;
-    return result;
-  end function one_to_many_fb;
-end lfsr_pkg;

data/tests/parser_tests/test_microwatt_cache_ram_pp.vhd

@@ -1,68 +0,0 @@
--- generated by Vertigo VHDL tool
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-use ieee.math_real.all;
- 
-entity cache_ram is
-  generic(
-    row_bits : integer16 := 16;
-    width : integer64 := 64;
-    trace : booleanfalse := false;
-    add_buf : booleanfalse := false);
-  port(
-    clk : in std_logic;
-    rd_en : in std_logic;
-    rd_addr : in std_logic_vector(row_bits - 1 downto 0);
-    rd_data : out std_logic_vector(width - 1 downto 0);
-    wr_en : in std_logic;
-    wr_sel : in std_logic_vector(width / 8 - 1 downto 0);
-    wr_addr : in std_logic_vector(row_bits - 1 downto 0);
-    wr_data : in std_logic_vector(width - 1 downto 0));
-end entity cache_ram;
- 
-architecture rtl of cache_ram is
-  constant size : integer := 2 ** row_bits;
-   
-  type ram_type is array(range 0 to size - 1) of std_logic_vector(width - 1 downto 0);
-  signal ram : ram_type;
-  attribute ram_style : string;
-  attribute ram_style of ram : signal is "block";
-  attribute ram_decomp : string;
-  attribute ram_decomp of ram : signal is "power";
-  signal rd_data0 : std_logic_vector(width - 1 downto 0);
-begin
- 
-   
-  process(clk)
-    variable lbit : integer range 0 to width - 1;
-    variable mbit : integer range 0 to width - 1;
-    variable widx : integer range 0 to size - 1;
-  begin
-    if rising_edge(clk) then
-      if wr_en = '1' then
-        if trace then
-          report "write a:" & to_hstring(wr_addr) & " sel:" & to_hstring(wr_sel) & " dat:" & to_hstring(wr_data);
-        end if;
-      end if;
-      if rd_en = '1' then
-        rd_data0 <= ram(to_integer(unsigned(rd_addr)));
-        if trace then
-          report "read a:" & to_hstring(rd_addr) & " dat:" & to_hstring(ram(to_integer(unsigned(rd_addr))));
-        end if;
-      end if;
-    end if;
-  end process;
-  if add_buf generate
-     
-    process(clk)
-    begin
-      if rising_edge(clk) then
-        rd_data <= rd_data0;
-      end if;
-    end process;
-  end generate;
-  if add_buf generate
-    rd_data <= rd_data0;
-  end generate;
-end rtl;