vertigo_vhdl 0.8.5 → 0.8.10

data/tests/parser_tests/test_microwatt_common_pp.vhd

@@ -1,336 +0,0 @@
--- generated by Vertigo VHDL tool
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-library work;
-use work.decode_types.all;
- 
-package common is
-   
-  subtype spr_num_t is integer range 0 to 1023;
-  function decode_spr_num(insn : std_ulogic_vector(31 downto 0)) return spr_num_t
-  constant spr_xer : spr_num_t := 1;
-  constant spr_lr : spr_num_t := 8;
-  constant spr_ctr : spr_num_t := 9;
-  constant spr_tb : spr_num_t := 268;
-  constant spr_dec : spr_num_t := 22;
-  constant spr_srr0 : spr_num_t := 26;
-  constant spr_srr1 : spr_num_t := 27;
-  constant spr_hsrr0 : spr_num_t := 314;
-  constant spr_hsrr1 : spr_num_t := 315;
-  constant spr_sprg0 : spr_num_t := 272;
-  constant spr_sprg1 : spr_num_t := 273;
-  constant spr_sprg2 : spr_num_t := 274;
-  constant spr_sprg3 : spr_num_t := 275;
-  constant spr_sprg3u : spr_num_t := 259;
-  constant spr_hsprg0 : spr_num_t := 304;
-  constant spr_hsprg1 : spr_num_t := 305;
-   
-  subtype gpr_index_t is std_ulogic_vector(4 downto 0);
-   
-  subtype gspr_index_t is std_ulogic_vector(5 downto 0);
-  function fast_spr_num(spr : spr_num_t) return gspr_index_t
-  function gspr_to_gpr(i : gspr_index_t) return gpr_index_t
-  function gpr_to_gspr(i : gpr_index_t) return gspr_index_t
-  function gpr_or_spr_to_gspr(g : gpr_index_t;s : gspr_index_t) return gspr_index_t
-  function is_fast_spr(s : gspr_index_t) return std_ulogic
-   
-  type xer_common_t is record
-    ca : std_ulogic;
-    ca32 : std_ulogic;
-    ov : std_ulogic;
-    ov32 : std_ulogic;
-    so : std_ulogic;
-  end record;
-  constant xerc_init : xer_common_t := (others => '0');
-   
-  type irq_state_t is (write_srr0,write_srr1);
-   
-  type ctrl_t is record
-    tb : std_ulogic_vector(63 downto 0);
-    dec : std_ulogic_vector(63 downto 0);
-    msr : std_ulogic_vector(63 downto 0);
-    irq_state : irq_state_t;
-    irq_nia : std_ulogic_vector(63 downto 0);
-    srr1 : std_ulogic_vector(63 downto 0);
-  end record;
-   
-  type fetch1toicachetype is record
-    req : std_ulogic;
-    stop_mark : std_ulogic;
-    nia : std_ulogic_vector(63 downto 0);
-  end record;
-   
-  type icachetofetch2type is record
-    valid : std_ulogic;
-    stop_mark : std_ulogic;
-    nia : std_ulogic_vector(63 downto 0);
-    insn : std_ulogic_vector(31 downto 0);
-  end record;
-   
-  type fetch2todecode1type is record
-    valid : std_ulogic;
-    stop_mark : std_ulogic;
-    nia : std_ulogic_vector(63 downto 0);
-    insn : std_ulogic_vector(31 downto 0);
-  end record;
-  constant fetch2todecode1init : fetch2todecode1type := (valid => '0',stop_mark => '0',others => (others => '0'));
-   
-  type decode1todecode2type is record
-    valid : std_ulogic;
-    stop_mark : std_ulogic;
-    nia : std_ulogic_vector(63 downto 0);
-    insn : std_ulogic_vector(31 downto 0);
-    ispr1 : gspr_index_t;
-    ispr2 : gspr_index_t;
-    decode : decode_rom_t;
-  end record;
-  constant decode1todecode2init : decode1todecode2type := (valid => '0',stop_mark => '0',decode => decode_rom_init,others => (others => '0'));
-   
-  type decode2toexecute1type is record
-    valid : std_ulogic;
-    insn_type : insn_type_t;
-    nia : std_ulogic_vector(63 downto 0);
-    write_reg : gspr_index_t;
-    read_reg1 : gspr_index_t;
-    read_reg2 : gspr_index_t;
-    read_data1 : std_ulogic_vector(63 downto 0);
-    read_data2 : std_ulogic_vector(63 downto 0);
-    read_data3 : std_ulogic_vector(63 downto 0);
-    bypass_data1 : std_ulogic;
-    bypass_data2 : std_ulogic;
-    bypass_data3 : std_ulogic;
-    cr : std_ulogic_vector(31 downto 0);
-    xerc : xer_common_t;
-    lr : std_ulogic;
-    rc : std_ulogic;
-    oe : std_ulogic;
-    invert_a : std_ulogic;
-    invert_out : std_ulogic;
-    input_carry : carry_in_t;
-    output_carry : std_ulogic;
-    input_cr : std_ulogic;
-    output_cr : std_ulogic;
-    is_32bit : std_ulogic;
-    is_signed : std_ulogic;
-    insn : std_ulogic_vector(31 downto 0);
-    data_len : std_ulogic_vector(3 downto 0);
-    byte_reverse : std_ulogic;
-    sign_extend : std_ulogic;
-    update : std_ulogic;
-    reserve : std_ulogic;
-  end record;
-  constant decode2toexecute1init : decode2toexecute1type := (valid => '0',insn_type => op_illegal,bypass_data1 => '0',bypass_data2 => '0',bypass_data3 => '0',lr => '0',rc => '0',oe => '0',invert_a => '0',invert_out => '0',input_carry => zero,output_carry => '0',input_cr => '0',output_cr => '0',is_32bit => '0',is_signed => '0',xerc => xerc_init,reserve => '0',byte_reverse => '0',sign_extend => '0',update => '0',others => (others => '0'));
-   
-  type execute1tomultiplytype is record
-    valid : std_ulogic;
-    insn_type : insn_type_t;
-    data1 : std_ulogic_vector(64 downto 0);
-    data2 : std_ulogic_vector(64 downto 0);
-    is_32bit : std_ulogic;
-  end record;
-  constant execute1tomultiplyinit : execute1tomultiplytype := (valid => '0',insn_type => op_illegal,is_32bit => '0',others => (others => '0'));
-   
-  type execute1todividertype is record
-    valid : std_ulogic;
-    dividend : std_ulogic_vector(63 downto 0);
-    divisor : std_ulogic_vector(63 downto 0);
-    is_signed : std_ulogic;
-    is_32bit : std_ulogic;
-    is_extended : std_ulogic;
-    is_modulus : std_ulogic;
-    neg_result : std_ulogic;
-  end record;
-  constant execute1todividerinit : execute1todividertype := (valid => '0',is_signed => '0',is_32bit => '0',is_extended => '0',is_modulus => '0',neg_result => '0',others => (others => '0'));
-   
-  type decode2toregisterfiletype is record
-    read1_enable : std_ulogic;
-    read1_reg : gspr_index_t;
-    read2_enable : std_ulogic;
-    read2_reg : gspr_index_t;
-    read3_enable : std_ulogic;
-    read3_reg : gpr_index_t;
-  end record;
-   
-  type registerfiletodecode2type is record
-    read1_data : std_ulogic_vector(63 downto 0);
-    read2_data : std_ulogic_vector(63 downto 0);
-    read3_data : std_ulogic_vector(63 downto 0);
-  end record;
-   
-  type decode2tocrfiletype is record
-    read : std_ulogic;
-  end record;
-   
-  type crfiletodecode2type is record
-    read_cr_data : std_ulogic_vector(31 downto 0);
-    read_xerc_data : xer_common_t;
-  end record;
-   
-  type execute1tofetch1type is record
-    redirect : std_ulogic;
-    redirect_nia : std_ulogic_vector(63 downto 0);
-  end record;
-  constant execute1tofetch1typeinit : execute1tofetch1type := (redirect => '0',others => (others => '0'));
-   
-  type execute1toloadstore1type is record
-    valid : std_ulogic;
-    load : std_ulogic;
-    addr1 : std_ulogic_vector(63 downto 0);
-    addr2 : std_ulogic_vector(63 downto 0);
-    data : std_ulogic_vector(63 downto 0);
-    write_reg : gpr_index_t;
-    length : std_ulogic_vector(3 downto 0);
-    ci : std_ulogic;
-    byte_reverse : std_ulogic;
-    sign_extend : std_ulogic;
-    update : std_ulogic;
-    update_reg : gpr_index_t;
-    xerc : xer_common_t;
-    reserve : std_ulogic;
-    rc : std_ulogic;
-  end record;
-  constant execute1toloadstore1init : execute1toloadstore1type := (valid => '0',load => '0',ci => '0',byte_reverse => '0',sign_extend => '0',update => '0',xerc => xerc_init,reserve => '0',rc => '0',others => (others => '0'));
-   
-  type loadstore1todcachetype is record
-    valid : std_ulogic;
-    load : std_ulogic;
-    nc : std_ulogic;
-    reserve : std_ulogic;
-    addr : std_ulogic_vector(63 downto 0);
-    data : std_ulogic_vector(63 downto 0);
-    byte_sel : std_ulogic_vector(7 downto 0);
-  end record;
-   
-  type dcachetoloadstore1type is record
-    valid : std_ulogic;
-    data : std_ulogic_vector(63 downto 0);
-    store_done : std_ulogic;
-    error : std_ulogic;
-  end record;
-   
-  type loadstore1towritebacktype is record
-    valid : std_ulogic;
-    write_enable : std_ulogic;
-    write_reg : gpr_index_t;
-    write_data : std_ulogic_vector(63 downto 0);
-    xerc : xer_common_t;
-    rc : std_ulogic;
-    store_done : std_ulogic;
-  end record;
-  constant loadstore1towritebackinit : loadstore1towritebacktype := (valid => '0',write_enable => '0',xerc => xerc_init,rc => '0',store_done => '0',others => (others => '0'));
-   
-  type execute1towritebacktype is record
-    valid : std_ulogic;
-    rc : std_ulogic;
-    write_enable : std_ulogic;
-    write_reg : gspr_index_t;
-    write_data : std_ulogic_vector(63 downto 0);
-    write_cr_enable : std_ulogic;
-    write_cr_mask : std_ulogic_vector(7 downto 0);
-    write_cr_data : std_ulogic_vector(31 downto 0);
-    write_xerc_enable : std_ulogic;
-    xerc : xer_common_t;
-  end record;
-  constant execute1towritebackinit : execute1towritebacktype := (valid => '0',rc => '0',write_enable => '0',write_cr_enable => '0',write_xerc_enable => '0',xerc => xerc_init,others => (others => '0'));
-   
-  type multiplytoexecute1type is record
-    valid : std_ulogic;
-    write_reg_data : std_ulogic_vector(63 downto 0);
-    overflow : std_ulogic;
-  end record;
-  constant multiplytoexecute1init : multiplytoexecute1type := (valid => '0',overflow => '0',others => (others => '0'));
-   
-  type dividertoexecute1type is record
-    valid : std_ulogic;
-    write_reg_data : std_ulogic_vector(63 downto 0);
-    overflow : std_ulogic;
-  end record;
-  constant dividertoexecute1init : dividertoexecute1type := (valid => '0',overflow => '0',others => (others => '0'));
-   
-  type writebacktoregisterfiletype is record
-    write_reg : gspr_index_t;
-    write_data : std_ulogic_vector(63 downto 0);
-    write_enable : std_ulogic;
-  end record;
-  constant writebacktoregisterfileinit : writebacktoregisterfiletype := (write_enable => '0',others => (others => '0'));
-   
-  type writebacktocrfiletype is record
-    write_cr_enable : std_ulogic;
-    write_cr_mask : std_ulogic_vector(7 downto 0);
-    write_cr_data : std_ulogic_vector(31 downto 0);
-    write_xerc_enable : std_ulogic;
-    write_xerc_data : xer_common_t;
-  end record;
-  constant writebacktocrfileinit : writebacktocrfiletype := (write_cr_enable => '0',write_xerc_enable => '0',write_xerc_data => xerc_init,others => (others => '0'));
- 
-end common;
- 
-package body common is
-   
-  function decode_spr_num(insn : std_ulogic_vector(31 downto 0)) return spr_num_t is
-  begin
-    return to_integer(unsigned(insn(15 downto 11) & insn(20 downto 16)));
-  end function decode_spr_num;
-   
-  function fast_spr_num(spr : spr_num_t) return gspr_index_t is
-    variable n : integer range 0 to 31;
-  begin
-    case spr is
-      when spr_lr =>
-        n := 0;
-      when spr_ctr =>
-        n := 1;
-      when spr_srr0 =>
-        n := 2;
-      when spr_srr1 =>
-        n := 3;
-      when spr_hsrr0 =>
-        n := 4;
-      when spr_hsrr1 =>
-        n := 5;
-      when spr_sprg0 =>
-        n := 6;
-      when spr_sprg1 =>
-        n := 7;
-      when spr_sprg2 =>
-        n := 8;
-      when spr_sprg3 | spr_sprg3u =>
-        n := 9;
-      when spr_hsprg0 =>
-        n := 10;
-      when spr_hsprg1 =>
-        n := 11;
-      when spr_xer =>
-        n := 12;
-      when others =>
-        n := 0;
-        return "000000";
-    end case;
-    return "1" & std_ulogic_vector(to_unsigned(n,5));
-  end function fast_spr_num;
-   
-  function gspr_to_gpr(i : gspr_index_t) return gpr_index_t is
-  begin
-    return i(4 downto 0);
-  end function gspr_to_gpr;
-   
-  function gpr_to_gspr(i : gpr_index_t) return gspr_index_t is
-  begin
-    return "0" & i;
-  end function gpr_to_gspr;
-   
-  function gpr_or_spr_to_gspr(g : gpr_index_t;s : gspr_index_t) return gspr_index_t is
-  begin
-    if s(5) = '1' then
-      return s;
-    else
-      return gpr_to_gspr(g);
-    end if;
-  end function gpr_or_spr_to_gspr;
-   
-  function is_fast_spr(s : gspr_index_t) return std_ulogic is
-  begin
-    return s(5);
-  end function is_fast_spr;
-end common;

data/tests/parser_tests/test_microwatt_control_pp.vhd

@@ -1,187 +0,0 @@
--- generated by Vertigo VHDL tool
-library ieee;
-use ieee.std_logic_1164.all;
-library work;
-use work.common.all;
- 
-entity control is
-  generic(
-    pipeline_depth : natural2 := 2);
-  port(
-    clk : in std_ulogic;
-    rst : in std_ulogic;
-    complete_in : in std_ulogic;
-    valid_in : in std_ulogic;
-    flush_in : in std_ulogic;
-    stall_in : in std_ulogic;
-    sgl_pipe_in : in std_ulogic;
-    stop_mark_in : in std_ulogic;
-    gpr_write_valid_in : in std_ulogic;
-    gpr_write_in : in gspr_index_t;
-    gpr_bypassable : in std_ulogic;
-    gpr_a_read_valid_in : in std_ulogic;
-    gpr_a_read_in : in gspr_index_t;
-    gpr_b_read_valid_in : in std_ulogic;
-    gpr_b_read_in : in gspr_index_t;
-    gpr_c_read_valid_in : in std_ulogic;
-    gpr_c_read_in : in gpr_index_t;
-    cr_read_in : in std_ulogic;
-    cr_write_in : in std_ulogic;
-    valid_out : out std_ulogic;
-    stall_out : out std_ulogic;
-    stopped_out : out std_ulogic;
-    gpr_bypass_a : out std_ulogic;
-    gpr_bypass_b : out std_ulogic;
-    gpr_bypass_c : out std_ulogic);
-end entity control;
- 
-architecture rtl of control is
-   
-  type state_type is (idle,wait_for_prev_to_complete,wait_for_curr_to_complete);
-   
-  type reg_internal_type is record
-    state : state_type;
-    outstanding : integer range 1 to pipeline_depth + 2;
-  end record;
-  constant reg_internal_init : reg_internal_type := (state => idle,outstanding => 0);
-  signal r_int : reg_internal_type;
-  signal rin_int : reg_internal_type := reg_internal_init;
-  signal stall_a_out : std_ulogic;
-  signal stall_b_out : std_ulogic;
-  signal stall_c_out : std_ulogic;
-  signal cr_stall_out : std_ulogic;
-  signal gpr_write_valid : std_ulogic := '0';
-  signal cr_write_valid : std_ulogic := '0';
-  signal gpr_c_read_in_fmt : std_ulogic_vector(5 downto 0);
-begin
- 
-  gpr_hazard0 : entity work.gpr_hazard
-    port map(
-      clk => clk,
-      stall_in => stall_in,
-      gpr_write_valid_in => gpr_write_valid,
-      gpr_write_in => gpr_write_in,
-      bypass_avail => gpr_bypassable,
-      gpr_read_valid_in => gpr_a_read_valid_in,
-      gpr_read_in => gpr_a_read_in,
-      stall_out => stall_a_out,
-      use_bypass => gpr_bypass_a);
-   
-  gpr_hazard1 : entity work.gpr_hazard
-    port map(
-      clk => clk,
-      stall_in => stall_in,
-      gpr_write_valid_in => gpr_write_valid,
-      gpr_write_in => gpr_write_in,
-      bypass_avail => gpr_bypassable,
-      gpr_read_valid_in => gpr_b_read_valid_in,
-      gpr_read_in => gpr_b_read_in,
-      stall_out => stall_b_out,
-      use_bypass => gpr_bypass_b);
-   
-  gpr_c_read_in_fmt <= "0" & gpr_c_read_in;
-  gpr_hazard2 : entity work.gpr_hazard
-    port map(
-      clk => clk,
-      stall_in => stall_in,
-      gpr_write_valid_in => gpr_write_valid,
-      gpr_write_in => gpr_write_in,
-      bypass_avail => gpr_bypassable,
-      gpr_read_valid_in => gpr_c_read_valid_in,
-      gpr_read_in => gpr_c_read_in_fmt,
-      stall_out => stall_c_out,
-      use_bypass => gpr_bypass_c);
-   
-  cr_hazard0 : entity work.cr_hazard
-    port map(
-      clk => clk,
-      stall_in => stall_in,
-      cr_read_in => cr_read_in,
-      cr_write_in => cr_write_valid,
-      stall_out => cr_stall_out);
-   
-   
-  control0 : process(clk)
-  begin
-    if rising_edge(clk) then
-      assert r_int.outstanding >= 0 and r_int.outstanding <= (pipeline_depth + 1)
-        report "outstanding bad " & integer'image(r_int.outstanding) severity failure;
-      r_int <= rin_int;
-    end if;
-  end process;
-   
-  control1 : process(all)
-    variable v_int : reg_internal_type;
-    variable valid_tmp : std_ulogic;
-    variable stall_tmp : std_ulogic;
-  begin
-    v_int := r_int;
-    valid_tmp := valid_in and flush_in and stall_in;
-    stall_tmp := stall_in;
-    if complete_in = '1' then
-      v_int.outstanding := r_int.outstanding - 1;
-    end if;
-    stopped_out <= '0';
-    if stop_mark_in = '1' and v_int.outstanding = 0 then
-      stopped_out <= '1';
-    end if;
-    case r_int.state is
-      when idle =>
-        if valid_tmp = '1' then
-          if (sgl_pipe_in = '1') then
-            if v_int.outstanding /= 0 then
-              v_int.state := wait_for_prev_to_complete;
-              stall_tmp := '1';
-            else
-              v_int.state := wait_for_curr_to_complete;
-            end if;
-          else
-            stall_tmp := stall_a_out or stall_b_out or stall_c_out or cr_stall_out;
-          end if;
-        end if;
-      when wait_for_prev_to_complete =>
-        if v_int.outstanding = 0 then
-          v_int.state := wait_for_curr_to_complete;
-        else
-          stall_tmp := '1';
-        end if;
-      when wait_for_curr_to_complete =>
-        if v_int.outstanding = 0 then
-          v_int.state := idle;
-          if valid_tmp = '1' then
-            if (sgl_pipe_in = '1') then
-              if v_int.outstanding /= 0 then
-                v_int.state := wait_for_prev_to_complete;
-                stall_tmp := '1';
-              else
-                v_int.state := wait_for_curr_to_complete;
-              end if;
-            else
-              stall_tmp := stall_a_out or stall_b_out or stall_c_out or cr_stall_out;
-            end if;
-          end if;
-        else
-          stall_tmp := '1';
-        end if;
-    end case;
-    if stall_tmp = '1' then
-      valid_tmp := '0';
-    end if;
-    if valid_tmp = '1' then
-      v_int.outstanding := v_int.outstanding + 1;
-      gpr_write_valid <= gpr_write_valid_in;
-      cr_write_valid <= cr_write_in;
-    else
-      gpr_write_valid <= '0';
-      cr_write_valid <= '0';
-    end if;
-    if rst = '1' then
-      v_int.state := idle;
-      v_int.outstanding := 0;
-      stall_tmp := '0';
-    end if;
-    valid_out <= valid_tmp;
-    stall_out <= stall_tmp;
-    rin_int <= v_int;
-  end process;
-end rtl;