udb 0.1.17 → 0.1.18

data/.data/spec/std/isa/csr/mip.yaml

@@ -215,8 +215,7 @@ fields:
       * `hip.VSSIP`
       * `hvip.VSSIP`
       * `vsip.SSIP` when `hideleg.VSSI` is set
-    type(): |
-      return VSSI_INTR_IMPL ? CsrFieldType::RW : CsrFieldType::RO;
+    type: RW
     reset_value: 0
     definedBy:
       extension:
@@ -304,8 +303,7 @@ fields:
       * `hip.VSTIP`
       * `vsip.STIP` when `hideleg.VSTI` is set
       * `hvip.VSTIP` <% if ext?(:Sstc) %>when `menvcfg.STCE` is clear<% end %> (though `hvip.VSTIP` is writable)
-    type(): |
-      return VSTI_INTR_IMPL ? CsrFieldType::ROH : CsrFieldType::RO;
+    type: RO-H
     reset_value: 0
     definedBy:
       extension:
@@ -372,8 +370,7 @@ fields:
 
       * `hip.VSEIP`
       * `vsip.SEIP` when `hideleg.VSEI` is set
-    type(): |
-      return VSEI_INTR_IMPL ? CsrFieldType::ROH : CsrFieldType::RO;
+    type: RO-H
     reset_value: 0
     definedBy:
       extension:

data/.data/spec/std/isa/csr/misa.yaml

@@ -103,25 +103,6 @@ fields:
 
       # fall-through; write the intended value
       return csr_value.F;
-  G:
-    location: 6
-    description: |
-      Indicates support for all of the following extensions: `I`, `A`, `M`, `F`, `D`.
-    type(): |
-      if ((implemented?(ExtensionName::A) && MUTABLE_MISA_A) ||
-          (implemented?(ExtensionName::M) && MUTABLE_MISA_M) ||
-          (implemented?(ExtensionName::F) && MUTABLE_MISA_F) ||
-          (implemented?(ExtensionName::D) && MUTABLE_MISA_D)) {
-        return CsrFieldType::ROH;
-      } else {
-        return CsrFieldType::RO;
-      }
-    reset_value(): |
-      return (
-        implemented?(ExtensionName::A) &&
-        implemented?(ExtensionName::M) &&
-        implemented?(ExtensionName::F) &&
-        implemented?(ExtensionName::D)) ? 1 : 0;
   H:
     location: 7
     description: |
@@ -241,10 +222,9 @@ sw_read(): |
     (CSR[misa].S `<< 18) |
     (CSR[misa].Q `<< 16) |
     (CSR[misa].M `<< 12) |
-    (CSR[misa].I `<< 7) |
-    (CSR[misa].H `<< 6) |
-    ((CSR[misa].A & CSR[misa].M & CSR[misa].F & CSR[misa].D) `<< 5) | # 'G'
-    (CSR[misa].F `<< 4) |
+    (CSR[misa].I `<< 8) |
+    (CSR[misa].H `<< 7) |
+    (CSR[misa].F `<< 5) |
     (CSR[misa].D `<< 3) |
     (CSR[misa].C `<< 2) |
     (CSR[misa].B `<< 1) |

data/.data/spec/std/isa/csr/mseccfg.yaml

@@ -22,4 +22,30 @@ definedBy:
           - name: Smmpm
           - name: Zicfilp
           - name: Smepmp
-fields: {}
+fields:
+  USEED:
+    location: 8
+    description: |
+      Controls access to the `seed` CSR from U-mode.
+    definedBy:
+      extension:
+        allOf:
+          - name: Zkr
+          - name: U
+    type(): |
+      return USEED_READ_ONLY_ZERO ? CsrFieldType::RO : CsrFieldType::RW;
+    reset_value(): |
+      return USEED_READ_ONLY_ZERO ? 0 : UNDEFINED_LEGAL;
+  SSEED:
+    location: 9
+    description: |
+      Controls access to the `seed` CSR from S-mode and VS-mode.
+    definedBy:
+      extension:
+        allOf:
+          - name: Zkr
+          - name: S
+    type(): |
+      return SSEED_READ_ONLY_ZERO ? CsrFieldType::RO : CsrFieldType::RW;
+    reset_value(): |
+      return SSEED_READ_ONLY_ZERO ? 0 : UNDEFINED_LEGAL;

data/.data/spec/std/isa/csr/mstatus.yaml

@@ -607,7 +607,10 @@ fields:
       extension:
         name: S
     reset_value(): |
-      return (CSR[misa].S == 1'b1) ? UNDEFINED_LEGAL : 0;
+      if (CSR[misa].S == 1'b1) {
+        return UNDEFINED_LEGAL;
+      }
+      return 0;
   MIE:
     location: 3
     long_name: M-mode Interrupt Enable
@@ -644,4 +647,7 @@ fields:
       extension:
         name: S
     reset_value(): |
-      return (CSR[misa].S == 1'b1) ? UNDEFINED_LEGAL : 0;
+      if (CSR[misa].S == 1'b1) {
+        return UNDEFINED_LEGAL;
+      }
+      return 0;

data/.data/spec/std/isa/csr/scontext.yaml

@@ -18,10 +18,14 @@ description: |
   with a hypervisor that does not swap `scontext`.
 
 definedBy:
-  extension:
-    allOf:
-      - name: Sdtrig
-      - name: S
+  allOf:
+    - extension:
+        name: Sdtrig
+    - extension:
+        name: S
+    - param:
+        name: SCONTEXT_IMPLEMENTED
+        equal: true
 fields:
   DATA:
     location: 31-0

data/.data/spec/std/isa/csr/tcontrol.yaml

@@ -13,8 +13,12 @@ description: |
   This optional register is only accessible in M-mode and Debug Mode and provides
   various control bits related to triggers.
 definedBy:
-  extension:
-    name: Sdtrig
+  allOf:
+    - extension:
+        name: Sdtrig
+    - param:
+        name: TCONTROL_IMPLEMENTED
+        equal: true
 fields:
   MPTE:
     location: 7

data/.data/spec/std/isa/csr/tdata2.yaml

@@ -21,8 +21,12 @@ description: |
   If XLEN is less than DXLEN, writes to this register are sign-extended.
 
 definedBy:
-  extension:
-    name: Sdtrig
+  allOf:
+    - extension:
+        name: Sdtrig
+    - param:
+        name: TDATA2_IMPLEMENTED
+        equal: true
 fields:
   DATA:
     location_rv32: 31-0

data/.data/spec/std/isa/csr/tdata3.yaml

@@ -21,8 +21,12 @@ description: |
   If XLEN is less than DXLEN, writes to this register are sign-extended.
 
 definedBy:
-  extension:
-    name: Sdtrig
+  allOf:
+    - extension:
+        name: Sdtrig
+    - param:
+        name: TDATA3_IMPLEMENTED
+        equal: true
 fields:
   DATA:
     location_rv32: 31-0

data/.data/spec/std/isa/ext/Sdext.yaml

@@ -6,9 +6,65 @@
 $schema: "ext_schema.json#"
 kind: extension
 name: Sdext
-long_name: Debug
+long_name: External debug support
 description: |
-  Hart-visible portion of the debug spec.
+  Sdext is the hart-visible portion of the RISC-V Debug Specification. It
+  defines Debug Mode, the `dret` instruction, and the `dcsr`, `dpc`,
+  `dscratch0`, and `dscratch1` CSRs that allow an external debugger (via the
+  Debug Module) to halt, inspect, and resume a hart.
+
+  *Debug Mode*
+
+  Debug Mode is a special processor mode used only when a hart is halted for
+  external debugging. While in Debug Mode:
+
+  * All operations are executed with machine-mode privilege, except that
+    `mstatus.MPRV` is ignored unless `dcsr.MPRVEN` is set.
+  * Interrupts (including NMI) are not taken.
+  * Exceptions do not update any registers (including `mcause`, `mepc`, and
+    `mtval`); the hart instead returns to the Debug Module's park loop.
+  * Triggers do not fire.
+  * Counters and `time` may be stopped, as controlled by `dcsr.STOPCOUNT` and
+    `dcsr.STOPTIME`.
+  * The debug CSRs (`dcsr`, `dpc`, `dscratch0`, `dscratch1`) are accessible.
+    Accessing them outside of Debug Mode raises an Illegal Instruction
+    exception.
+
+  *Halting*
+
+  A hart enters Debug Mode (halts) in response to a halt request from the
+  debugger, a halt-on-reset request, an `ebreak` executed in a mode whose
+  `dcsr.EBREAK*` bit is set, a trigger with `action`=1, completion of a
+  single step, membership in a halt group, or (with Smdbltrp and
+  `dcsr.CETRIG`=1) a critical error. On entry:
+
+  . `dcsr.CAUSE` (and, where applicable, `dcsr.EXTCAUSE`) records why Debug
+    Mode was entered.
+  . `dcsr.PRV` and `dcsr.V` record the privilege and virtualization mode the
+    hart was in.
+  . `dpc` records the virtual address of the next instruction that would have
+    executed.
+  . If Zicfilp is implemented, `dcsr.PELP` records the current `ELP` state and
+    `ELP` is set to `NO_LP_EXPECTED`.
+
+  *Resuming*
+
+  The debugger resumes the hart by having it execute `dret` from Debug Mode.
+  On resume, the PC is set to `dpc`, the privilege and virtualization mode
+  are restored from `dcsr.PRV` and `dcsr.V`, `mstatus.MPRV` (and, with
+  Smdbltrp/Ssdbltrp, the double-trap bits) are cleared when returning to a
+  less-privileged mode, `ELP` is restored from `dcsr.PELP` when Zicfilp is
+  implemented, and the hart leaves Debug Mode. A debugger may write `dcsr`
+  and `dpc` before resuming to change where and in what mode execution
+  continues.
+
+  *Single step*
+
+  When `dcsr.STEP` is set and the hart resumes, it executes exactly one
+  instruction and then re-enters Debug Mode with `dcsr.CAUSE` = 4 (step). If
+  that instruction takes an exception, the hart enters Debug Mode
+  immediately after the PC is updated to the trap handler. `dcsr.STEPIE`
+  controls whether interrupts may be taken while single stepping.
 type: privileged
 versions:
   - version: "1.0.0"

data/.data/spec/std/isa/ext/Sm.yaml

@@ -62,8 +62,8 @@ versions:
         `pc` to `__x__tval`.
       - Specified relaxed constraints for implicit reads of non-idempotent regions.
   - version: "1.13.0"
-    state: frozen
-    ratification_date: 2023-12
+    state: ratified
+    ratification_date: 2024-10
     changes:
       - Redefined `misa`.MXL to be read-only, making MXLEN a constant.
       - Defined the `misa`.B field to reflect that the B extension has been

data/.data/spec/std/isa/ext/Smcdeleg.yaml

@@ -38,3 +38,10 @@ versions:
         company: Ventana Microsystems
       - name: John Hauser
         email: jh.riscv@jhauser.us
+requirements:
+  extension:
+    allOf:
+      - name: Ssccfg
+        version: ~> 1.0
+      - name: Sscsrind
+        version: ~> 1.0

data/.data/spec/std/isa/ext/Smmpm.yaml

@@ -14,3 +14,11 @@ versions:
   - version: "1.0.0"
     state: ratified
     ratification_date: 2024-10
+requirements:
+  allOf:
+    - param:
+        name: MXLEN
+        equal: 64
+    - extension:
+        name: Sm
+        version: ">= 1.12"

data/.data/spec/std/isa/ext/Smnpm.yaml

@@ -15,3 +15,22 @@ versions:
   - version: "1.0.0"
     state: ratified
     ratification_date: 2024-10
+requirements:
+  allOf:
+    - extension:
+        name: U
+    - if:
+        extension:
+          name: S
+      then:
+        param:
+          name: SXLEN
+          includes: 64
+    - if:
+        not:
+          extension:
+            name: S
+      then:
+        param:
+          name: UXLEN
+          includes: 64

data/.data/spec/std/isa/ext/Smpmpdeleg.yaml

@@ -0,0 +1,33 @@
+# Copyright (c) Shanghai Jiao Tong University
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../schemas/ext_schema.json
+
+$schema: "ext_schema.json#"
+kind: extension
+name: Smpmpdeleg
+type: privileged
+long_name: Machine PMP Delegation to SPMP
+description: |
+  The Smpmpdeleg extension provides the mpmpdeleg CSR, which controls how many
+  PMP entries are delegated to SPMP.
+
+  The mpmpdeleg CSR contains a pmpnum field in bits [6:0]. Let max_pmp be the
+  implementation's total number of PMP entries. Entries 0 through pmpnum-1
+  remain as PMP entries, while entries pmpnum through max_pmp-1 are delegated
+  to SPMP.
+
+  When pmpnum = 0, all entries are delegated to SPMP.
+  When pmpnum = max_pmp, no entries are delegated to SPMP.
+
+  Writes to SPMP CSRs are ignored when no entries are delegated to SPMP.
+versions:
+  - version: "1.0.0"
+    state: ratified
+    ratification_date: 2026-08
+    url: "https://github.com/riscv/riscv-spmp/tree/v1.0"
+requirements:
+  extension:
+    allOf:
+      - name: S
+      - name: Smcsrind

data/.data/spec/std/isa/ext/Ssccfg.yaml

@@ -14,3 +14,10 @@ versions:
     state: ratified
     ratification_date: 2024-03
     url: https://docs.google.com/document/d/1s-GeH5XpHBLzbQZucA8DPA7vvF7Xvf_nrPbrU2YLBcE/edit#heading=h.yyrgtolcaczx
+requirements:
+  extension:
+    allOf:
+      - name: Smcdeleg
+        version: ~> 1.0
+      - name: Sscsrind
+        version: ~> 1.0

data/.data/spec/std/isa/ext/Ssnpm.yaml

@@ -15,3 +15,11 @@ versions:
   - version: "1.0.0"
     state: ratified
     ratification_date: 2024-10
+requirements:
+  allOf:
+    - extension:
+        name: S
+        version: ">= 1.12"
+    - param:
+        name: UXLEN
+        includes: 64

data/.data/spec/std/isa/ext/Sspmp.yaml

@@ -0,0 +1,44 @@
+# Copyright (c) Shanghai Jiao Tong University
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../schemas/ext_schema.json
+
+$schema: "ext_schema.json#"
+kind: extension
+name: Sspmp
+type: privileged
+long_name: Supervisor Physical Memory Protection
+description: |
+  The Sspmp extension defines a Supervisor-level Physical Memory Protection (SPMP)
+  mechanism that allows S-mode software to configure memory protection regions.
+
+  SPMP entries are accessed indirectly via the Sscsrind/Smcsrind extension.
+  The siselect CSR selects the SPMP entry (0x100-0x13F), and sireg/sireg2 access
+  the corresponding spmpaddr/spmpcfg values.
+
+  SPMP provides memory protection for S-mode and U-mode accesses when satp.MODE
+  is Bare. It does not apply when virtual memory translation is active.
+
+  Key behaviors:
+
+  * SPMP entries are delegated from PMP entries via the mpmpdeleg CSR.
+  * Each SPMP entry has address (spmpaddr) and configuration (spmpcfg) registers
+  * spmpcfg includes R, W, X permissions, address matching mode (A), lock bit (L),
+    U-mode bit (U), and SHARED bit
+  * Out-of-bounds siselect values read as 0 and writes are ignored
+versions:
+  - version: "1.0.0"
+    state: ratified
+    ratification_date: 2026-08
+    url: "https://github.com/riscv/riscv-spmp/tree/v1.0"
+requirements:
+  allOf:
+    - extension:
+        name: Sscsrind
+    - anyOf:
+      - not:
+          extension:
+            name: Sm
+            version: "~> 1.13"
+      - extension:
+          name: Smpmpdeleg

data/.data/spec/std/isa/ext/Sspmpen.yaml

@@ -0,0 +1,30 @@
+# Copyright (c) Shanghai Jiao Tong University
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../schemas/ext_schema.json
+
+$schema: "ext_schema.json#"
+kind: extension
+name: Sspmpen
+type: privileged
+long_name: SPMP Enable Register
+description: |
+  The Sspmpen extension adds the spmpen CSR, which provides per-entry enable bits
+  for SPMP regions.
+
+  Each bit spmpen[i] controls whether SPMP entry i is active. An entry is active
+  only when both spmpen[i] is set and spmpcfg[i].A != 0 (address matching mode
+  is not OFF).
+
+  When spmpcfg[i].L (lock bit) is set, spmpen[i] becomes read-only.
+
+  The spmpen CSR is a WARL register. Bits beyond the number of implemented SPMP
+  entries are read-only zero.
+versions:
+  - version: "1.0.0"
+    state: ratified
+    ratification_date: 2026-08
+    url: "https://github.com/riscv/riscv-spmp/tree/v1.0"
+requirements:
+  extension:
+    name: Sspmp

data/.data/spec/std/isa/ext/Zvabd.yaml

@@ -12,9 +12,13 @@ description: |
   vectors of integers, including widening absolute-difference-and-accumulate
   variants. These operations are widely used in image registration, object
   recognition, motion estimation, and loop filters for video workloads.
+
+  The single-width instructions support SEW = 8, 16, and 32, and also support
+  SEW = 64 when Zve64x is implemented. The widening accumulate instructions
+  support SEW = 8 and 16.
 type: unprivileged
 versions:
-  - version: "0.7.0"
+  - version: "0.9.0"
     state: frozen
 requirements:
   extension:

data/.data/spec/std/isa/ext/Zvfbdota32f.yaml

@@ -0,0 +1,23 @@
+# Copyright (c) 2026 Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+$schema: "ext_schema.json#"
+kind: extension
+name: Zvfbdota32f
+long_name: FP32 batched dot-product extension
+type: unprivileged
+rvi_jira_issue: https://riscv.atlassian.net/browse/RVS-3925
+requirements:
+  extension:
+    name: Zve32f
+    version: "= 1.0.0"
+versions:
+  - version: "0.7.0"
+    state: development
+    repositories:
+      - url: https://github.com/riscv/riscv-isa-manual.git
+        branch: zvbdot
+description: |
+  `Zvfbdota32f` is a member of the `Zvbdota` family of batched
+  dot-product extensions. It provides FP32 batched dot-product capability for
+  vector floating-point computation.

data/.data/spec/std/isa/ext/Zvzip.yaml

@@ -0,0 +1,24 @@
+# Copyright (c) 2026 Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+# yaml-language-server: $schema=../../../schemas/ext_schema.json
+
+$schema: "ext_schema.json#"
+kind: extension
+name: Zvzip
+long_name: Vector Extension for Reordering Structured Data
+type: unprivileged
+versions:
+  - version: "0.3.0"
+    state: development
+    repositories:
+      - url: https://github.com/ptomsich/riscv-isa-manual.git
+        branch: zvzip
+requirements:
+  extension:
+    name: Zve32x
+description: |
+  The `Zvzip` extension provides vector instructions for reordering structured
+  data in vector registers: interleaving and deinterleaving element sequences,
+  and pairwise transposition of elements from two vector register groups.
+  These operations support packing and unpacking structured data and
+  transposing small matrices.

data/.data/spec/std/isa/inst/C/c.bnez.yaml

@@ -8,8 +8,8 @@ kind: instruction
 name: c.bnez
 long_name: Branch if NOT Equal Zero
 description: |
-  C.BEQZ performs conditional control transfers. The offset is sign-extended and added to the pc to form the branch target address. It can therefore target a ±256 B range. C.BEQZ takes the branch if the value in register xs1' is NOT zero.
-  It expands to `beq` `xs1, x0, offset`.
+  C.BNEZ performs conditional control transfers. The offset is sign-extended and added to the pc to form the branch target address. It can therefore target a ±256 B range. C.BNEZ takes the branch if the value in register xs1' is NOT zero.
+  It expands to `bne` `xs1, x0, offset`.
 definedBy:
   extension:
     name: Zca

data/.data/spec/std/isa/inst/H/hlv.b.yaml

@@ -13,7 +13,7 @@ description: |
 definedBy:
   extension:
     name: H
-assembly: xd, xs1
+assembly: xd, (xs1)
 encoding:
   match: 011000000000-----100-----1110011
   variables:

data/.data/spec/std/isa/inst/H/hlv.bu.yaml

@@ -13,7 +13,7 @@ description: |
 definedBy:
   extension:
     name: H
-assembly: xd, xs1
+assembly: xd, (xs1)
 encoding:
   match: 011000000001-----100-----1110011
   variables:

data/.data/spec/std/isa/inst/H/hlv.d.yaml

@@ -15,7 +15,7 @@ definedBy:
     - xlen: 64
     - extension:
         name: H
-assembly: xd, xs1
+assembly: xd, (xs1)
 encoding:
   match: 011011000000-----100-----1110011
   variables:

data/.data/spec/std/isa/inst/H/hlv.h.yaml

@@ -13,7 +13,7 @@ description: |
 definedBy:
   extension:
     name: H
-assembly: xd, xs1
+assembly: xd, (xs1)
 encoding:
   match: 011001000000-----100-----1110011
   variables:

data/.data/spec/std/isa/inst/H/hlv.hu.yaml

@@ -13,7 +13,7 @@ description: |
 definedBy:
   extension:
     name: H
-assembly: xd, xs1
+assembly: xd, (xs1)
 encoding:
   match: 011001000001-----100-----1110011
   variables:

data/.data/spec/std/isa/inst/H/hlv.w.yaml

@@ -13,7 +13,7 @@ description: |
 definedBy:
   extension:
     name: H
-assembly: xd, xs1
+assembly: xd, (xs1)
 encoding:
   match: 011010000000-----100-----1110011
   variables:

data/.data/spec/std/isa/inst/H/hlv.wu.yaml

@@ -15,7 +15,7 @@ definedBy:
     - xlen: 64
     - extension:
         name: H
-assembly: xd, xs1
+assembly: xd, (xs1)
 encoding:
   match: 011010000001-----100-----1110011
   variables:

data/.data/spec/std/isa/inst/H/hlvx.hu.yaml

@@ -15,7 +15,7 @@ description: |
 definedBy:
   extension:
     name: H
-assembly: xd, xs1
+assembly: xd, (xs1)
 encoding:
   match: 011001000011-----100-----1110011
   variables:

data/.data/spec/std/isa/inst/H/hlvx.wu.yaml

@@ -15,7 +15,7 @@ description: |
 definedBy:
   extension:
     name: H
-assembly: xd, xs1
+assembly: xd, (xs1)
 encoding:
   match: 011010000011-----100-----1110011
   variables:

data/.data/spec/std/isa/inst/H/hsv.b.yaml

@@ -13,7 +13,7 @@ description: |
 definedBy:
   extension:
     name: H
-assembly: xs1, xs2
+assembly: xs2, (xs1)
 encoding:
   match: 0110001----------100000001110011
   variables:

data/.data/spec/std/isa/inst/H/hsv.d.yaml

@@ -15,7 +15,7 @@ definedBy:
     - xlen: 64
     - extension:
         name: H
-assembly: xs1, xs2
+assembly: xs2, (xs1)
 encoding:
   match: 0110111----------100000001110011
   variables:

data/.data/spec/std/isa/inst/H/hsv.h.yaml

@@ -13,7 +13,7 @@ description: |
 definedBy:
   extension:
     name: H
-assembly: xs1, xs2
+assembly: xs2, (xs1)
 encoding:
   match: 0110011----------100000001110011
   variables:

data/.data/spec/std/isa/inst/H/hsv.w.yaml

@@ -13,7 +13,7 @@ description: |
 definedBy:
   extension:
     name: H
-assembly: xs1, xs2
+assembly: xs2, (xs1)
 encoding:
   match: 0110101----------100000001110011
   variables: