udb 0.1.17 → 0.1.18

data/.data/spec/std/isa/inst/I/ld.yaml

@@ -58,15 +58,16 @@ access:
 operation(): |
   XReg virtual_address = X[xs1] + $signed(imm);
 
-  if (xlen() == 32) {
-    if (implemented?(ExtensionName::Zilsd)) {
-      Bits<64> data = read_memory(64, virtual_address, $encoding);
-
-      X[xd] = data[31:0];
-      X[xd+1] = data[63:32];
+  if (xlen() == 64) {
+    X[xd] = read_memory(64, virtual_address, $encoding);
+  } else if (implemented?(ExtensionName::Zilsd)) {
+    if (endianness() == Endian::Big) {
+      X[xd+1] = read_memory(32, virtual_address, $encoding);
+      X[xd] = read_memory(32, virtual_address + 4, $encoding);
     } else {
-      raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+      X[xd] = read_memory(32, virtual_address, $encoding);
+      X[xd+1] = read_memory(32, virtual_address + 4, $encoding);
     }
   } else {
-    X[xd] = read_memory(64, virtual_address, $encoding);
+    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
   }

data/.data/spec/std/isa/inst/I/sd.yaml

@@ -52,17 +52,18 @@ access:
   vs: always
   vu: always
 operation(): |
-  Bits<64> data;
   XReg virtual_address = X[xs1] + $signed(imm);
 
-  if (xlen() == 32) {
-    if (implemented?(ExtensionName::Zilsd)) {
-      data = {X[xs2 + 1], X[xs2]};
+  if (xlen() == 64) {
+    write_memory(64, virtual_address, X[xs2], $encoding);
+  } else if (implemented?(ExtensionName::Zilsd)) {
+    if (endianness() == Endian::Big) {
+      write_memory(32, virtual_address, X[xs2 + 1], $encoding);
+      write_memory(32, virtual_address + 4, X[xs2], $encoding);
     } else {
-      raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+      write_memory(32, virtual_address, X[xs2], $encoding);
+      write_memory(32, virtual_address + 4, X[xs2 + 1], $encoding);
     }
   } else {
-    data = X[xs2];
+    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
   }
-
-  write_memory(64, virtual_address, data, $encoding);

data/.data/spec/std/isa/inst/Q/fcvt.q.d.yaml

@@ -11,7 +11,7 @@ definedBy:
   extension:
     name: Q
 description: |
-  `fcvt.d.q` converts a double-precision floating-point number to a quad-precision floating-point number.
+  `fcvt.q.d` converts a double-precision floating-point number to a quad-precision floating-point number.
 assembly: fd, fs1, rm
 encoding:
   match: 010001100001-------------1010011

data/.data/spec/std/isa/inst/Q/flq.yaml

@@ -18,7 +18,7 @@ description: |
 definedBy:
   extension:
     name: Q
-assembly: fd, xs1, imm
+assembly: fd, imm(xs1)
 encoding:
   match: "-----------------100-----0000111"
   variables:

data/.data/spec/std/isa/inst/Sdext/dret.yaml

@@ -6,9 +6,26 @@
 $schema: inst_schema.json#
 kind: instruction
 name: dret
-long_name: No synopsis available
+long_name: Return from Debug Mode
 description: |
-  No description available.
+  Resumes execution after Debug Mode. `dret` is only legal in Debug Mode;
+  executing it in any other mode raises an Illegal Instruction exception.
+
+  When executed in Debug Mode, `dret`:
+
+  . Sets the PC to the value in `dpc`.
+  . Changes the privilege and virtualization mode to those held in
+    `dcsr.PRV` and `dcsr.V`.
+  . If the new privilege mode is less privileged than M-mode, clears
+    `mstatus.MPRV`.
+  . If Smdbltrp is implemented and the new privilege mode is less privileged
+    than M-mode, clears `mstatus.MDT`.
+  . If Ssdbltrp is implemented and the new privilege mode is U, VS, or VU,
+    clears `sstatus.SDT`; if the new mode is VU, also clears `vsstatus.SDT`.
+  . If Zicfilp is implemented, sets `ELP` to `dcsr.PELP` if Zicfilp is
+    enabled (`xLPE`=1) in the new privilege mode, otherwise to
+    `NO_LP_EXPECTED`, and then clears `dcsr.PELP`.
+  . Leaves Debug Mode.
 definedBy:
   extension:
     name: Sdext
@@ -17,9 +34,58 @@ encoding:
   match: "01111011001000000000000001110011"
   variables: []
 access:
-  s: always
-  u: always
-  vs: always
-  vu: always
+  s: never
+  u: never
+  vs: never
+  vu: never
 data_independent_timing: false
 operation(): |
+  # UDB does not yet model Debug Mode state, so the hart can never be in Debug
+  # Mode and dret is always illegal, regardless of privilege mode.
+  # TODO: once Debug Mode is modeled, raise this only when the hart is not in
+  # Debug Mode.
+  raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
+
+  # determine the resume mode from dcsr.PRV/dcsr.V
+  PrivilegeMode new_mode = PrivilegeMode::M;
+  if (CSR[dcsr].PRV == 2'b11) {
+    new_mode = PrivilegeMode::M;
+  } else if (CSR[dcsr].PRV == 2'b01) {
+    new_mode = PrivilegeMode::S;
+    if (implemented?(ExtensionName::H)) {
+      if (CSR[dcsr].V == 1'b1) {
+        new_mode = PrivilegeMode::VS;
+      }
+    }
+  } else if (CSR[dcsr].PRV == 2'b00) {
+    new_mode = PrivilegeMode::U;
+    if (implemented?(ExtensionName::H)) {
+      if (CSR[dcsr].V == 1'b1) {
+        new_mode = PrivilegeMode::VU;
+      }
+    }
+  } else {
+    unpredictable("dcsr.PRV holds a reserved encoding; the hart may resume in any supported privilege mode");
+  }
+
+  if (new_mode != PrivilegeMode::M) {
+    if (implemented?(ExtensionName::U)) {
+      CSR[mstatus].MPRV = 0;
+    }
+    if (implemented?(ExtensionName::Smdbltrp)) {
+      CSR[mstatus].MDT = 1'b0;
+    }
+  }
+
+  # TODO: Ssdbltrp: if new_mode is U, VS, or VU, clear sstatus.SDT; if new_mode
+  # is VU, also clear vsstatus.SDT. UDB does not yet define the SDT fields.
+
+  if (implemented?(ExtensionName::Zicfilp)) {
+    # TODO: set ELP to dcsr.PELP if xLPE is enabled for new_mode, otherwise to
+    # NO_LP_EXPECTED. UDB does not yet model the ELP state, so this restore
+    # must happen before dcsr.PELP is cleared below once it is added.
+    CSR[dcsr].PELP = 1'b0;
+  }
+
+  set_mode(new_mode);
+  $pc = $bits(CSR[dpc]);

data/.data/spec/std/isa/inst/V/vfncvt.f.f.w.yaml

@@ -6,9 +6,9 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: vfncvt.f.f.w
-long_name: "Vector floating-point widening conversion"
+long_name: "Vector floating-point narrowing conversion"
 description: |
-  Converts floating-point elements from vector register vs2 to a wider floating-point format and stores results in vector register vd, using vector mask vm. The conversion follows IEEE 754 standards.
+  Converts double-width floating-point elements from vector register vs2 to a single-width floating-point format and stores results in vector register vd, using vector mask vm. The conversion follows IEEE 754 standards.
 definedBy:
   extension:
     anyOf:

data/.data/spec/std/isa/inst/V/vfncvt.f.x.w.yaml

@@ -6,9 +6,9 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: vfncvt.f.x.w
-long_name: "Vector integer to floating-point widening conversion"
+long_name: "Vector integer to floating-point narrowing conversion"
 description: |
-  Converts signed integer elements from vector register vs2 to a wider floating-point format and stores results in vector register vd, using vector mask vm. The conversion follows IEEE 754 standards.
+  Converts double-width signed integer elements from vector register vs2 to a single-width floating-point format and stores results in vector register vd, using vector mask vm. The conversion follows IEEE 754 standards.
 definedBy:
   extension:
     name: Zvl32b

data/.data/spec/std/isa/inst/V/vfncvt.f.xu.w.yaml

@@ -6,9 +6,9 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: vfncvt.f.xu.w
-long_name: "Vector unsigned integer to floating-point widening conversion"
+long_name: "Vector unsigned integer to floating-point narrowing conversion"
 description: |
-  Converts unsigned integer elements from vector register vs2 to a wider floating-point format and stores results in vector register vd, using vector mask vm. The conversion follows IEEE 754 standards.
+  Converts double-width unsigned integer elements from vector register vs2 to a single-width floating-point format and stores results in vector register vd, using vector mask vm. The conversion follows IEEE 754 standards.
 definedBy:
   extension:
     name: Zvl32b

data/.data/spec/std/isa/inst/V/vfncvt.rod.f.f.w.yaml

@@ -6,9 +6,9 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: vfncvt.rod.f.f.w
-long_name: "Vector floating-point format conversion with round-to-odd (widening)"
+long_name: "Vector floating-point narrowing conversion with round-to-odd"
 description: |
-  Converts floating-point elements from vector register vs2 to a wider floating-point format using round-to-odd mode and stores results in vector register vd, using vector mask vm.
+  Converts double-width floating-point elements from vector register vs2 to a single-width floating-point format using round-to-odd mode and stores results in vector register vd, using vector mask vm.
 definedBy:
   extension:
     anyOf:

data/.data/spec/std/isa/inst/V/vfncvt.rtz.x.f.w.yaml

@@ -6,9 +6,9 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: vfncvt.rtz.x.f.w
-long_name: "Vector floating-point to integer widening conversion with truncation"
+long_name: "Vector floating-point to integer narrowing conversion with truncation"
 description: |
-  Converts floating-point elements from vector register vs2 to a wider integer format using round-toward-zero mode and stores results in vector register vd, using vector mask vm.
+  Converts double-width floating-point elements from vector register vs2 to a single-width integer format using round-toward-zero mode and stores results in vector register vd, using vector mask vm.
 definedBy:
   extension:
     anyOf:

data/.data/spec/std/isa/inst/V/vfncvt.rtz.xu.f.w.yaml

@@ -6,9 +6,9 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: vfncvt.rtz.xu.f.w
-long_name: "Vector floating-point to unsigned integer widening conversion with truncation"
+long_name: "Vector floating-point to unsigned integer narrowing conversion with truncation"
 description: |
-  Converts floating-point elements from vector register vs2 to a wider unsigned integer format using round-toward-zero mode and stores results in vector register vd, using vector mask vm.
+  Converts double-width floating-point elements from vector register vs2 to a single-width unsigned integer format using round-toward-zero mode and stores results in vector register vd, using vector mask vm.
 definedBy:
   extension:
     anyOf:

data/.data/spec/std/isa/inst/V/vfncvt.x.f.w.yaml

@@ -6,9 +6,9 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: vfncvt.x.f.w
-long_name: "Vector floating-point to integer widening conversion"
+long_name: "Vector floating-point to integer narrowing conversion"
 description: |
-  Converts floating-point elements from vector register vs2 to a wider integer format and stores results in vector register vd, using vector mask vm. The conversion follows IEEE 754 rounding rules.
+  Converts double-width floating-point elements from vector register vs2 to a single-width integer format and stores results in vector register vd, using vector mask vm. The conversion follows IEEE 754 rounding rules.
 definedBy:
   extension:
     anyOf:

data/.data/spec/std/isa/inst/V/vfncvt.xu.f.w.yaml

@@ -6,9 +6,9 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: vfncvt.xu.f.w
-long_name: "Vector floating-point to unsigned integer widening conversion"
+long_name: "Vector floating-point to unsigned integer narrowing conversion"
 description: |
-  Converts floating-point elements from vector register vs2 to a wider unsigned integer format and stores results in vector register vd, using vector mask vm. The conversion follows IEEE 754 rounding rules.
+  Converts double-width floating-point elements from vector register vs2 to a single-width unsigned integer format and stores results in vector register vd, using vector mask vm. The conversion follows IEEE 754 rounding rules.
 definedBy:
   extension:
     anyOf:

data/.data/spec/std/isa/inst/V/vnclip.wi.yaml

@@ -6,9 +6,9 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: vnclip.wi
-long_name: "Vector widening signed clip with immediate"
+long_name: "Vector narrowing signed clip with immediate"
 description: |
-  Performs widening signed clip operation on elements from vector register vs2 using immediate clip value and stores results in vector register vd, using vector mask vm. The operation clips values to a specified range and widens the result.
+  Performs narrowing signed clip operation on double-width elements from vector register vs2 using immediate clip value and stores results in vector register vd, using vector mask vm. The operation clips values to a specified range and packs the result into a narrower destination.
 definedBy:
   extension:
     name: Zvl32b

data/.data/spec/std/isa/inst/V/vnclip.wv.yaml

@@ -6,9 +6,9 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: vnclip.wv
-long_name: "Vector widening signed clip"
+long_name: "Vector narrowing signed clip"
 description: |
-  Performs widening signed clip operation on elements from vector register vs2 using clip values from vector register vs1 and stores results in vector register vd, using vector mask vm. The operation clips values to a specified range and widens the result.
+  Performs narrowing signed clip operation on double-width elements from vector register vs2 using clip values from vector register vs1 and stores results in vector register vd, using vector mask vm. The operation clips values to a specified range and packs the result into a narrower destination.
 definedBy:
   extension:
     name: Zvl32b

data/.data/spec/std/isa/inst/V/vnclip.wx.yaml

@@ -6,9 +6,9 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: vnclip.wx
-long_name: "Vector widening signed clip with scalar"
+long_name: "Vector narrowing signed clip with scalar"
 description: |
-  Performs widening signed clip operation on elements from vector register vs2 using scalar clip value from register xs1 and stores results in vector register vd, using vector mask vm. The operation clips values to a specified range and widens the result.
+  Performs narrowing signed clip operation on double-width elements from vector register vs2 using scalar clip value from register xs1 and stores results in vector register vd, using vector mask vm. The operation clips values to a specified range and packs the result into a narrower destination.
 definedBy:
   extension:
     name: Zvl32b

data/.data/spec/std/isa/inst/V/vnclipu.wi.yaml

@@ -6,9 +6,9 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: vnclipu.wi
-long_name: "Vector widening unsigned clip with immediate"
+long_name: "Vector narrowing unsigned clip with immediate"
 description: |
-  Performs widening unsigned clip operation on elements from vector register vs2 using immediate clip value and stores results in vector register vd, using vector mask vm. The operation clips values to a specified range and widens the result.
+  Performs narrowing unsigned clip operation on double-width elements from vector register vs2 using immediate clip value and stores results in vector register vd, using vector mask vm. The operation clips values to a specified range and packs the result into a narrower destination.
 definedBy:
   extension:
     name: Zvl32b

data/.data/spec/std/isa/inst/V/vnclipu.wv.yaml

@@ -6,9 +6,9 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: vnclipu.wv
-long_name: "Vector widening unsigned clip"
+long_name: "Vector narrowing unsigned clip"
 description: |
-  Performs widening unsigned clip operation on elements from vector register vs2 using clip values from vector register vs1 and stores results in vector register vd, using vector mask vm. The operation clips values to a specified range and widens the result.
+  Performs narrowing unsigned clip operation on double-width elements from vector register vs2 using clip values from vector register vs1 and stores results in vector register vd, using vector mask vm. The operation clips values to a specified range and packs the result into a narrower destination.
 definedBy:
   extension:
     name: Zvl32b

data/.data/spec/std/isa/inst/V/vnclipu.wx.yaml

@@ -6,9 +6,9 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: vnclipu.wx
-long_name: "Vector widening unsigned clip with scalar"
+long_name: "Vector narrowing unsigned clip with scalar"
 description: |
-  Performs widening unsigned clip operation on elements from vector register vs2 using scalar clip value from register xs1 and stores results in vector register vd, using vector mask vm. The operation clips values to a specified range and widens the result.
+  Performs narrowing unsigned clip operation on double-width elements from vector register vs2 using scalar clip value from register xs1 and stores results in vector register vd, using vector mask vm. The operation clips values to a specified range and packs the result into a narrower destination.
 definedBy:
   extension:
     name: Zvl32b

data/.data/spec/std/isa/inst/V/vnsra.wi.yaml

@@ -6,9 +6,9 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: vnsra.wi
-long_name: "Vector widening signed shift right arithmetic with immediate"
+long_name: "Vector narrowing signed shift right arithmetic with immediate"
 description: |
-  Performs widening signed arithmetic right shift on elements from vector register vs2 by immediate shift amount and stores results in vector register vd, using vector mask vm. The operation preserves the sign bit and widens the result.
+  Performs narrowing signed arithmetic right shift on double-width elements from vector register vs2 by immediate shift amount and stores results in vector register vd, using vector mask vm. The operation preserves the sign bit and writes a single-width destination.
 definedBy:
   extension:
     name: Zvl32b

data/.data/spec/std/isa/inst/V/vnsra.wv.yaml

@@ -6,9 +6,9 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: vnsra.wv
-long_name: "Vector widening signed shift right arithmetic"
+long_name: "Vector narrowing signed shift right arithmetic"
 description: |
-  Performs widening signed arithmetic right shift on elements from vector register vs2 by shift amounts from vector register vs1 and stores results in vector register vd, using vector mask vm. The operation preserves the sign bit and widens the result.
+  Performs narrowing signed arithmetic right shift on double-width elements from vector register vs2 by shift amounts from vector register vs1 and stores results in vector register vd, using vector mask vm. The operation preserves the sign bit and writes a single-width destination.
 definedBy:
   extension:
     name: Zvl32b

data/.data/spec/std/isa/inst/V/vnsra.wx.yaml

@@ -6,9 +6,9 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: vnsra.wx
-long_name: "Vector widening signed shift right arithmetic with scalar"
+long_name: "Vector narrowing signed shift right arithmetic with scalar"
 description: |
-  Performs widening signed arithmetic right shift on elements from vector register vs2 by shift amount from scalar register xs1 and stores results in vector register vd, using vector mask vm. The operation preserves the sign bit and widens the result.
+  Performs narrowing signed arithmetic right shift on double-width elements from vector register vs2 by shift amount from scalar register xs1 and stores results in vector register vd, using vector mask vm. The operation preserves the sign bit and writes a single-width destination.
 definedBy:
   extension:
     name: Zvl32b

data/.data/spec/std/isa/inst/V/vnsrl.wi.yaml

@@ -6,9 +6,9 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: vnsrl.wi
-long_name: "Vector widening logical shift right with immediate"
+long_name: "Vector narrowing logical shift right with immediate"
 description: |
-  Performs widening logical right shift on elements from vector register vs2 by immediate shift amount and stores results in vector register vd, using vector mask vm. The operation fills with zeros and widens the result.
+  Performs narrowing logical right shift on double-width elements from vector register vs2 by immediate shift amount and stores results in vector register vd, using vector mask vm. The operation fills with zeros and writes a single-width destination.
 definedBy:
   extension:
     name: Zvl32b

data/.data/spec/std/isa/inst/V/vnsrl.wv.yaml

@@ -6,9 +6,9 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: vnsrl.wv
-long_name: "Vector widening logical shift right"
+long_name: "Vector narrowing logical shift right"
 description: |
-  Performs widening logical right shift on elements from vector register vs2 by shift amounts from vector register vs1 and stores results in vector register vd, using vector mask vm. The operation fills with zeros and widens the result.
+  Performs narrowing logical right shift on double-width elements from vector register vs2 by shift amounts from vector register vs1 and stores results in vector register vd, using vector mask vm. The operation fills with zeros and writes a single-width destination.
 definedBy:
   extension:
     name: Zvl32b

data/.data/spec/std/isa/inst/V/vnsrl.wx.yaml

@@ -6,9 +6,9 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: vnsrl.wx
-long_name: "Vector widening logical shift right with scalar"
+long_name: "Vector narrowing logical shift right with scalar"
 description: |
-  Performs widening logical right shift on elements from vector register vs2 by shift amount from scalar register xs1 and stores results in vector register vd, using vector mask vm. The operation fills with zeros and widens the result.
+  Performs narrowing logical right shift on double-width elements from vector register vs2 by shift amount from scalar register xs1 and stores results in vector register vd, using vector mask vm. The operation fills with zeros and writes a single-width destination.
 definedBy:
   extension:
     name: Zvl32b

data/.data/spec/std/isa/inst/Zfh/fcvt.h.s.yaml

@@ -6,7 +6,7 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: fcvt.h.s
-long_name: Convert half-precision float to a single-precision float
+long_name: Convert single-precision float to a half-precision float
 definedBy:
   extension:
     oneOf:
@@ -14,7 +14,7 @@ definedBy:
       - name: Zhinxmin
 assembly: fd, fs1, rm
 description: |
-  Converts a half-precision number in floating-point register _fs1_ into a single-precision floating-point number in
+  Converts a single-precision number in floating-point register _fs1_ into a half-precision floating-point number in
   floating-point register _fd_.
 
   `fcvt.h.s` rounds according to the _rm_ field.
@@ -39,34 +39,42 @@ access:
 operation(): |
   check_f_ok($encoding);
 
-  Bits<16> hp_value = F[fs1][15:0];
+  # STATUS: INCOMPLETE. Narrowing single -> half loses precision, so it needs
+  # IEEE 754 rounding (per _rm_), overflow/underflow and inexact handling.
+  # Only the NaN, infinity and zero cases below are handled. Every other
+  # input hits the assert(false) TODO. softfloat_roundPackToF16 does not exist
+  # in fp.idl yet.
+  Bits<32> sp_value = F[fs1][31:0];
 
-  Bits<1> sign = hp_value[15];
-  Bits<5> exp = hp_value[14:10];
-  Bits<10> frac = hp_value[9:0];
+  Bits<1> sign = sp_value[31];
+  Bits<8> exp = sp_value[30:23];
+  Bits<23> frac = sp_value[22:0];
 
-  if (exp == 0x1F) {
+  if (exp == 0xFF) {
     if (frac != 0) {
-      if ((hp_value & 0x0200) != 0) {
+      # NaN. A signaling NaN has the quiet bit (frac[22]) clear and raises NV.
+      if ((sp_value & 0x00400000) == 0) {
         set_fp_flag(FpFlag::NV);
       }
-      F[fd] = HP_CANONICAL_NAN;
+      F[fd] = nan_box(16, FLEN, HP_CANONICAL_NAN);
     } else {
-      F[fd] = packToF32UI(sign, 0xFF, 0);
+      F[fd] = nan_box(16, FLEN, packToF16UI( sign, 0x1F, 0 ));
     }
   } else {
-    if (exp != 0) {
-      if (frac != 0) {
-        F[fd] = packToF32UI(sign, 0, 0);
-      } else {
-        Bits<6> norm_exp;
-        (norm_exp, frac) = softfloat_normSubnormalF16Sig( frac );
-        exp = norm_exp - 1;
-        F[fd] = packToF32UI(sign, exp + 0x70, frac << 13);
-      }
+
+    # frac is a 24-bit significand, the bottom 9 bits LSB are extracted and OR-red
+    # into a sticky flag, the top 15 MSBs are extracted, the LSB of this top slice
+    # is OR-red with the sticky
+    Bits<16> frac16 = (frac >> 9) | ((frac & 0x1ff) != 0 ? 1 : 0);
+    if ((exp | frac16) == 0) {
+      F[fd] = nan_box(16, FLEN, packToF16UI( sign, 0, 0 ));
     } else {
-      F[fd] = packToF32UI(sign, exp + 0x70, frac << 13);
+      # TODO: finite nonzero inputs need softfloat_roundPackToF16, which is not implemented.
+      # The frac16/sticky computation above is unverified draft code.
+      assert(false, "TODO: implement roundPackToF16");
+      # F[fd] = softfloat_roundPackToF16(sign, exp - 0x71, frac16 | 0x4000);
     }
+
   }
 
   mark_f_state_dirty();

data/.data/spec/std/isa/inst/Zfh/fcvt.s.h.yaml

@@ -6,7 +6,7 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: fcvt.s.h
-long_name: Convert single-precision float to a half-precision float
+long_name: Convert half-precision float to a single-precision float
 definedBy:
   extension:
     oneOf:
@@ -14,7 +14,7 @@ definedBy:
       - name: Zhinxmin
 assembly: fd, fs1, rm
 description: |
-  Converts a single-precision number in floating-point register _fs1_ into a half-precision floating-point number in
+  Converts a half-precision number in floating-point register _fs1_ into a single-precision floating-point number in
   floating-point register _fd_.
 
   `fcvt.s.h` will never round, and so the 'rm' field is effectively ignored.
@@ -36,34 +36,49 @@ access:
 operation(): |
   check_f_ok($encoding);
 
-  Bits<32> sp_value = F[fs1][31:0];
+  Bits<16> hp_value = F[fs1][15:0];
 
-  Bits<1> sign = sp_value[31];
-  Bits<8> exp = sp_value[30:23];
-  Bits<23> frac = sp_value[22:0];
+  Bits<1> sign = hp_value[15];
+  Bits<5> exp = hp_value[14:10];
+  Bits<10> frac = hp_value[9:0];
 
-  if (exp == 0xFF) {
+  Bits<32> sp_value = 0;
+
+  # Widening half -> single is always exact, so no rounding is needed.
+  if (exp == 0x1F) {
     if (frac != 0) {
-      if ((sp_value & 0x00400000) != 0) {
+      # NaN. A signaling NaN has the quiet bit (frac[9]) clear and raises NV.
+      # Either way the result is the canonical single-precision NaN.
+      if ((hp_value & 0x0200) == 0) {
         set_fp_flag(FpFlag::NV);
       }
-      F[fd] = nan_box(16, FLEN, HP_CANONICAL_NAN);
+      sp_value = SP_CANONICAL_NAN;
     } else {
-      F[fd] = nan_box(16, FLEN, packToF16UI( sign, 0x1F, 0 ));
+      sp_value = packToF32UI(sign, 0xFF, 0);
     }
-  } else {
-
-    # frac is a 24-bit significand, the bottom 9 bits LSB are extracted and OR-red
-    # into a sticky flag, the top 15 MSBs are extracted, the LSB of this top slice
-    # is OR-red with the sticky
-    Bits<16> frac16 = (frac >> 9) | ((frac & 0x1ff) != 0 ? 1 : 0);
-    if ((exp | frac16) == 0) {
-      F[fd] = nan_box(16, FLEN, packToF16UI( sign, 0, 0 ));
+  } else if (exp == 0) {
+    if (frac == 0) {
+      sp_value = packToF32UI(sign, 0, 0);
     } else {
-      assert(false, "TODO: implement roundPackToF16");
-      # F[fd] = soffloat_roundPackToF16(sign, exp - 0x71, frac16 | 0x4000);
+      # Subnormal half: value = frac * 2^-24. Shift the leading 1 of frac up to
+      # bit 10 (the implicit-bit position), drop it, and rebias the exponent.
+      Bits<16> frac16 = frac;
+      Bits<8> shift_dist = count_leading_zeros(16, frac16) - 5;
+      Bits<32> norm_frac = ((frac16 << shift_dist) & 0x3FF);
+      sp_value = packToF32UI(sign, 0x71 - shift_dist, norm_frac << 13);
     }
+  } else {
+    # Normal half: rebias the exponent (127 - 15 = 0x70) and widen the fraction
+    # from 10 to 23 bits.
+    Bits<8> sp_exp = exp;
+    Bits<32> frac32 = frac;
+    sp_value = packToF32UI(sign, sp_exp + 0x70, frac32 << 13);
+  }
 
+  if (implemented?(ExtensionName::D)) {
+    F[fd] = nan_box(32, 64, sp_value);
+  } else {
+    F[fd] = sp_value;
   }
 
   mark_f_state_dirty();

data/.data/spec/std/isa/inst/Zvabd/vabd.vv.yaml

@@ -11,13 +11,13 @@ description: |
   Computes the element-wise absolute difference of two signed integer SEW-bit
   source operands vs1 and vs2 and writes the result to vd according to mask vm.
 
-  Reserved when SEW is neither 8 nor 16.
+  Supports SEW of 8, 16, and 32. If the Zve64x extension is supported, SEW 64 is also supported.
 definedBy:
   extension:
     name: Zvabd
 assembly: vd, vs2, vs1, vm
 encoding:
-  match: 010001-----------010-----1010111
+  match: 010101-----------010-----1010111
   variables:
     - name: vm
       location: 25
@@ -35,7 +35,7 @@ access:
 operation(): |
   VectorState state = vector_state();
 
-  if (state.sew != 8 && state.sew != 16) {
+  if (!implemented?(ExtensionName::Zve64x) && state.sew > 32) {
     raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
   }