udb 0.1.17 → 0.1.18

data/.data/spec/std/isa/param/SSEED_READ_ONLY_ZERO.yaml

@@ -0,0 +1,28 @@
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../schemas/param_schema.json
+
+$schema: param_schema.json#
+kind: parameter
+name: SSEED_READ_ONLY_ZERO
+long_name: Whether `mseccfg.SSEED` is read-only zero
+description: |
+  Indicates whether the `mseccfg.SSEED` field is hardwired read-only zero.
+
+  Options:
+
+    true::
+      `mseccfg.SSEED` is read-only zero.
+
+    false::
+      `mseccfg.SSEED` is writable.
+schema:
+  type: boolean
+definedBy:
+  extension:
+    allOf:
+      - name: Sm
+        version: ">= 1.12"
+      - name: Zkr
+      - name: S

data/.data/spec/std/isa/param/SSI_INTR_IMPL.yaml

@@ -13,7 +13,7 @@ description: |
 
   true::
     Supervisor-level software interrupts are implemented.
-    `mie.SSIE` and `mideleg.SSI` are writable.
+    `mie.SSIE` is writable, and `mideleg.SSI` is writable if `MIDELEG_DELEGATABLE[1]` is true.
 
   false::
     Supervisor-level software interrupts are not implemented.

data/.data/spec/std/isa/param/STI_INTR_IMPL.yaml

@@ -14,7 +14,7 @@ description: |
 
   true::
     Supervisor-level timer interrupts are implemented.
-    `mie.STIE` and `mideleg.STI` are writable.
+    `mie.STIE` is writable, and `mideleg.STI` is writable if `MIDELEG_DELEGATABLE[5]` is true.
 
   false::
     Supervisor-level timer interrupts are not implemented.

data/.data/spec/std/isa/param/TCONTROL_IMPLEMENTED.yaml

@@ -0,0 +1,16 @@
+# Copyright (C) 2026 Harvey Mudd College
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../schemas/param_schema.json
+
+$schema: param_schema.json#
+kind: parameter
+name: TCONTROL_IMPLEMENTED
+description: |
+  Specifies if the tcontrol CSR is implemented
+long_name: tcontrol CSR is implemented
+schema:
+  type: boolean
+definedBy:
+  extension:
+    name: Sdtrig

data/.data/spec/std/isa/param/TDATA2_IMPLEMENTED.yaml

@@ -0,0 +1,26 @@
+# Copyright (C) 2026 Harvey Mudd College
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../schemas/param_schema.json
+
+$schema: param_schema.json#
+kind: parameter
+name: TDATA2_IMPLEMENTED
+description: |
+  Specifies if the tdata2 CSR is implemented.
+
+  Debug spec 1.0, tdata2: "This register is optional if no implemented triggers use it."
+long_name: tdata2 CSR is implemented
+schema:
+  type: boolean
+requirements:
+  idl(): |
+    (
+      $array_includes?(SDTRIG_MCONTROL6_SUPPORTED_TRIGGERS, true) ||
+      $array_includes?(SDTRIG_ITRIGGER_SUPPORTED_TRIGGERS, true) ||
+      $array_includes?(SDTRIG_ETRIGGER_SUPPORTED_TRIGGERS, true)
+    ) -> TDATA2_IMPLEMENTED;
+  reason: These trigger types require the tdata2 CSR.
+definedBy:
+  extension:
+    name: Sdtrig

data/.data/spec/std/isa/param/TDATA3_IMPLEMENTED.yaml

@@ -0,0 +1,29 @@
+# Copyright (C) 2026 Harvey Mudd College
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../schemas/param_schema.json
+
+$schema: param_schema.json#
+kind: parameter
+name: TDATA3_IMPLEMENTED
+description: |
+  Specifies if the tdata3 CSR is implemented.
+
+  Debug spec 1.0, tdata3: "This register is optional if no implemented triggers use it."
+
+  Must be true if any trigger supports type 2-6 (mcontrol, icount, itrigger, etrigger, mcontrol6).
+long_name: tdata3 CSR is implemented
+schema:
+  type: boolean
+requirements:
+  idl(): |
+    (
+      $array_includes?(SDTRIG_MCONTROL6_SUPPORTED_TRIGGERS, true) ||
+      $array_includes?(SDTRIG_ICOUNT_SUPPORTED_TRIGGERS, true) ||
+      $array_includes?(SDTRIG_ITRIGGER_SUPPORTED_TRIGGERS, true) ||
+      $array_includes?(SDTRIG_ETRIGGER_SUPPORTED_TRIGGERS, true)
+    ) -> TDATA3_IMPLEMENTED;
+  reason: Trigger types 2-6 (mcontrol, icount, itrigger, etrigger, mcontrol6) use tdata3.
+definedBy:
+  extension:
+    name: Sdtrig

data/.data/spec/std/isa/param/USEED_READ_ONLY_ZERO.yaml

@@ -0,0 +1,28 @@
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../schemas/param_schema.json
+
+$schema: param_schema.json#
+kind: parameter
+name: USEED_READ_ONLY_ZERO
+long_name: Whether `mseccfg.USEED` is read-only zero
+description: |
+  Indicates whether the `mseccfg.USEED` field is hardwired read-only zero.
+
+  Options:
+
+    true::
+      `mseccfg.USEED` is read-only zero.
+
+    false::
+      `mseccfg.USEED` is writable.
+schema:
+  type: boolean
+definedBy:
+  extension:
+    allOf:
+      - name: Sm
+        version: ">= 1.12"
+      - name: Zkr
+      - name: U

data/.data/spec/std/isa/profile/RVA23p1S64.yaml

@@ -0,0 +1,37 @@
+# Copyright (c) 2026 RISC-V International
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../schemas/profile_schema.json
+
+$schema: profile_schema.json#
+kind: profile
+name: RVA23p1S64
+long_name: S-mode extensions for version 23.1 of the 64-bit Apps Processor profile
+marketing_name: RVA23p1S64
+$inherits: "profile/RVA23S64.yaml#"
+release: { $ref: profile_release/RVA23p1.yaml# }
+introduction: |
+  The RVA23p1S64 profile specifies the ISA features available to a
+  supervisor-mode execution environment in 64-bit application processors.
+  RVA23p1S64 is based on and requires an RVA23S64 implementation.
+extensions:
+  Svrsw60t59b:
+    presence:
+      optional: development
+    version: ~> 1.0
+  Ssdbltrp:
+    presence:
+      optional: development
+    version: ~> 1.0
+  Ssccfg:
+    presence:
+      optional: development
+    version: ~> 1.0
+  Ssctr:
+    presence:
+      optional: expansion
+    version: ~> 1.0
+  Ssqosid:
+    presence:
+      optional: expansion
+    version: ~> 1.0

data/.data/spec/std/isa/profile/RVB23p1S64.yaml

@@ -0,0 +1,39 @@
+# Copyright (c) 2026 RISC-V International
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../schemas/profile_schema.json
+
+$schema: profile_schema.json#
+kind: profile
+name: RVB23p1S64
+long_name: S-mode extensions for version 23.1 of the 64-bit Bespoke Apps Processor profile
+marketing_name: RVB23p1S64
+$inherits: "profile/RVB23S64.yaml#"
+release: { $ref: profile_release/RVB23p1.yaml# }
+introduction: |
+  The RVB23p1S64 profile specifies the ISA features available to a
+  supervisor-mode execution environment in 64-bit application processors.
+  RVB23p1S64 is based on and requires an RVB23S64 implementation.
+extensions:
+  Svrsw60t59b:
+    presence:
+      optional: development
+    version: ~> 1.0
+    note: Used to avoid optionality in Linux kernel page tables.
+  Ssdbltrp:
+    presence:
+      optional: development
+    version: ~> 1.0
+    note: Included to make trap handling more robust.
+  Ssccfg:
+    presence:
+      optional: expansion
+    version: ~> 1.0
+  Ssctr:
+    presence:
+      optional: expansion
+    version: ~> 1.0
+  Ssqosid:
+    presence:
+      optional: expansion
+    version: ~> 1.0

data/.data/spec/std/isa/profile_family/RVA.yaml

@@ -135,11 +135,13 @@ description: |
   important features as profile options and limiting their granularity.
 naming_scheme: |
   The profile family name is RVA (RISC-V Apps processor).
-  A profile release name is an integer (currently 2 digits, could grow in the future).
+  A profile release name is a major release number (currently 2 digits, could grow in the future),
+  optionally followed by a minor release number separated by a period.
   A full profile name is comprised of, in order:
 
   * Prefix *RVA* for RISC-V Applications
   * Profile release
+  ** In an ISA string, a minor-release period is replaced by the lowercase letter *p*
   * Privilege mode:
   ** *U* Unprivileged (available to any privilege mode, *U* is *not* User-mode)
   ** *S* Supervisor mode (note that Hypervisor support is treated as an option)

data/.data/spec/std/isa/profile_family/RVB.yaml

@@ -31,11 +31,13 @@ description: |
   variants.
 naming_scheme: |
   The profile family name is RVB (RISC-V Bespoke processor).
-  A profile release name is a integer (currently 2 digits, could grow in the future).
+  A profile release name is a major release number (currently 2 digits, could grow in the future),
+  optionally followed by a minor release number separated by a period.
   A full profile name is comprised of, in order:
 
   * Prefix *RVB* for RISC-V Bespoke
   * Profile release
+  ** In an ISA string, a minor-release period is replaced by the lowercase letter *p*
   * Privilege mode:
   ** *U* Unprivileged (available to any privilege mode, *U* is *not* User-mode)
   ** *S* Supervisor mode (note that Hypervisor support is treated as an option)

data/.data/spec/std/isa/profile_release/RVA23p1.yaml

@@ -0,0 +1,30 @@
+# Copyright (c) 2026 RISC-V International
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../schemas/profile_release_schema.json
+
+$schema: profile_release_schema.json#
+kind: profile release
+name: RVA23p1
+long_name: RVA23.1
+marketing_name: RVA23.1
+family:
+  $ref: profile_family/RVA.yaml#
+release: "23.1"
+state: ratified
+ratification_date: "2026-10-19"
+# Semantic versions within the release
+versions:
+  - version: "1.0.0"
+
+introduction: |
+  The RVA23.1 profile release expands upon the RVA23 family of RISC-V
+  application processor profiles with additional optional extensions.
+description: |
+  This is a minor release of the RVA23 profile family. As such, it contains
+  only optional extensions and introduces no new mandatory extensions.
+
+  Only a supervisor-mode profile is specified in this release.
+
+profiles:
+  - { $ref: profile/RVA23p1S64.yaml# }

data/.data/spec/std/isa/profile_release/RVB23p1.yaml

@@ -0,0 +1,30 @@
+# Copyright (c) 2026 RISC-V International
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../schemas/profile_release_schema.json
+
+$schema: profile_release_schema.json#
+kind: profile release
+name: RVB23p1
+long_name: RVB23.1
+marketing_name: RVB23.1
+family:
+  $ref: profile_family/RVB.yaml#
+release: "23.1"
+state: ratified
+ratification_date: "2026-10-19"
+# Semantic versions within the release
+versions:
+  - version: "1.0.0"
+
+introduction: |
+  The RVB23.1 profile release expands upon the RVB23 family of RISC-V
+  application processor profiles with additional optional extensions.
+description: |
+  This is a minor release of the RVB23 profile family. As such, it contains
+  only optional extensions and introduces no new mandatory extensions.
+
+  Only a supervisor-mode profile is specified in this release.
+
+profiles:
+  - { $ref: profile/RVB23p1S64.yaml# }

data/lib/udb/version.rb

@@ -5,5 +5,5 @@
 # frozen_string_literal: true
 
 module Udb
-  def self.version = "0.1.17"
+  def self.version = "0.1.18"
 end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: udb
 version: !ruby/object:Gem::Version
-  version: 0.1.17
+  version: 0.1.18
 platform: ruby
 authors:
 - Derek Hower
 - James Ball
 bindir: bin
 cert_chain: []
-date: 2026-09-28 00:00:00.000000000 Z
+date: 2026-10-22 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: activesupport
@@ -456,8 +456,10 @@ files:
 - ".data/cfgs/profile/RVA22U64.yaml"
 - ".data/cfgs/profile/RVA23S64.yaml"
 - ".data/cfgs/profile/RVA23U64.yaml"
+- ".data/cfgs/profile/RVA23p1S64.yaml"
 - ".data/cfgs/profile/RVB23S64.yaml"
 - ".data/cfgs/profile/RVB23U64.yaml"
+- ".data/cfgs/profile/RVB23p1S64.yaml"
 - ".data/cfgs/profile/RVI20U32.yaml"
 - ".data/cfgs/profile/RVI20U64.yaml"
 - ".data/cfgs/qc_iu.yaml"
@@ -876,6 +878,8 @@ files:
 - ".data/spec/std/isa/csr/I/pmpcfgN.layout"
 - ".data/spec/std/isa/csr/S/scounteren.layout"
 - ".data/spec/std/isa/csr/S/scounteren.yaml"
+- ".data/spec/std/isa/csr/Smcdeleg/scountinhibit.layout"
+- ".data/spec/std/isa/csr/Smcdeleg/scountinhibit.yaml"
 - ".data/spec/std/isa/csr/Smcntrpmf/mcyclecfg.yaml"
 - ".data/spec/std/isa/csr/Smcntrpmf/mcyclecfgh.yaml"
 - ".data/spec/std/isa/csr/Smcntrpmf/minstretcfg.yaml"
@@ -1106,6 +1110,7 @@ files:
 - ".data/spec/std/isa/csr/Zihpm/mhpmevent9h.yaml"
 - ".data/spec/std/isa/csr/Zihpm/mhpmeventN.layout"
 - ".data/spec/std/isa/csr/Zihpm/mhpmeventNh.layout"
+- ".data/spec/std/isa/csr/Zkr/seed.yaml"
 - ".data/spec/std/isa/csr/cycle.yaml"
 - ".data/spec/std/isa/csr/cycleh.yaml"
 - ".data/spec/std/isa/csr/dcsr.yaml"
@@ -1245,6 +1250,7 @@ files:
 - ".data/spec/std/isa/ext/Smepmp.yaml"
 - ".data/spec/std/isa/ext/Smmpm.yaml"
 - ".data/spec/std/isa/ext/Smnpm.yaml"
+- ".data/spec/std/isa/ext/Smpmpdeleg.yaml"
 - ".data/spec/std/isa/ext/Smpmpmt.yaml"
 - ".data/spec/std/isa/ext/Smrnmi.yaml"
 - ".data/spec/std/isa/ext/Smstateen.yaml"
@@ -1258,6 +1264,8 @@ files:
 - ".data/spec/std/isa/ext/Ssdbltrp.yaml"
 - ".data/spec/std/isa/ext/Ssnpm.yaml"
 - ".data/spec/std/isa/ext/Sspm.yaml"
+- ".data/spec/std/isa/ext/Sspmp.yaml"
+- ".data/spec/std/isa/ext/Sspmpen.yaml"
 - ".data/spec/std/isa/ext/Ssqosid.yaml"
 - ".data/spec/std/isa/ext/Ssstateen.yaml"
 - ".data/spec/std/isa/ext/Ssstrict.yaml"
@@ -1360,6 +1368,7 @@ files:
 - ".data/spec/std/isa/ext/Zve64d.yaml"
 - ".data/spec/std/isa/ext/Zve64f.yaml"
 - ".data/spec/std/isa/ext/Zve64x.yaml"
+- ".data/spec/std/isa/ext/Zvfbdota32f.yaml"
 - ".data/spec/std/isa/ext/Zvfbfa.yaml"
 - ".data/spec/std/isa/ext/Zvfbfmin.yaml"
 - ".data/spec/std/isa/ext/Zvfbfwma.yaml"
@@ -1387,6 +1396,7 @@ files:
 - ".data/spec/std/isa/ext/Zvl32b.yaml"
 - ".data/spec/std/isa/ext/Zvl512b.yaml"
 - ".data/spec/std/isa/ext/Zvl64b.yaml"
+- ".data/spec/std/isa/ext/Zvzip.yaml"
 - ".data/spec/std/isa/inst/B/andn.yaml"
 - ".data/spec/std/isa/inst/B/orn.yaml"
 - ".data/spec/std/isa/inst/B/rev8.yaml"
@@ -2733,10 +2743,13 @@ files:
 - ".data/spec/std/isa/inst/Zks/sm4ed.yaml"
 - ".data/spec/std/isa/inst/Zks/sm4ks.yaml"
 - ".data/spec/std/isa/inst/Zvabd/vabd.vv.yaml"
+- ".data/spec/std/isa/inst/Zvabd/vabd.vx.yaml"
 - ".data/spec/std/isa/inst/Zvabd/vabdu.vv.yaml"
-- ".data/spec/std/isa/inst/Zvabd/vabs.v.yaml"
+- ".data/spec/std/isa/inst/Zvabd/vabdu.vx.yaml"
 - ".data/spec/std/isa/inst/Zvabd/vwabda.vv.yaml"
+- ".data/spec/std/isa/inst/Zvabd/vwabda.vx.yaml"
 - ".data/spec/std/isa/inst/Zvabd/vwabdau.vv.yaml"
+- ".data/spec/std/isa/inst/Zvabd/vwabdau.vx.yaml"
 - ".data/spec/std/isa/inst/Zvbb/vbrev.v.yaml"
 - ".data/spec/std/isa/inst/Zvbb/vclz.v.yaml"
 - ".data/spec/std/isa/inst/Zvbb/vcpop.v.yaml"
@@ -2748,6 +2761,7 @@ files:
 - ".data/spec/std/isa/inst/Zvbc/vclmul.vx.yaml"
 - ".data/spec/std/isa/inst/Zvbc/vclmulh.vv.yaml"
 - ".data/spec/std/isa/inst/Zvbc/vclmulh.vx.yaml"
+- ".data/spec/std/isa/inst/Zvfbdota32f/vfbdota.vv.yaml"
 - ".data/spec/std/isa/inst/Zvfbfmin/vfncvtbf16.f.f.w.yaml"
 - ".data/spec/std/isa/inst/Zvfbfmin/vfwcvtbf16.f.f.v.yaml"
 - ".data/spec/std/isa/inst/Zvfbfwma/vfwmaccbf16.vf.yaml"
@@ -2786,6 +2800,11 @@ files:
 - ".data/spec/std/isa/inst/Zvks/vsm4k.vi.yaml"
 - ".data/spec/std/isa/inst/Zvks/vsm4r.vs.yaml"
 - ".data/spec/std/isa/inst/Zvks/vsm4r.vv.yaml"
+- ".data/spec/std/isa/inst/Zvzip/vpaire.vv.yaml"
+- ".data/spec/std/isa/inst/Zvzip/vpairo.vv.yaml"
+- ".data/spec/std/isa/inst/Zvzip/vunzipe.v.yaml"
+- ".data/spec/std/isa/inst/Zvzip/vunzipo.v.yaml"
+- ".data/spec/std/isa/inst/Zvzip/vzip.vv.yaml"
 - ".data/spec/std/isa/inst_opcode/OP-32.yaml"
 - ".data/spec/std/isa/inst_opcode/OP.yaml"
 - ".data/spec/std/isa/inst_subtype/I/I-x-x.yaml"
@@ -2834,7 +2853,7 @@ files:
 - ".data/spec/std/isa/param/FOLLOW_VTYPE_RESET_RECOMMENDATION.yaml"
 - ".data/spec/std/isa/param/FORCE_UPGRADE_CBO_INVAL_TO_FLUSH.yaml"
 - ".data/spec/std/isa/param/GSTAGE_MODE_BARE.yaml"
-- ".data/spec/std/isa/param/HCONTEXT_AVAILABLE.yaml"
+- ".data/spec/std/isa/param/HCONTEXT_IMPLEMENTED.yaml"
 - ".data/spec/std/isa/param/HCOUNTENABLE_EN.yaml"
 - ".data/spec/std/isa/param/HPM_COUNTER10_WIDTH.yaml"
 - ".data/spec/std/isa/param/HPM_COUNTER11_WIDTH.yaml"
@@ -2889,7 +2908,7 @@ files:
 - ".data/spec/std/isa/param/LRSC_RESERVATION_STRATEGY.yaml"
 - ".data/spec/std/isa/param/MARCHID_IMPLEMENTED.yaml"
 - ".data/spec/std/isa/param/MCID_WIDTH.yaml"
-- ".data/spec/std/isa/param/MCONTEXT_AVAILABLE.yaml"
+- ".data/spec/std/isa/param/MCONTEXT_IMPLEMENTED.yaml"
 - ".data/spec/std/isa/param/MCOUNTENABLE_EN.yaml"
 - ".data/spec/std/isa/param/MCOUNTINHIBIT_IMPLEMENTED.yaml"
 - ".data/spec/std/isa/param/MCTRCTL_CORSWAPINH_IMPLEMENTED.yaml"
@@ -2909,7 +2928,9 @@ files:
 - ".data/spec/std/isa/param/MCTRCTL_STE_IMPLEMENTED.yaml"
 - ".data/spec/std/isa/param/MCTRCTL_TKBRINH_IMPLEMENTED.yaml"
 - ".data/spec/std/isa/param/MCTRCTL_TRETINH_IMPLEMENTED.yaml"
+- ".data/spec/std/isa/param/MEDELEG_DELEGATABLE.yaml"
 - ".data/spec/std/isa/param/MEI_INTR_IMPL.yaml"
+- ".data/spec/std/isa/param/MIDELEG_DELEGATABLE.yaml"
 - ".data/spec/std/isa/param/MIMPID_IMPLEMENTED.yaml"
 - ".data/spec/std/isa/param/MISALIGNED_AMO.yaml"
 - ".data/spec/std/isa/param/MISALIGNED_LDST.yaml"
@@ -3007,10 +3028,41 @@ files:
 - ".data/spec/std/isa/param/RESERVED_VSET_X0X0_VLMAX_CHANGE.yaml"
 - ".data/spec/std/isa/param/RVV_VL_WHEN_AVL_LT_DOUBLE_VLMAX.yaml"
 - ".data/spec/std/isa/param/SATP_MODE_BARE.yaml"
+- ".data/spec/std/isa/param/SCONTEXT_IMPLEMENTED.yaml"
 - ".data/spec/std/isa/param/SCOUNTENABLE_EN.yaml"
 - ".data/spec/std/isa/param/SCTRDEPTH_DEPTH_LEGAL_VALUES.yaml"
+- ".data/spec/std/isa/param/SDTRIG_BREAKPOINT_REENTRANCY.yaml"
+- ".data/spec/std/isa/param/SDTRIG_ETRIGGER_SUPPORTED_EXCEPTIONS.yaml"
+- ".data/spec/std/isa/param/SDTRIG_ETRIGGER_SUPPORTED_TRIGGERS.yaml"
+- ".data/spec/std/isa/param/SDTRIG_ICOUNT_COUNT_HARDWIRED_1.yaml"
+- ".data/spec/std/isa/param/SDTRIG_ICOUNT_SELF_WRITE_SETS_PENDING.yaml"
+- ".data/spec/std/isa/param/SDTRIG_ICOUNT_SUPPORTED_TRIGGERS.yaml"
+- ".data/spec/std/isa/param/SDTRIG_ITRIGGER_SUPPORTED_INTERRUPTS.yaml"
+- ".data/spec/std/isa/param/SDTRIG_ITRIGGER_SUPPORTED_TRIGGERS.yaml"
+- ".data/spec/std/isa/param/SDTRIG_MAX_CHAIN_LENGTH.yaml"
+- ".data/spec/std/isa/param/SDTRIG_MCONTROL6_EXECUTE_WRITABLE.yaml"
+- ".data/spec/std/isa/param/SDTRIG_MCONTROL6_LOAD_WRITABLE.yaml"
+- ".data/spec/std/isa/param/SDTRIG_MCONTROL6_MASKMAX6.yaml"
+- ".data/spec/std/isa/param/SDTRIG_MCONTROL6_MATCH_LEGAL_VALUES.yaml"
+- ".data/spec/std/isa/param/SDTRIG_MCONTROL6_SELECT_WRITABLE.yaml"
+- ".data/spec/std/isa/param/SDTRIG_MCONTROL6_SIZE_LEGAL_VALUES.yaml"
+- ".data/spec/std/isa/param/SDTRIG_MCONTROL6_STORE_WRITABLE.yaml"
+- ".data/spec/std/isa/param/SDTRIG_MCONTROL6_SUPPORTED_TRIGGERS.yaml"
+- ".data/spec/std/isa/param/SDTRIG_M_WRITABLE.yaml"
+- ".data/spec/std/isa/param/SDTRIG_NUM_TRIGGERS.yaml"
+- ".data/spec/std/isa/param/SDTRIG_S_WRITABLE.yaml"
+- ".data/spec/std/isa/param/SDTRIG_TEXTRA_MHSELECT_MCONTEXT_MATCH.yaml"
+- ".data/spec/std/isa/param/SDTRIG_TEXTRA_MHSELECT_VMID_MATCH.yaml"
+- ".data/spec/std/isa/param/SDTRIG_TEXTRA_MHVALUE_LEN.yaml"
+- ".data/spec/std/isa/param/SDTRIG_TEXTRA_SSELECT_ASID_MATCH.yaml"
+- ".data/spec/std/isa/param/SDTRIG_TEXTRA_SSELECT_SCONTEXT_MATCH.yaml"
+- ".data/spec/std/isa/param/SDTRIG_TEXTRA_SVALUE_LEN.yaml"
+- ".data/spec/std/isa/param/SDTRIG_U_WRITABLE.yaml"
+- ".data/spec/std/isa/param/SDTRIG_VS_WRITABLE.yaml"
+- ".data/spec/std/isa/param/SDTRIG_VU_WRITABLE.yaml"
 - ".data/spec/std/isa/param/SEI_INTR_IMPL.yaml"
 - ".data/spec/std/isa/param/SEW_MIN.yaml"
+- ".data/spec/std/isa/param/SSEED_READ_ONLY_ZERO.yaml"
 - ".data/spec/std/isa/param/SSI_INTR_IMPL.yaml"
 - ".data/spec/std/isa/param/SSTATEEN_JVT_TYPE.yaml"
 - ".data/spec/std/isa/param/STI_INTR_IMPL.yaml"
@@ -3031,6 +3083,9 @@ files:
 - ".data/spec/std/isa/param/SV57_VSMODE_TRANSLATION.yaml"
 - ".data/spec/std/isa/param/SXLEN.yaml"
 - ".data/spec/std/isa/param/S_MODE_ENDIANNESS.yaml"
+- ".data/spec/std/isa/param/TCONTROL_IMPLEMENTED.yaml"
+- ".data/spec/std/isa/param/TDATA2_IMPLEMENTED.yaml"
+- ".data/spec/std/isa/param/TDATA3_IMPLEMENTED.yaml"
 - ".data/spec/std/isa/param/TIME_CSR_IMPLEMENTED.yaml"
 - ".data/spec/std/isa/param/TINST_VALUE_ON_BREAKPOINT.yaml"
 - ".data/spec/std/isa/param/TINST_VALUE_ON_FINAL_INSTRUCTION_GUEST_PAGE_FAULT.yaml"
@@ -3058,6 +3113,7 @@ files:
 - ".data/spec/std/isa/param/TRAP_ON_SFENCE_VMA_WHEN_SATP_MODE_IS_READ_ONLY.yaml"
 - ".data/spec/std/isa/param/TRAP_ON_UNIMPLEMENTED_CSR.yaml"
 - ".data/spec/std/isa/param/TRAP_ON_UNIMPLEMENTED_INSTRUCTION.yaml"
+- ".data/spec/std/isa/param/USEED_READ_ONLY_ZERO.yaml"
 - ".data/spec/std/isa/param/UXLEN.yaml"
 - ".data/spec/std/isa/param/U_MODE_ENDIANNESS.yaml"
 - ".data/spec/std/isa/param/VECTOR_FF_NO_EXCEPTION_TRIM.yaml"
@@ -3078,11 +3134,8 @@ files:
 - ".data/spec/std/isa/param/VILL_SET_ON_RESERVED_VTYPE.yaml"
 - ".data/spec/std/isa/param/VLEN.yaml"
 - ".data/spec/std/isa/param/VMID_WIDTH.yaml"
-- ".data/spec/std/isa/param/VSEI_INTR_IMPL.yaml"
-- ".data/spec/std/isa/param/VSSI_INTR_IMPL.yaml"
 - ".data/spec/std/isa/param/VSSTAGE_MODE_BARE.yaml"
 - ".data/spec/std/isa/param/VSSTATUS_VS_EXISTS.yaml"
-- ".data/spec/std/isa/param/VSTI_INTR_IMPL.yaml"
 - ".data/spec/std/isa/param/VSTVEC_MODES.yaml"
 - ".data/spec/std/isa/param/VSXLEN.yaml"
 - ".data/spec/std/isa/param/VS_MODE_ENDIANNESS.yaml"
@@ -3097,8 +3150,10 @@ files:
 - ".data/spec/std/isa/profile/RVA22U64.yaml"
 - ".data/spec/std/isa/profile/RVA23S64.yaml"
 - ".data/spec/std/isa/profile/RVA23U64.yaml"
+- ".data/spec/std/isa/profile/RVA23p1S64.yaml"
 - ".data/spec/std/isa/profile/RVB23S64.yaml"
 - ".data/spec/std/isa/profile/RVB23U64.yaml"
+- ".data/spec/std/isa/profile/RVB23p1S64.yaml"
 - ".data/spec/std/isa/profile/RVI20U32.yaml"
 - ".data/spec/std/isa/profile/RVI20U64.yaml"
 - ".data/spec/std/isa/profile_family/RVA.yaml"
@@ -3107,7 +3162,9 @@ files:
 - ".data/spec/std/isa/profile_release/RVA20.yaml"
 - ".data/spec/std/isa/profile_release/RVA22.yaml"
 - ".data/spec/std/isa/profile_release/RVA23.yaml"
+- ".data/spec/std/isa/profile_release/RVA23p1.yaml"
 - ".data/spec/std/isa/profile_release/RVB23.yaml"
+- ".data/spec/std/isa/profile_release/RVB23p1.yaml"
 - ".data/spec/std/isa/profile_release/RVI20.yaml"
 - ".data/spec/std/isa/prose/interrupts.adoc"
 - ".data/spec/std/isa/register_file/F.yaml"

data/.data/spec/std/isa/param/HCONTEXT_AVAILABLE.yaml

@@ -1,19 +0,0 @@
-# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
-# SPDX-License-Identifier: BSD-3-Clause-Clear
-
-# yaml-language-server: $schema=../../../schemas/param_schema.json
-
-$schema: param_schema.json#
-kind: parameter
-name: HCONTEXT_AVAILABLE
-description: |
-  Specifies if HCONTEXT is available
-long_name: HCONTEXT Availability
-schema:
-  type: boolean
-definedBy:
-  extension:
-    name: Sdtrig
-requirements:
-  idl(): HCONTEXT_AVAILABLE -> MCONTEXT_AVAILABLE;
-  reason: HCONTEXT cannot exist without MCONTEXT

data/.data/spec/std/isa/param/VSEI_INTR_IMPL.yaml

@@ -1,28 +0,0 @@
-# Copyright (C) Qualcomm Technologies, Inc. and/or its subsidiaries.
-# SPDX-License-Identifier: BSD-3-Clause-Clear
-
-# yaml-language-server: $schema=../../../schemas/param_schema.json
-
-$schema: param_schema.json#
-kind: parameter
-name: VSEI_INTR_IMPL
-description: |
-  Whether or not virtual supervisor-level external interrupts are implemented.
-
-  Possible values:
-
-  true::
-    Virtual supervisor-level external interrupts are implemented.
-    `mie.VSEIE` and `mideleg.VSEI` are writable.
-
-  false::
-    Virtual supervisor-level external interrupts are not implemented.
-    `mie.VSEIE`, `mip.VSEIP`, and `mideleg.VSEI` are read-only zero.
-long_name: Virtual supervisor-level external interrupts are implemented
-schema:
-  type: boolean
-definedBy:
-  extension:
-    allOf:
-      - name: Zicsr
-      - name: H

data/.data/spec/std/isa/param/VSSI_INTR_IMPL.yaml

@@ -1,28 +0,0 @@
-# Copyright (C) Qualcomm Technologies, Inc. and/or its subsidiaries.
-# SPDX-License-Identifier: BSD-3-Clause-Clear
-
-# yaml-language-server: $schema=../../../schemas/param_schema.json
-
-$schema: param_schema.json#
-kind: parameter
-name: VSSI_INTR_IMPL
-description: |
-  Whether or not virtual supervisor-level software interrupts are implemented.
-
-  Possible values:
-
-  true::
-    Virtual supervisor-level software interrupts are implemented.
-    `mie.VSSIE` and `mideleg.VSSI` are writable.
-
-  false::
-    Virtual supervisor-level software interrupts are not implemented.
-    `mie.VSSIE`, `mip.VSSIP`, and `mideleg.VSSI` are read-only zero.
-long_name: Virtual supervisor-level software interrupts are implemented
-schema:
-  type: boolean
-definedBy:
-  extension:
-    allOf:
-      - name: Zicsr
-      - name: H