udb 0.1.17 → 0.1.18
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- checksums.yaml +4 -4
- data/.data/cfgs/example_rv64_with_overlay.yaml +140 -5
- data/.data/cfgs/profile/RVA23S64.yaml +1 -1
- data/.data/cfgs/profile/RVA23p1S64.yaml +217 -0
- data/.data/cfgs/profile/RVB23S64.yaml +1 -1
- data/.data/cfgs/profile/RVB23p1S64.yaml +179 -0
- data/.data/cfgs/rv32-riscv-tests.yaml +134 -0
- data/.data/cfgs/rv32-vector.yaml +134 -0
- data/.data/cfgs/rv64-riscv-tests.yaml +134 -0
- data/.data/cfgs/rv64-vector.yaml +134 -0
- data/.data/spec/schemas/schema_defs.json +4 -1
- data/.data/spec/std/isa/csr/I/mcounteren.layout +7 -0
- data/.data/spec/std/isa/csr/I/mcounteren.yaml +7 -0
- data/.data/spec/std/isa/csr/Smcdeleg/scountinhibit.layout +111 -0
- data/.data/spec/std/isa/csr/Smcdeleg/scountinhibit.yaml +840 -0
- data/.data/spec/std/isa/csr/Smcntrpmf/mcyclecfg.yaml +2 -0
- data/.data/spec/std/isa/csr/Smcntrpmf/mcyclecfgh.yaml +2 -0
- data/.data/spec/std/isa/csr/Smcntrpmf/minstretcfg.yaml +2 -0
- data/.data/spec/std/isa/csr/Smcntrpmf/minstretcfgh.yaml +2 -0
- data/.data/spec/std/isa/csr/Sscofpmf/scountovf.layout +7 -0
- data/.data/spec/std/isa/csr/Sscofpmf/scountovf.yaml +7 -0
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter10.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter10h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter11.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter11h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter12.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter12h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter13.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter13h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter14.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter14h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter15.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter15h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter16.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter16h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter17.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter17h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter18.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter18h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter19.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter19h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter20.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter20h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter21.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter21h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter22.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter22h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter23.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter23h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter24.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter24h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter25.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter25h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter26.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter26h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter27.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter27h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter28.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter28h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter29.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter29h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter3.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter30.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter30h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter31.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter31h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter3h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter4.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter4h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter5.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter5h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter6.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter6h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter7.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter7h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter8.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter8h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter9.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter9h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounterN.layout +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounterNh.layout +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent10.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent10h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent11.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent11h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent12.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent12h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent13.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent13h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent14.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent14h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent15.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent15h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent16.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent16h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent17.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent17h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent18.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent18h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent19.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent19h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent20.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent20h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent21.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent21h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent22.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent22h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent23.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent23h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent24.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent24h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent25.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent25h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent26.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent26h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent27.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent27h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent28.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent28h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent29.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent29h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent3.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent30.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent30h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent31.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent31h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent3h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent4.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent4h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent5.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent5h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent6.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent6h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent7.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent7h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent8.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent8h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent9.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent9h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmeventN.layout +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmeventNh.layout +4 -4
- data/.data/spec/std/isa/csr/Zkr/seed.yaml +75 -0
- data/.data/spec/std/isa/csr/hcontext.yaml +4 -4
- data/.data/spec/std/isa/csr/mcontext.yaml +4 -4
- data/.data/spec/std/isa/csr/mcycle.yaml +2 -0
- data/.data/spec/std/isa/csr/mcycleh.yaml +2 -0
- data/.data/spec/std/isa/csr/medeleg.yaml +72 -36
- data/.data/spec/std/isa/csr/menvcfg.yaml +12 -1
- data/.data/spec/std/isa/csr/menvcfgh.yaml +12 -0
- data/.data/spec/std/isa/csr/mideleg.yaml +13 -36
- data/.data/spec/std/isa/csr/mie.yaml +3 -6
- data/.data/spec/std/isa/csr/minstret.yaml +2 -0
- data/.data/spec/std/isa/csr/minstreth.yaml +2 -0
- data/.data/spec/std/isa/csr/mip.yaml +3 -6
- data/.data/spec/std/isa/csr/misa.yaml +3 -23
- data/.data/spec/std/isa/csr/mseccfg.yaml +27 -1
- data/.data/spec/std/isa/csr/mstatus.yaml +8 -2
- data/.data/spec/std/isa/csr/scontext.yaml +8 -4
- data/.data/spec/std/isa/csr/tcontrol.yaml +6 -2
- data/.data/spec/std/isa/csr/tdata2.yaml +6 -2
- data/.data/spec/std/isa/csr/tdata3.yaml +6 -2
- data/.data/spec/std/isa/ext/Sdext.yaml +58 -2
- data/.data/spec/std/isa/ext/Sm.yaml +2 -2
- data/.data/spec/std/isa/ext/Smcdeleg.yaml +7 -0
- data/.data/spec/std/isa/ext/Smmpm.yaml +8 -0
- data/.data/spec/std/isa/ext/Smnpm.yaml +19 -0
- data/.data/spec/std/isa/ext/Smpmpdeleg.yaml +33 -0
- data/.data/spec/std/isa/ext/Ssccfg.yaml +7 -0
- data/.data/spec/std/isa/ext/Ssnpm.yaml +8 -0
- data/.data/spec/std/isa/ext/Sspmp.yaml +44 -0
- data/.data/spec/std/isa/ext/Sspmpen.yaml +30 -0
- data/.data/spec/std/isa/ext/Zvabd.yaml +5 -1
- data/.data/spec/std/isa/ext/Zvfbdota32f.yaml +23 -0
- data/.data/spec/std/isa/ext/Zvzip.yaml +24 -0
- data/.data/spec/std/isa/inst/C/c.bnez.yaml +2 -2
- data/.data/spec/std/isa/inst/H/hlv.b.yaml +1 -1
- data/.data/spec/std/isa/inst/H/hlv.bu.yaml +1 -1
- data/.data/spec/std/isa/inst/H/hlv.d.yaml +1 -1
- data/.data/spec/std/isa/inst/H/hlv.h.yaml +1 -1
- data/.data/spec/std/isa/inst/H/hlv.hu.yaml +1 -1
- data/.data/spec/std/isa/inst/H/hlv.w.yaml +1 -1
- data/.data/spec/std/isa/inst/H/hlv.wu.yaml +1 -1
- data/.data/spec/std/isa/inst/H/hlvx.hu.yaml +1 -1
- data/.data/spec/std/isa/inst/H/hlvx.wu.yaml +1 -1
- data/.data/spec/std/isa/inst/H/hsv.b.yaml +1 -1
- data/.data/spec/std/isa/inst/H/hsv.d.yaml +1 -1
- data/.data/spec/std/isa/inst/H/hsv.h.yaml +1 -1
- data/.data/spec/std/isa/inst/H/hsv.w.yaml +1 -1
- data/.data/spec/std/isa/inst/I/ld.yaml +9 -8
- data/.data/spec/std/isa/inst/I/sd.yaml +9 -8
- data/.data/spec/std/isa/inst/Q/fcvt.q.d.yaml +1 -1
- data/.data/spec/std/isa/inst/Q/flq.yaml +1 -1
- data/.data/spec/std/isa/inst/Sdext/dret.yaml +72 -6
- data/.data/spec/std/isa/inst/V/vfncvt.f.f.w.yaml +2 -2
- data/.data/spec/std/isa/inst/V/vfncvt.f.x.w.yaml +2 -2
- data/.data/spec/std/isa/inst/V/vfncvt.f.xu.w.yaml +2 -2
- data/.data/spec/std/isa/inst/V/vfncvt.rod.f.f.w.yaml +2 -2
- data/.data/spec/std/isa/inst/V/vfncvt.rtz.x.f.w.yaml +2 -2
- data/.data/spec/std/isa/inst/V/vfncvt.rtz.xu.f.w.yaml +2 -2
- data/.data/spec/std/isa/inst/V/vfncvt.x.f.w.yaml +2 -2
- data/.data/spec/std/isa/inst/V/vfncvt.xu.f.w.yaml +2 -2
- data/.data/spec/std/isa/inst/V/vnclip.wi.yaml +2 -2
- data/.data/spec/std/isa/inst/V/vnclip.wv.yaml +2 -2
- data/.data/spec/std/isa/inst/V/vnclip.wx.yaml +2 -2
- data/.data/spec/std/isa/inst/V/vnclipu.wi.yaml +2 -2
- data/.data/spec/std/isa/inst/V/vnclipu.wv.yaml +2 -2
- data/.data/spec/std/isa/inst/V/vnclipu.wx.yaml +2 -2
- data/.data/spec/std/isa/inst/V/vnsra.wi.yaml +2 -2
- data/.data/spec/std/isa/inst/V/vnsra.wv.yaml +2 -2
- data/.data/spec/std/isa/inst/V/vnsra.wx.yaml +2 -2
- data/.data/spec/std/isa/inst/V/vnsrl.wi.yaml +2 -2
- data/.data/spec/std/isa/inst/V/vnsrl.wv.yaml +2 -2
- data/.data/spec/std/isa/inst/V/vnsrl.wx.yaml +2 -2
- data/.data/spec/std/isa/inst/Zfh/fcvt.h.s.yaml +28 -20
- data/.data/spec/std/isa/inst/Zfh/fcvt.s.h.yaml +35 -20
- data/.data/spec/std/isa/inst/Zvabd/vabd.vv.yaml +3 -3
- data/.data/spec/std/isa/inst/Zvabd/vabd.vx.yaml +69 -0
- data/.data/spec/std/isa/inst/Zvabd/vabdu.vv.yaml +3 -3
- data/.data/spec/std/isa/inst/Zvabd/{vabs.v.yaml → vabdu.vx.yaml} +17 -11
- data/.data/spec/std/isa/inst/Zvabd/vwabda.vv.yaml +1 -1
- data/.data/spec/std/isa/inst/Zvabd/vwabda.vx.yaml +73 -0
- data/.data/spec/std/isa/inst/Zvabd/vwabdau.vv.yaml +1 -1
- data/.data/spec/std/isa/inst/Zvabd/vwabdau.vx.yaml +74 -0
- data/.data/spec/std/isa/inst/Zvfbdota32f/vfbdota.vv.yaml +68 -0
- data/.data/spec/std/isa/inst/Zvzip/vpaire.vv.yaml +36 -0
- data/.data/spec/std/isa/inst/Zvzip/vpairo.vv.yaml +37 -0
- data/.data/spec/std/isa/inst/Zvzip/vunzipe.v.yaml +33 -0
- data/.data/spec/std/isa/inst/Zvzip/vunzipo.v.yaml +33 -0
- data/.data/spec/std/isa/inst/Zvzip/vzip.vv.yaml +37 -0
- data/.data/spec/std/isa/isa/builtin_functions.idl +51 -0
- data/.data/spec/std/isa/isa/globals.isa +117 -5
- data/.data/spec/std/isa/param/HCONTEXT_IMPLEMENTED.yaml +29 -0
- data/.data/spec/std/isa/param/{MCONTEXT_AVAILABLE.yaml → MCONTEXT_IMPLEMENTED.yaml} +3 -3
- data/.data/spec/std/isa/param/MEDELEG_DELEGATABLE.yaml +121 -0
- data/.data/spec/std/isa/param/MEI_INTR_IMPL.yaml +1 -1
- data/.data/spec/std/isa/param/MIDELEG_DELEGATABLE.yaml +177 -0
- data/.data/spec/std/isa/param/MSI_INTR_IMPL.yaml +1 -1
- data/.data/spec/std/isa/param/MTI_INTR_IMPL.yaml +1 -1
- data/.data/spec/std/isa/param/SCONTEXT_IMPLEMENTED.yaml +18 -0
- data/.data/spec/std/isa/param/SDTRIG_BREAKPOINT_REENTRANCY.yaml +45 -0
- data/.data/spec/std/isa/param/SDTRIG_ETRIGGER_SUPPORTED_EXCEPTIONS.yaml +37 -0
- data/.data/spec/std/isa/param/SDTRIG_ETRIGGER_SUPPORTED_TRIGGERS.yaml +25 -0
- data/.data/spec/std/isa/param/SDTRIG_ICOUNT_COUNT_HARDWIRED_1.yaml +23 -0
- data/.data/spec/std/isa/param/SDTRIG_ICOUNT_SELF_WRITE_SETS_PENDING.yaml +23 -0
- data/.data/spec/std/isa/param/SDTRIG_ICOUNT_SUPPORTED_TRIGGERS.yaml +25 -0
- data/.data/spec/std/isa/param/SDTRIG_ITRIGGER_SUPPORTED_INTERRUPTS.yaml +37 -0
- data/.data/spec/std/isa/param/SDTRIG_ITRIGGER_SUPPORTED_TRIGGERS.yaml +25 -0
- data/.data/spec/std/isa/param/SDTRIG_MAX_CHAIN_LENGTH.yaml +33 -0
- data/.data/spec/std/isa/param/SDTRIG_MCONTROL6_EXECUTE_WRITABLE.yaml +22 -0
- data/.data/spec/std/isa/param/SDTRIG_MCONTROL6_LOAD_WRITABLE.yaml +22 -0
- data/.data/spec/std/isa/param/SDTRIG_MCONTROL6_MASKMAX6.yaml +26 -0
- data/.data/spec/std/isa/param/SDTRIG_MCONTROL6_MATCH_LEGAL_VALUES.yaml +41 -0
- data/.data/spec/std/isa/param/SDTRIG_MCONTROL6_SELECT_WRITABLE.yaml +22 -0
- data/.data/spec/std/isa/param/SDTRIG_MCONTROL6_SIZE_LEGAL_VALUES.yaml +38 -0
- data/.data/spec/std/isa/param/SDTRIG_MCONTROL6_STORE_WRITABLE.yaml +22 -0
- data/.data/spec/std/isa/param/SDTRIG_MCONTROL6_SUPPORTED_TRIGGERS.yaml +25 -0
- data/.data/spec/std/isa/param/SDTRIG_M_WRITABLE.yaml +17 -0
- data/.data/spec/std/isa/param/SDTRIG_NUM_TRIGGERS.yaml +22 -0
- data/.data/spec/std/isa/param/SDTRIG_S_WRITABLE.yaml +19 -0
- data/.data/spec/std/isa/param/SDTRIG_TEXTRA_MHSELECT_MCONTEXT_MATCH.yaml +24 -0
- data/.data/spec/std/isa/param/SDTRIG_TEXTRA_MHSELECT_VMID_MATCH.yaml +23 -0
- data/.data/spec/std/isa/param/SDTRIG_TEXTRA_MHVALUE_LEN.yaml +26 -0
- data/.data/spec/std/isa/param/SDTRIG_TEXTRA_SSELECT_ASID_MATCH.yaml +23 -0
- data/.data/spec/std/isa/param/SDTRIG_TEXTRA_SSELECT_SCONTEXT_MATCH.yaml +26 -0
- data/.data/spec/std/isa/param/SDTRIG_TEXTRA_SVALUE_LEN.yaml +26 -0
- data/.data/spec/std/isa/param/SDTRIG_U_WRITABLE.yaml +19 -0
- data/.data/spec/std/isa/param/SDTRIG_VS_WRITABLE.yaml +19 -0
- data/.data/spec/std/isa/param/SDTRIG_VU_WRITABLE.yaml +19 -0
- data/.data/spec/std/isa/param/SEI_INTR_IMPL.yaml +1 -1
- data/.data/spec/std/isa/param/SSEED_READ_ONLY_ZERO.yaml +28 -0
- data/.data/spec/std/isa/param/SSI_INTR_IMPL.yaml +1 -1
- data/.data/spec/std/isa/param/STI_INTR_IMPL.yaml +1 -1
- data/.data/spec/std/isa/param/TCONTROL_IMPLEMENTED.yaml +16 -0
- data/.data/spec/std/isa/param/TDATA2_IMPLEMENTED.yaml +26 -0
- data/.data/spec/std/isa/param/TDATA3_IMPLEMENTED.yaml +29 -0
- data/.data/spec/std/isa/param/USEED_READ_ONLY_ZERO.yaml +28 -0
- data/.data/spec/std/isa/profile/RVA23p1S64.yaml +37 -0
- data/.data/spec/std/isa/profile/RVB23p1S64.yaml +39 -0
- data/.data/spec/std/isa/profile_family/RVA.yaml +3 -1
- data/.data/spec/std/isa/profile_family/RVB.yaml +3 -1
- data/.data/spec/std/isa/profile_release/RVA23p1.yaml +30 -0
- data/.data/spec/std/isa/profile_release/RVB23p1.yaml +30 -0
- data/lib/udb/version.rb +1 -1
- metadata +65 -8
- data/.data/spec/std/isa/param/HCONTEXT_AVAILABLE.yaml +0 -19
- data/.data/spec/std/isa/param/VSEI_INTR_IMPL.yaml +0 -28
- data/.data/spec/std/isa/param/VSSI_INTR_IMPL.yaml +0 -28
- data/.data/spec/std/isa/param/VSTI_INTR_IMPL.yaml +0 -33
|
@@ -257,3 +257,137 @@ params:
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WFI_U_MODE: false
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WFI_FINITE: true
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NON_STANDARD_EXTENSION_IMPLEMENTED: false
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+
MEDELEG_DELEGATABLE:
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[
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true,
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true,
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true,
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true,
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true,
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true,
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true,
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true,
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false,
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true,
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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]
|
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+
MIDELEG_DELEGATABLE:
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[
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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365
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false,
|
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366
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+
false,
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367
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false,
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+
false,
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369
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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+
]
|
data/.data/cfgs/rv32-vector.yaml
CHANGED
|
@@ -291,3 +291,137 @@ params:
|
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291
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WFI_U_MODE: false
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|
292
292
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WFI_FINITE: true
|
|
293
293
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NON_STANDARD_EXTENSION_IMPLEMENTED: false
|
|
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+
MEDELEG_DELEGATABLE:
|
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[
|
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true,
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true,
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true,
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true,
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true,
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true,
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true,
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true,
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true,
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true,
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false,
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false,
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true,
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true,
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false,
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true,
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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false,
|
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false,
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false,
|
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351
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false,
|
|
352
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false,
|
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353
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false,
|
|
354
|
+
false,
|
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355
|
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false,
|
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|
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false,
|
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357
|
+
false,
|
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|
+
false,
|
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359
|
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false,
|
|
360
|
+
]
|
|
361
|
+
MIDELEG_DELEGATABLE:
|
|
362
|
+
[
|
|
363
|
+
false,
|
|
364
|
+
false,
|
|
365
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false,
|
|
366
|
+
false,
|
|
367
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+
false,
|
|
368
|
+
false,
|
|
369
|
+
false,
|
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370
|
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false,
|
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371
|
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false,
|
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372
|
+
false,
|
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373
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false,
|
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374
|
+
false,
|
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375
|
+
false,
|
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376
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false,
|
|
377
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false,
|
|
378
|
+
false,
|
|
379
|
+
false,
|
|
380
|
+
false,
|
|
381
|
+
false,
|
|
382
|
+
false,
|
|
383
|
+
false,
|
|
384
|
+
false,
|
|
385
|
+
false,
|
|
386
|
+
false,
|
|
387
|
+
false,
|
|
388
|
+
false,
|
|
389
|
+
false,
|
|
390
|
+
false,
|
|
391
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false,
|
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392
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false,
|
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393
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false,
|
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|
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false,
|
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|
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false,
|
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396
|
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false,
|
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397
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+
false,
|
|
398
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+
false,
|
|
399
|
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false,
|
|
400
|
+
false,
|
|
401
|
+
false,
|
|
402
|
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false,
|
|
403
|
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false,
|
|
404
|
+
false,
|
|
405
|
+
false,
|
|
406
|
+
false,
|
|
407
|
+
false,
|
|
408
|
+
false,
|
|
409
|
+
false,
|
|
410
|
+
false,
|
|
411
|
+
false,
|
|
412
|
+
false,
|
|
413
|
+
false,
|
|
414
|
+
false,
|
|
415
|
+
false,
|
|
416
|
+
false,
|
|
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+
false,
|
|
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|
+
false,
|
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false,
|
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+
false,
|
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false,
|
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false,
|
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false,
|
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+
false,
|
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425
|
+
false,
|
|
426
|
+
false,
|
|
427
|
+
]
|
|
@@ -250,3 +250,137 @@ params:
|
|
|
250
250
|
WFI_U_MODE: false
|
|
251
251
|
WFI_FINITE: true
|
|
252
252
|
NON_STANDARD_EXTENSION_IMPLEMENTED: false
|
|
253
|
+
MEDELEG_DELEGATABLE:
|
|
254
|
+
[
|
|
255
|
+
true,
|
|
256
|
+
true,
|
|
257
|
+
true,
|
|
258
|
+
true,
|
|
259
|
+
true,
|
|
260
|
+
true,
|
|
261
|
+
true,
|
|
262
|
+
true,
|
|
263
|
+
true,
|
|
264
|
+
true,
|
|
265
|
+
false,
|
|
266
|
+
false,
|
|
267
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+
true,
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+
true,
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false,
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|
+
true,
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271
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+
false,
|
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272
|
+
false,
|
|
273
|
+
false,
|
|
274
|
+
false,
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275
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+
false,
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276
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+
false,
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277
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+
false,
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278
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+
false,
|
|
279
|
+
false,
|
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280
|
+
false,
|
|
281
|
+
false,
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282
|
+
false,
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283
|
+
false,
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+
false,
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false,
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+
false,
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|
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false,
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false,
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false,
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false,
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false,
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false,
|
|
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+
false,
|
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294
|
+
false,
|
|
295
|
+
false,
|
|
296
|
+
false,
|
|
297
|
+
false,
|
|
298
|
+
false,
|
|
299
|
+
false,
|
|
300
|
+
false,
|
|
301
|
+
false,
|
|
302
|
+
false,
|
|
303
|
+
false,
|
|
304
|
+
false,
|
|
305
|
+
false,
|
|
306
|
+
false,
|
|
307
|
+
false,
|
|
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|
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false,
|
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|
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false,
|
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|
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false,
|
|
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|
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false,
|
|
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|
+
false,
|
|
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|
+
false,
|
|
314
|
+
false,
|
|
315
|
+
false,
|
|
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|
+
false,
|
|
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|
+
false,
|
|
318
|
+
false,
|
|
319
|
+
]
|
|
320
|
+
MIDELEG_DELEGATABLE:
|
|
321
|
+
[
|
|
322
|
+
false,
|
|
323
|
+
false,
|
|
324
|
+
false,
|
|
325
|
+
false,
|
|
326
|
+
false,
|
|
327
|
+
false,
|
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328
|
+
false,
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329
|
+
false,
|
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330
|
+
false,
|
|
331
|
+
false,
|
|
332
|
+
false,
|
|
333
|
+
false,
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|
334
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+
false,
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+
false,
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336
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+
false,
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337
|
+
false,
|
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338
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+
false,
|
|
339
|
+
false,
|
|
340
|
+
false,
|
|
341
|
+
false,
|
|
342
|
+
false,
|
|
343
|
+
false,
|
|
344
|
+
false,
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|
345
|
+
false,
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|
346
|
+
false,
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|
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|
+
false,
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|
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false,
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349
|
+
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|
+
false,
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|
351
|
+
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|
352
|
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|
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|
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|
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366
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367
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368
|
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|
369
|
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|
370
|
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|
371
|
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|
372
|
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false,
|
|
373
|
+
false,
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|
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|
+
false,
|
|
375
|
+
false,
|
|
376
|
+
false,
|
|
377
|
+
false,
|
|
378
|
+
false,
|
|
379
|
+
false,
|
|
380
|
+
false,
|
|
381
|
+
false,
|
|
382
|
+
false,
|
|
383
|
+
false,
|
|
384
|
+
false,
|
|
385
|
+
false,
|
|
386
|
+
]
|
data/.data/cfgs/rv64-vector.yaml
CHANGED
|
@@ -290,3 +290,137 @@ params:
|
|
|
290
290
|
WFI_U_MODE: false
|
|
291
291
|
WFI_FINITE: true
|
|
292
292
|
NON_STANDARD_EXTENSION_IMPLEMENTED: false
|
|
293
|
+
MEDELEG_DELEGATABLE:
|
|
294
|
+
[
|
|
295
|
+
true,
|
|
296
|
+
true,
|
|
297
|
+
true,
|
|
298
|
+
true,
|
|
299
|
+
true,
|
|
300
|
+
true,
|
|
301
|
+
true,
|
|
302
|
+
true,
|
|
303
|
+
true,
|
|
304
|
+
true,
|
|
305
|
+
false,
|
|
306
|
+
false,
|
|
307
|
+
true,
|
|
308
|
+
true,
|
|
309
|
+
false,
|
|
310
|
+
true,
|
|
311
|
+
false,
|
|
312
|
+
false,
|
|
313
|
+
false,
|
|
314
|
+
false,
|
|
315
|
+
false,
|
|
316
|
+
false,
|
|
317
|
+
false,
|
|
318
|
+
false,
|
|
319
|
+
false,
|
|
320
|
+
false,
|
|
321
|
+
false,
|
|
322
|
+
false,
|
|
323
|
+
false,
|
|
324
|
+
false,
|
|
325
|
+
false,
|
|
326
|
+
false,
|
|
327
|
+
false,
|
|
328
|
+
false,
|
|
329
|
+
false,
|
|
330
|
+
false,
|
|
331
|
+
false,
|
|
332
|
+
false,
|
|
333
|
+
false,
|
|
334
|
+
false,
|
|
335
|
+
false,
|
|
336
|
+
false,
|
|
337
|
+
false,
|
|
338
|
+
false,
|
|
339
|
+
false,
|
|
340
|
+
false,
|
|
341
|
+
false,
|
|
342
|
+
false,
|
|
343
|
+
false,
|
|
344
|
+
false,
|
|
345
|
+
false,
|
|
346
|
+
false,
|
|
347
|
+
false,
|
|
348
|
+
false,
|
|
349
|
+
false,
|
|
350
|
+
false,
|
|
351
|
+
false,
|
|
352
|
+
false,
|
|
353
|
+
false,
|
|
354
|
+
false,
|
|
355
|
+
false,
|
|
356
|
+
false,
|
|
357
|
+
false,
|
|
358
|
+
false,
|
|
359
|
+
]
|
|
360
|
+
MIDELEG_DELEGATABLE:
|
|
361
|
+
[
|
|
362
|
+
false,
|
|
363
|
+
false,
|
|
364
|
+
false,
|
|
365
|
+
false,
|
|
366
|
+
false,
|
|
367
|
+
false,
|
|
368
|
+
false,
|
|
369
|
+
false,
|
|
370
|
+
false,
|
|
371
|
+
false,
|
|
372
|
+
false,
|
|
373
|
+
false,
|
|
374
|
+
false,
|
|
375
|
+
false,
|
|
376
|
+
false,
|
|
377
|
+
false,
|
|
378
|
+
false,
|
|
379
|
+
false,
|
|
380
|
+
false,
|
|
381
|
+
false,
|
|
382
|
+
false,
|
|
383
|
+
false,
|
|
384
|
+
false,
|
|
385
|
+
false,
|
|
386
|
+
false,
|
|
387
|
+
false,
|
|
388
|
+
false,
|
|
389
|
+
false,
|
|
390
|
+
false,
|
|
391
|
+
false,
|
|
392
|
+
false,
|
|
393
|
+
false,
|
|
394
|
+
false,
|
|
395
|
+
false,
|
|
396
|
+
false,
|
|
397
|
+
false,
|
|
398
|
+
false,
|
|
399
|
+
false,
|
|
400
|
+
false,
|
|
401
|
+
false,
|
|
402
|
+
false,
|
|
403
|
+
false,
|
|
404
|
+
false,
|
|
405
|
+
false,
|
|
406
|
+
false,
|
|
407
|
+
false,
|
|
408
|
+
false,
|
|
409
|
+
false,
|
|
410
|
+
false,
|
|
411
|
+
false,
|
|
412
|
+
false,
|
|
413
|
+
false,
|
|
414
|
+
false,
|
|
415
|
+
false,
|
|
416
|
+
false,
|
|
417
|
+
false,
|
|
418
|
+
false,
|
|
419
|
+
false,
|
|
420
|
+
false,
|
|
421
|
+
false,
|
|
422
|
+
false,
|
|
423
|
+
false,
|
|
424
|
+
false,
|
|
425
|
+
false,
|
|
426
|
+
]
|
|
@@ -1,6 +1,6 @@
|
|
|
1
1
|
{
|
|
2
2
|
"$schema": "http://json-schema.org/draft-07/schema#",
|
|
3
|
-
"$id": "v0.
|
|
3
|
+
"$id": "v0.3",
|
|
4
4
|
"title": "Common patterns used by all schemas",
|
|
5
5
|
"$defs": {
|
|
6
6
|
"$source": {
|
|
@@ -638,6 +638,9 @@
|
|
|
638
638
|
},
|
|
639
639
|
{
|
|
640
640
|
"type": "string"
|
|
641
|
+
},
|
|
642
|
+
{
|
|
643
|
+
"type": "boolean"
|
|
641
644
|
}
|
|
642
645
|
]
|
|
643
646
|
},
|
|
@@ -84,6 +84,13 @@ description: |
|
|
|
84
84
|
<%%- end -%>
|
|
85
85
|
.
|
|
86
86
|
<%%- end -%>
|
|
87
|
+
<%%- if ext?(:Smcdeleg) -%>
|
|
88
|
+
|
|
89
|
+
When the Smcdeleg/Ssccfg extensions are enabled (`menvcfg.CDE`=1), `mcounteren` further
|
|
90
|
+
allows M-mode to delegate select counters to S-mode. When a counter _i_ is delegated
|
|
91
|
+
(`mcounteren`[_i_]=1 and `menvcfg.CDE`=1), the register state associated with counter _i_
|
|
92
|
+
can be read or written via `sireg*`, while `siselect` holds 0x40+_i_.
|
|
93
|
+
<%%- end -%>
|
|
87
94
|
definedBy:
|
|
88
95
|
extension:
|
|
89
96
|
name: U # actually, defined by RV64, but must implement U-mode for this CSR to exist
|
|
@@ -87,6 +87,13 @@ description: |
|
|
|
87
87
|
<%- end -%>
|
|
88
88
|
.
|
|
89
89
|
<%- end -%>
|
|
90
|
+
<%- if ext?(:Smcdeleg) -%>
|
|
91
|
+
|
|
92
|
+
When the Smcdeleg/Ssccfg extensions are enabled (`menvcfg.CDE`=1), `mcounteren` further
|
|
93
|
+
allows M-mode to delegate select counters to S-mode. When a counter _i_ is delegated
|
|
94
|
+
(`mcounteren`[_i_]=1 and `menvcfg.CDE`=1), the register state associated with counter _i_
|
|
95
|
+
can be read or written via `sireg*`, while `siselect` holds 0x40+_i_.
|
|
96
|
+
<%- end -%>
|
|
90
97
|
definedBy:
|
|
91
98
|
extension:
|
|
92
99
|
name: U # actually, defined by RV64, but must implement U-mode for this CSR to exist
|
|
@@ -0,0 +1,111 @@
|
|
|
1
|
+
# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
|
|
2
|
+
# SPDX-License-Identifier: BSD-3-Clause-Clear
|
|
3
|
+
|
|
4
|
+
# yaml-language-server: $schema=../../../../schemas/csr_schema.json
|
|
5
|
+
|
|
6
|
+
$schema: csr_schema.json#
|
|
7
|
+
kind: csr
|
|
8
|
+
name: scountinhibit
|
|
9
|
+
long_name: Supervisor Counter Inhibit
|
|
10
|
+
address: 0x120
|
|
11
|
+
writable: true
|
|
12
|
+
priv_mode: S
|
|
13
|
+
length: 32
|
|
14
|
+
description: |
|
|
15
|
+
`scountinhibit` is a masked alias of `mcountinhibit`. For counters delegated to S-mode,
|
|
16
|
+
the associated `mcountinhibit` bits can be accessed via `scountinhibit`. For counters
|
|
17
|
+
not delegated to S-mode, the associated bits in `scountinhibit` are read-only zero.
|
|
18
|
+
|
|
19
|
+
A counter _i_ is delegated to S-mode when `mcounteren`[_i_]=1 and `menvcfg.CDE`=1.
|
|
20
|
+
|
|
21
|
+
When `menvcfg.CDE`=0, attempts to access `scountinhibit` raise an `Illegal Instruction`
|
|
22
|
+
exception. When Supervisor Counter Delegation is enabled, attempts to access
|
|
23
|
+
`scountinhibit` from VS-mode or VU-mode raise a `Virtual Instruction` exception.
|
|
24
|
+
definedBy:
|
|
25
|
+
allOf:
|
|
26
|
+
- extension:
|
|
27
|
+
name: Ssccfg
|
|
28
|
+
- param:
|
|
29
|
+
name: MCOUNTINHIBIT_IMPLEMENTED
|
|
30
|
+
equal: true
|
|
31
|
+
sw_read(): |
|
|
32
|
+
if (CSR[menvcfg].CDE == 1'b0) {
|
|
33
|
+
raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
|
|
34
|
+
}
|
|
35
|
+
if (virtual_mode?()) {
|
|
36
|
+
raise(ExceptionCode::VirtualInstruction, mode(), $encoding);
|
|
37
|
+
}
|
|
38
|
+
return $bits(CSR[mcountinhibit]) & $bits(CSR[mcounteren]);
|
|
39
|
+
fields:
|
|
40
|
+
CY:
|
|
41
|
+
location: 0
|
|
42
|
+
alias: mcountinhibit.CY
|
|
43
|
+
description: |
|
|
44
|
+
Alias of `mcountinhibit.CY` when `mcycle` is delegated to S-mode (`mcounteren.CY`=1);
|
|
45
|
+
otherwise read-only zero.
|
|
46
|
+
type(): |
|
|
47
|
+
return COUNTINHIBIT_EN[0] ? CsrFieldType::RWR : CsrFieldType::RO;
|
|
48
|
+
reset_value(): |
|
|
49
|
+
return COUNTINHIBIT_EN[0] ? UNDEFINED_LEGAL : 0;
|
|
50
|
+
sw_write(csr_value): |
|
|
51
|
+
if (CSR[menvcfg].CDE == 1'b0) {
|
|
52
|
+
raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
|
|
53
|
+
}
|
|
54
|
+
if (virtual_mode?()) {
|
|
55
|
+
raise(ExceptionCode::VirtualInstruction, mode(), $encoding);
|
|
56
|
+
}
|
|
57
|
+
if (CSR[mcounteren].CY == 1'b1) {
|
|
58
|
+
CSR[mcountinhibit].CY = csr_value.CY;
|
|
59
|
+
return csr_value.CY;
|
|
60
|
+
}
|
|
61
|
+
return 1'b0;
|
|
62
|
+
IR:
|
|
63
|
+
location: 2
|
|
64
|
+
alias: mcountinhibit.IR
|
|
65
|
+
description: |
|
|
66
|
+
Alias of `mcountinhibit.IR` when `minstret` is delegated to S-mode (`mcounteren.IR`=1);
|
|
67
|
+
otherwise read-only zero.
|
|
68
|
+
type(): |
|
|
69
|
+
return COUNTINHIBIT_EN[2] ? CsrFieldType::RWR : CsrFieldType::RO;
|
|
70
|
+
reset_value(): |
|
|
71
|
+
return COUNTINHIBIT_EN[2] ? UNDEFINED_LEGAL : 0;
|
|
72
|
+
sw_write(csr_value): |
|
|
73
|
+
if (CSR[menvcfg].CDE == 1'b0) {
|
|
74
|
+
raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
|
|
75
|
+
}
|
|
76
|
+
if (virtual_mode?()) {
|
|
77
|
+
raise(ExceptionCode::VirtualInstruction, mode(), $encoding);
|
|
78
|
+
}
|
|
79
|
+
if (CSR[mcounteren].IR == 1'b1) {
|
|
80
|
+
CSR[mcountinhibit].IR = csr_value.IR;
|
|
81
|
+
return csr_value.IR;
|
|
82
|
+
}
|
|
83
|
+
return 1'b0;
|
|
84
|
+
<%- (3..31).each do |hpm_num| -%>
|
|
85
|
+
HPM<%= hpm_num %>:
|
|
86
|
+
location: <%= hpm_num %>
|
|
87
|
+
alias: mcountinhibit.HPM<%= hpm_num %>
|
|
88
|
+
description: |
|
|
89
|
+
[when="COUNTINHIBIT_EN[<%= hpm_num %>] == true"]
|
|
90
|
+
Alias of `mcountinhibit.HPM<%= hpm_num %>` when `mhpmcounter<%= hpm_num %>` is delegated to S-mode
|
|
91
|
+
(`mcounteren.HPM<%= hpm_num %>`=1); otherwise read-only zero.
|
|
92
|
+
|
|
93
|
+
[when="COUNTINHIBIT_EN[<%= hpm_num %>] == false"]
|
|
94
|
+
Since `mcountinhibit.HPM<%= hpm_num %>` is not writable, this field is read-only zero.
|
|
95
|
+
type(): |
|
|
96
|
+
return COUNTINHIBIT_EN[<%= hpm_num %>] ? CsrFieldType::RWR : CsrFieldType::RO;
|
|
97
|
+
reset_value(): |
|
|
98
|
+
return COUNTINHIBIT_EN[<%= hpm_num %>] ? UNDEFINED_LEGAL : 0;
|
|
99
|
+
sw_write(csr_value): |
|
|
100
|
+
if (CSR[menvcfg].CDE == 1'b0) {
|
|
101
|
+
raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
|
|
102
|
+
}
|
|
103
|
+
if (virtual_mode?()) {
|
|
104
|
+
raise(ExceptionCode::VirtualInstruction, mode(), $encoding);
|
|
105
|
+
}
|
|
106
|
+
if (CSR[mcounteren].HPM<%= hpm_num %> == 1'b1) {
|
|
107
|
+
CSR[mcountinhibit].HPM<%= hpm_num %> = csr_value.HPM<%= hpm_num %>;
|
|
108
|
+
return csr_value.HPM<%= hpm_num %>;
|
|
109
|
+
}
|
|
110
|
+
return 1'b0;
|
|
111
|
+
<%- end -%>
|