udb 0.1.17 → 0.1.18

data/.data/spec/std/isa/inst/Zvabd/vabd.vx.yaml

@@ -0,0 +1,69 @@
+# Copyright (c) Alibaba Damo Academy
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+
+$schema: "inst_schema.json#"
+kind: instruction
+name: vabd.vx
+long_name: Vector Single-Width Signed Integer Absolute Difference with Scalar
+description: |
+  Computes the element-wise absolute difference of signed integer operands from
+  vector register vs2 and scalar register xs1, and writes the SEW-bit results to
+  vd according to mask vm. The scalar is sign-extended or truncated to SEW.
+
+  Supports SEW of 8, 16, and 32, and SEW of 64 when Zve64x is implemented.
+definedBy:
+  extension:
+    name: Zvabd
+assembly: vd, vs2, xs1, vm
+encoding:
+  match: 010101-----------110-----1010111
+  variables:
+    - name: vm
+      location: 25
+    - name: vs2
+      location: 24-20
+    - name: xs1
+      location: 19-15
+    - name: vd
+      location: 11-7
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+pseudoinstructions:
+  - when: xs1 == 0
+    to: vabs.v vd, vs2, vm
+operation(): |
+  VectorState state = vector_state();
+
+  VectorLmulType lmul_type = state.lmul_type;
+
+  XReg vlen = VLEN;
+  XReg vlmax;
+  if (lmul_type == VectorLmulType::Multiply) {
+    vlmax = (vlen << state.log2_lmul) >> state.log2_sew;
+  } else {
+    vlmax = (vlen >> state.log2_lmul) >> state.log2_sew;
+  }
+
+  Bits<64> scalar = $signed(X[xs1]);
+
+  for (U32 i = CSR[vstart].VALUE; i < CSR[vl].VALUE; i++) {
+    U32 start_bit_pos = i * state.sew;
+    U32 end_bit_pos = start_bit_pos + state.sew - 1;
+    if (vm == 1'b1 || V[0][i:i] == 1'b1) {
+      # active element
+      if ($signed(V[vs2][end_bit_pos:start_bit_pos]) >= $signed(scalar[state.sew-1:0])) {
+        V[vd][end_bit_pos:start_bit_pos] = V[vs2][end_bit_pos:start_bit_pos] - scalar[state.sew-1:0];
+      } else {
+        V[vd][end_bit_pos:start_bit_pos] = scalar[state.sew-1:0] - V[vs2][end_bit_pos:start_bit_pos];
+      }
+    }
+    # inactive element: handled according to vtype.VMA policy
+  }
+  # tail elements (i >= vl): handled according to vtype.VTA policy
+
+  CSR[vstart].VALUE = 0;

data/.data/spec/std/isa/inst/Zvabd/vabdu.vv.yaml

@@ -11,13 +11,13 @@ description: |
   Computes the element-wise absolute difference of two unsigned integer SEW-bit
   source operands vs1 and vs2 and writes the result to vd according to mask vm.
 
-  Reserved when SEW is neither 8 nor 16.
+  Supports SEW of 8, 16, and 32. If the Zve64x extension is supported, SEW 64 is also supported.
 definedBy:
   extension:
     name: Zvabd
 assembly: vd, vs2, vs1, vm
 encoding:
-  match: 010011-----------010-----1010111
+  match: 010110-----------010-----1010111
   variables:
     - name: vm
       location: 25
@@ -35,7 +35,7 @@ access:
 operation(): |
   VectorState state = vector_state();
 
-  if (state.sew != 8 && state.sew != 16) {
+  if (!implemented?(ExtensionName::Zve64x) && state.sew > 32) {
     raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
   }
 

data/.data/spec/std/isa/inst/Zvabd/{vabs.v.yaml → vabdu.vx.yaml}

@@ -5,25 +5,28 @@
 
 $schema: "inst_schema.json#"
 kind: instruction
-name: vabs.v
-long_name: Vector Single-Width Signed Integer Absolute
+name: vabdu.vx
+long_name: Vector Single-Width Unsigned Integer Absolute Difference with Scalar
 description: |
-  An absolute value operation is performed on each element of vs2, storing the
-  result in vector register vd according to mask vm.
+  Computes the element-wise absolute difference of unsigned integer operands
+  from vector register vs2 and scalar register xs1, and writes the SEW-bit
+  results to vd according to mask vm. The scalar is sign-extended or truncated
+  to SEW before being interpreted as an unsigned value.
 
-  vabs.v supports SEW of 8, 16, and 32 when Zve32x is implemented.
-  When Zve64x is implemented, vabs.v also supports SEW of 64.
+  Supports SEW of 8, 16, and 32, and SEW of 64 when Zve64x is implemented.
 definedBy:
   extension:
     name: Zvabd
-assembly: vd, vs2, vm
+assembly: vd, vs2, xs1, vm
 encoding:
-  match: 010010------10000010-----1010111
+  match: 010110-----------110-----1010111
   variables:
     - name: vm
       location: 25
     - name: vs2
       location: 24-20
+    - name: xs1
+      location: 19-15
     - name: vd
       location: 11-7
 access:
@@ -33,6 +36,7 @@ access:
   vu: always
 operation(): |
   VectorState state = vector_state();
+
   VectorLmulType lmul_type = state.lmul_type;
 
   XReg vlen = VLEN;
@@ -43,15 +47,17 @@ operation(): |
     vlmax = (vlen >> state.log2_lmul) >> state.log2_sew;
   }
 
+  Bits<64> scalar = $signed(X[xs1]);
+
   for (U32 i = CSR[vstart].VALUE; i < CSR[vl].VALUE; i++) {
     U32 start_bit_pos = i * state.sew;
     U32 end_bit_pos = start_bit_pos + state.sew - 1;
     if (vm == 1'b1 || V[0][i:i] == 1'b1) {
       # active element
-      if (V[vs2][end_bit_pos:end_bit_pos] == 1'b1) {
-        V[vd][end_bit_pos:start_bit_pos] = -$signed(V[vs2][end_bit_pos:start_bit_pos]);
+      if (V[vs2][end_bit_pos:start_bit_pos] >= scalar[state.sew-1:0]) {
+        V[vd][end_bit_pos:start_bit_pos] = V[vs2][end_bit_pos:start_bit_pos] - scalar[state.sew-1:0];
       } else {
-        V[vd][end_bit_pos:start_bit_pos] = V[vs2][end_bit_pos:start_bit_pos];
+        V[vd][end_bit_pos:start_bit_pos] = scalar[state.sew-1:0] - V[vs2][end_bit_pos:start_bit_pos];
       }
     }
     # inactive element: handled according to vtype.VMA policy

data/.data/spec/std/isa/inst/Zvabd/vwabda.vv.yaml

@@ -18,7 +18,7 @@ definedBy:
     name: Zvabd
 assembly: vd, vs2, vs1, vm
 encoding:
-  match: 010101-----------010-----1010111
+  match: 111101-----------000-----1010111
   variables:
     - name: vm
       location: 25

data/.data/spec/std/isa/inst/Zvabd/vwabda.vx.yaml

@@ -0,0 +1,73 @@
+# Copyright (c) Alibaba Damo Academy
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+
+$schema: "inst_schema.json#"
+kind: instruction
+name: vwabda.vx
+long_name: Vector Widening Signed Integer Absolute Difference and Accumulate with Scalar
+description: |
+  Computes the element-wise absolute difference of signed integer operands from
+  vector register vs2 and scalar register xs1, and accumulates the results into
+  the 2*SEW-bit elements of vd. The scalar is sign-extended or truncated to SEW.
+
+  Reserved when SEW is neither 8 nor 16.
+definedBy:
+  extension:
+    name: Zvabd
+assembly: vd, vs2, xs1, vm
+encoding:
+  match: 111101-----------100-----1010111
+  variables:
+    - name: vm
+      location: 25
+    - name: vs2
+      location: 24-20
+    - name: xs1
+      location: 19-15
+    - name: vd
+      location: 11-7
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+operation(): |
+  VectorState state = vector_state();
+
+  if (state.sew != 8 && state.sew != 16) {
+    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+  }
+
+  VectorLmulType lmul_type = state.lmul_type;
+
+  XReg vlen = VLEN;
+  XReg vlmax;
+  if (lmul_type == VectorLmulType::Multiply) {
+    vlmax = (vlen << state.log2_lmul) >> state.log2_sew;
+  } else {
+    vlmax = (vlen >> state.log2_lmul) >> state.log2_sew;
+  }
+
+  Bits<64> scalar = $signed(X[xs1]);
+  U32 sew2 = state.sew + state.sew;
+
+  for (U32 i = CSR[vstart].VALUE; i < CSR[vl].VALUE; i++) {
+    U32 src_start = i * state.sew;
+    U32 src_end = src_start + state.sew - 1;
+    U32 dst_start = i * sew2;
+    U32 dst_end = dst_start + sew2 - 1;
+    if (vm == 1'b1 || V[0][i:i] == 1'b1) {
+      # active element
+      if ($signed(V[vs2][src_end:src_start]) >= $signed(scalar[state.sew-1:0])) {
+        V[vd][dst_end:dst_start] = V[vd][dst_end:dst_start] + (V[vs2][src_end:src_start] - scalar[state.sew-1:0]);
+      } else {
+        V[vd][dst_end:dst_start] = V[vd][dst_end:dst_start] + (scalar[state.sew-1:0] - V[vs2][src_end:src_start]);
+      }
+    }
+    # inactive element: handled according to vtype.VMA policy
+  }
+  # tail elements (i >= vl): handled according to vtype.VTA policy
+
+  CSR[vstart].VALUE = 0;

data/.data/spec/std/isa/inst/Zvabd/vwabdau.vv.yaml

@@ -18,7 +18,7 @@ definedBy:
     name: Zvabd
 assembly: vd, vs2, vs1, vm
 encoding:
-  match: 010110-----------010-----1010111
+  match: 111110-----------000-----1010111
   variables:
     - name: vm
       location: 25

data/.data/spec/std/isa/inst/Zvabd/vwabdau.vx.yaml

@@ -0,0 +1,74 @@
+# Copyright (c) Alibaba Damo Academy
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+
+$schema: "inst_schema.json#"
+kind: instruction
+name: vwabdau.vx
+long_name: Vector Widening Unsigned Integer Absolute Difference and Accumulate with Scalar
+description: |
+  Computes the element-wise absolute difference of unsigned integer operands
+  from vector register vs2 and scalar register xs1, and accumulates the results
+  into the 2*SEW-bit elements of vd. The scalar is sign-extended or truncated
+  to SEW before being interpreted as an unsigned value.
+
+  Reserved when SEW is neither 8 nor 16.
+definedBy:
+  extension:
+    name: Zvabd
+assembly: vd, vs2, xs1, vm
+encoding:
+  match: 111110-----------100-----1010111
+  variables:
+    - name: vm
+      location: 25
+    - name: vs2
+      location: 24-20
+    - name: xs1
+      location: 19-15
+    - name: vd
+      location: 11-7
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+operation(): |
+  VectorState state = vector_state();
+
+  if (state.sew != 8 && state.sew != 16) {
+    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+  }
+
+  VectorLmulType lmul_type = state.lmul_type;
+
+  XReg vlen = VLEN;
+  XReg vlmax;
+  if (lmul_type == VectorLmulType::Multiply) {
+    vlmax = (vlen << state.log2_lmul) >> state.log2_sew;
+  } else {
+    vlmax = (vlen >> state.log2_lmul) >> state.log2_sew;
+  }
+
+  Bits<64> scalar = $signed(X[xs1]);
+  U32 sew2 = state.sew + state.sew;
+
+  for (U32 i = CSR[vstart].VALUE; i < CSR[vl].VALUE; i++) {
+    U32 src_start = i * state.sew;
+    U32 src_end = src_start + state.sew - 1;
+    U32 dst_start = i * sew2;
+    U32 dst_end = dst_start + sew2 - 1;
+    if (vm == 1'b1 || V[0][i:i] == 1'b1) {
+      # active element
+      if (V[vs2][src_end:src_start] >= scalar[state.sew-1:0]) {
+        V[vd][dst_end:dst_start] = V[vd][dst_end:dst_start] + (V[vs2][src_end:src_start] - scalar[state.sew-1:0]);
+      } else {
+        V[vd][dst_end:dst_start] = V[vd][dst_end:dst_start] + (scalar[state.sew-1:0] - V[vs2][src_end:src_start]);
+      }
+    }
+    # inactive element: handled according to vtype.VMA policy
+  }
+  # tail elements (i >= vl): handled according to vtype.VTA policy
+
+  CSR[vstart].VALUE = 0;

data/.data/spec/std/isa/inst/Zvfbdota32f/vfbdota.vv.yaml

@@ -0,0 +1,68 @@
+# Copyright (c) 2026 Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+$schema: "inst_schema.json#"
+kind: instruction
+name: vfbdota.vv
+long_name: Vector FP32 Batched Dot Product Accumulate
+description: |
+  Performs a batched
+  dot-product operation on FP32 vectors, accumulating into FP32. The
+  instruction is reserved unless `SEW=32` and `LMUL=1`. The `vs1`, `vs2`, and
+  `vd` operands all have `EEW=SEW`.
+
+  The batched dot-product family treats `vs1` as an EMUL=1 vector register
+  group and `vs2` as an EMUL=8 vector register group, computing eight
+  independent dot products and accumulating the results into `vd`. `vl` sets
+  the length of each dot product. Tail elements are substituted with the bit
+  pattern of all zeros, then the computation is performed as though
+  `vl=VLMAX`.
+
+  For long-vector implementations with `VLEN > 8*EEW`, `ci` is a 3-bit
+  scaled-by-8 immediate indicating which eight elements of `vd` are read and
+  written. The `ci` field is encoded in `vs2[2:0]`; those bits are not needed
+  for the register address because `vs2` addresses an EMUL=8 register group.
+  The instruction is reserved if `ci >= VLEN/(8*EEW)`. Destination elements
+  at or beyond `ci+8` are tail elements, elements below `ci` are prestart
+  elements, and the remaining elements are body elements. The destination
+  vector register group cannot overlap either source vector register group.
+  Masked-off body elements follow the current mask agnostic or undisturbed
+  policy, and the instruction is reserved when `vstart` is nonzero; exceptions
+  are always reported with `vstart=0`.
+
+  The FP32 products are first computed to full precision, setting the invalid
+  operation exception flag as appropriate. The products are then optionally
+  rounded to FP32 according to the dynamic rounding mode, setting the inexact,
+  overflow, and underflow exception flags as appropriate. The sum of these
+  products and the accumulator is then computed as though by `vfredusum.vs`
+  with `SEW=32`, including the setting of exception flags.
+
+  This formulation allows significant implementation flexibility while being
+  sufficiently precise to implement SGEMM. The algorithm used by
+  `vfredusum.vs` offers several implementation choices; implementations are
+  not required to use the same algorithm configuration for `vfbdota.vv` as for
+  `vfredusum.vs`.
+definedBy:
+  extension:
+    name: Zvfbdota32f
+assembly: vd, vs2, vs1, ci, vm
+encoding:
+  match: 101011-----------001-----1110111
+  variables:
+    - name: vm
+      location: 25-25
+    - name: vs2
+      location: 24-23
+    - name: ci
+      location: 22-20
+    - name: vs1
+      location: 19-15
+    - name: vd
+      location: 11-7
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+data_independent_timing: false
+operation(): |

data/.data/spec/std/isa/inst/Zvzip/vpaire.vv.yaml

@@ -0,0 +1,36 @@
+# Copyright (c) 2026 Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+$schema: "inst_schema.json#"
+kind: instruction
+name: vpaire.vv
+long_name: Vector pair even
+description: |
+  Interleaves even-indexed elements of two source vector register groups into
+  the destination. All operands have EMUL=LMUL. For destination index `i`,
+  even indices read `vs2[i]` and odd indices read `vs1[i-1]`, producing
+  `[vs2[0], vs1[0], vs2[2], vs1[2], ...]`. Standard vector masking,
+  prestart, inactive, and tail handling applies. The destination may not
+  overlap either source group.
+definedBy:
+  extension:
+    name: Zvzip
+assembly: vd, vs2, vs1, vm
+encoding:
+  match: 001111-----------000-----1010111
+  variables:
+    - name: vm
+      location: 25
+    - name: vs2
+      location: 24-20
+    - name: vs1
+      location: 19-15
+    - name: vd
+      location: 11-7
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+data_independent_timing: true
+operation(): |

data/.data/spec/std/isa/inst/Zvzip/vpairo.vv.yaml

@@ -0,0 +1,37 @@
+# Copyright (c) 2026 Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+$schema: "inst_schema.json#"
+kind: instruction
+name: vpairo.vv
+long_name: Vector pair odd
+description: |
+  Interleaves odd-indexed elements of two source vector register groups into
+  the destination. All operands have EMUL=LMUL. For destination index `i`,
+  even indices read `vs2[i+1]` and odd indices read `vs1[i]`, producing
+  `[vs2[1], vs1[1], vs2[3], vs1[3], ...]`. When `vl` is odd, the final
+  out-of-range source position contributes zero; no source at or above `vl`
+  is read. Standard vector masking, prestart, inactive, and tail handling
+  applies. The destination may not overlap either source group.
+definedBy:
+  extension:
+    name: Zvzip
+assembly: vd, vs2, vs1, vm
+encoding:
+  match: 001111-----------010-----1010111
+  variables:
+    - name: vm
+      location: 25
+    - name: vs2
+      location: 24-20
+    - name: vs1
+      location: 19-15
+    - name: vd
+      location: 11-7
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+data_independent_timing: true
+operation(): |

data/.data/spec/std/isa/inst/Zvzip/vunzipe.v.yaml

@@ -0,0 +1,33 @@
+# Copyright (c) 2026 Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+$schema: "inst_schema.json#"
+kind: instruction
+name: vunzipe.v
+long_name: Vector unzip even
+description: |
+  Extracts even-indexed elements from source vector register group `vs2`,
+  with EMUL=2*LMUL, into destination `vd`, with EMUL=LMUL. For `0 <= i < vl`,
+  `vd[i] = vs2[2*i]`; source indices below `2*vl` may be read. `LMUL=8`
+  and masked encodings (`vm=0`) are illegal. Destination/source overlap is
+  allowed only when `vd` equals `vs2`, as for narrowing instructions.
+definedBy:
+  extension:
+    name: Zvzip
+assembly: vd, vs2, vm
+encoding:
+  match: 010010------01011010-----1010111
+  variables:
+    - name: vm
+      location: 25
+    - name: vs2
+      location: 24-20
+    - name: vd
+      location: 11-7
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+data_independent_timing: true
+operation(): |

data/.data/spec/std/isa/inst/Zvzip/vunzipo.v.yaml

@@ -0,0 +1,33 @@
+# Copyright (c) 2026 Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+$schema: "inst_schema.json#"
+kind: instruction
+name: vunzipo.v
+long_name: Vector unzip odd
+description: |
+  Extracts odd-indexed elements from source vector register group `vs2`,
+  with EMUL=2*LMUL, into destination `vd`, with EMUL=LMUL. For `0 <= i < vl`,
+  `vd[i] = vs2[2*i+1]`; source indices below `2*vl` may be read. `LMUL=8`
+  and masked encodings (`vm=0`) are illegal. Destination/source overlap is
+  allowed only when `vd` equals `vs2`, as for narrowing instructions.
+definedBy:
+  extension:
+    name: Zvzip
+assembly: vd, vs2, vm
+encoding:
+  match: 010010------01111010-----1010111
+  variables:
+    - name: vm
+      location: 25
+    - name: vs2
+      location: 24-20
+    - name: vd
+      location: 11-7
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+data_independent_timing: true
+operation(): |

data/.data/spec/std/isa/inst/Zvzip/vzip.vv.yaml

@@ -0,0 +1,37 @@
+# Copyright (c) 2026 Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+$schema: "inst_schema.json#"
+kind: instruction
+name: vzip.vv
+long_name: Vector zip
+description: |
+  Interleaves source vector register groups `vs2` and `vs1`, each with
+  EMUL=LMUL/2, into destination `vd` with EMUL=LMUL. For destination index
+  `i`, even indices read `vs2[i/2]` and odd indices read `vs1[i/2]`.
+  Standard vector masking, prestart, inactive, and tail handling applies.
+  The source and destination groups may overlap only when source EMUL is at
+  least 1 and their highest-numbered registers coincide. The encoding is
+  illegal when `2*SEW > LMUL * ELEN` or overlap rules are violated.
+definedBy:
+  extension:
+    name: Zvzip
+assembly: vd, vs2, vs1, vm
+encoding:
+  match: 111110-----------010-----1010111
+  variables:
+    - name: vm
+      location: 25
+    - name: vs2
+      location: 24-20
+    - name: vs1
+      location: 19-15
+    - name: vd
+      location: 11-7
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+data_independent_timing: true
+operation(): |

data/.data/spec/std/isa/isa/builtin_functions.idl

@@ -656,6 +656,38 @@ builtin function atomically_set_pte_a_d {
   }
 }
 
+builtin function atomic_read_modify_write_8 {
+  returns Bits<8>
+  arguments
+    Bits<PHYS_ADDR_WIDTH>  phys_addr,
+    Bits<8>                value,
+    AmoOperation           op
+  description {
+    Atomically read-modify-write 8-bits starting at phys_address using +value+ and +op+.
+
+    Return the original (unmodified) read value.
+
+    All access checks/alignment checks/etc. should be done before calling this function;
+    it's assumed the RMW is OK to proceed.
+  }
+}
+
+builtin function atomic_read_modify_write_16 {
+  returns Bits<16>
+  arguments
+    Bits<PHYS_ADDR_WIDTH>  phys_addr,
+    Bits<16>               value,
+    AmoOperation           op
+  description {
+    Atomically read-modify-write 16-bits starting at phys_address using +value+ and +op+.
+
+    Return the original (unmodified) read value.
+
+    All access checks/alignment checks/etc. should be done before calling this function;
+    it's assumed the RMW is OK to proceed.
+  }
+}
+
 builtin function atomic_read_modify_write_32 {
   returns Bits<32>
   arguments
@@ -687,3 +719,22 @@ builtin function atomic_read_modify_write_64 {
     it's assumed the RMW is OK to proceed.
   }
 }
+builtin function read_seed {
+ returns Bits<32>
+ description {
+   Poll the implementation's entropy source and return the 32-bit seed value.
+   Bits 31:30 hold the OPST status and bits 15:0 hold the entropy, which is
+   only meaningful when OPST is ES16. Each poll returns unique randomness,
+   even if its numerical value happens to match a previous poll.
+   A single call represents one complete poll, so the status and the entropy
+   it returns describe the same state of the source.
+ }
+}
+builtin function write_seed {
+ description {
+   Signal a write to the seed CSR.
+   The written value is ignored; the write exists to signal polling and
+   flushing, so an implementation may use this to advance the state of its
+   entropy source.
+ }
+}