udb 0.1.17 → 0.1.18

data/.data/spec/std/isa/isa/globals.isa

@@ -945,6 +945,76 @@ function xlen {
   }
 }
 
+enum Endian {
+  Little  0
+  Big     1
+}
+
+function endianness {
+  returns Endian
+  description {
+    Returns the endianness for the effective privilege mode.
+  }
+  body {
+    if (effective_ldst_mode() == PrivilegeMode::M) {
+      if (CSR[mstatus].MBE == 1'b1) {
+        return Endian::Big;
+      } else {
+        return Endian::Little;
+      }
+    } else if (implemented?(ExtensionName::S) && effective_ldst_mode() == PrivilegeMode::S) {
+      if (CSR[mstatus].SBE == 1'b1) {
+        return Endian::Big;
+      } else {
+        return Endian::Little;
+      }
+    } else if (implemented?(ExtensionName::U) && effective_ldst_mode() == PrivilegeMode::U) {
+      if (CSR[mstatus].UBE == 1'b1) {
+        return Endian::Big;
+      } else {
+        return Endian::Little;
+      }
+    } else if (implemented?(ExtensionName::H)) {
+      if (effective_ldst_mode() == PrivilegeMode::VS) {
+        if(CSR[hstatus].VSBE == 1'b1) {
+          return Endian::Big;
+        } else {
+          return Endian::Little;
+        }
+      } else if (effective_ldst_mode() == PrivilegeMode::VU) {
+        if(CSR[vsstatus].UBE == 1'b1) {
+          return Endian::Big;
+        } else {
+          return Endian::Little;
+        }
+      } else {
+        unreachable();
+      }
+    } else {
+      unreachable();
+    }
+  }
+}
+
+function byte_swap {
+  returns XReg
+  arguments
+    U32 LEN,
+    XReg value
+  description {
+    Swaps bytes in register based on LEN.
+  }
+  body {
+    XReg result;
+
+    result = 0;
+    for (U32 i=0; i < LEN; i = i+8) {
+      result[(i+7):i] = value[(LEN-1-i):(LEN-8-i)];
+    }
+    return result;
+  }
+}
+
 function virtual_mode? {
   returns Boolean
   description {
@@ -2627,9 +2697,19 @@ function read_memory {
   body {
     Boolean aligned = is_naturally_aligned(LEN, virtual_address);
     XReg physical_address;
+    XReg result;
 
     if (aligned) {
-      return read_memory_aligned(LEN, virtual_address, encoding, 1'b0, 1'b0);
+      result = read_memory_aligned(LEN, virtual_address, encoding, 1'b0, 1'b0);
+      if (LEN > 8 && endianness() == Endian::Big ) {
+        U32 tmp;
+        for (U32 i=0; i < LEN/2; i = i+8) {
+          tmp = result[(i+7):i];
+          result[(i+7):i] = result[(LEN-1-i):(LEN-8-i)];
+          result[(LEN-1-i):(LEN-8-i)] = tmp[7:0];
+        }
+      }
+      return result;
     }
 
     # access isn't naturally aligned, but it still might be atomic if this hart supports
@@ -2646,7 +2726,16 @@ function read_memory {
 
       if (misaligned_is_atomic?(LEN, physical_address)) {
         access_check(physical_address, LEN, virtual_address, MemoryOperation::Read, ExceptionCode::LoadAccessFault, effective_ldst_mode());
-        return read_physical_memory(LEN, physical_address);
+        result = read_physical_memory(LEN, physical_address);
+        if (LEN > 8 && endianness() == Endian::Big) {
+          U32 tmp;
+          for (U32 i=0; i < LEN/2; i = i+8) {
+            tmp = result[(i+7):i];
+            result[(i+7):i] = result[(LEN-1-i):(LEN-8-i)];
+            result[(LEN-1-i):(LEN-8-i)] = tmp[7:0];
+          }
+        }
+        return result;
       }
     }
 
@@ -2666,10 +2755,18 @@ function read_memory {
 
       # misaligned, must break into multiple reads
       if (MISALIGNED_SPLIT_STRATEGY == "sequential_bytes") {
-        XReg result = 0;
+        result = 0;
         for (U32 I = 0; I < (LEN/8); I++) {
           result = result | (read_memory_aligned(8, virtual_address + I, encoding, 1'b0, 1'b0) `<< (8*I));
         }
+        if(LEN > 8 && endianness() == Endian::Big) {
+          U32 tmp;
+          for (U32 i=0; i < LEN/2; i = i+8) {
+            tmp = result[(i+7):i];
+            result[(i+7):i] = result[(LEN-1-i):(LEN-8-i)];
+            result[(LEN-1-i):(LEN-8-i)] = tmp[7:0];
+          }
+        }
         return result;
       } else if (MISALIGNED_SPLIT_STRATEGY == "custom") {
         unpredictable("An implementation is free to break a misaligned access any way, leading to unpredictable behavior when any part of the misaligned access causes an exception");
@@ -2972,10 +3069,16 @@ function amo {
       raise (ExceptionCode::StoreAmoAddressMisaligned, mode(), virtual_address);
     }
 
-    if (N == 32) {
+    if (N == 8) {
+      return atomic_read_modify_write_8(physical_address, value, op);
+    } else if (N == 16) {
+      return atomic_read_modify_write_16(physical_address, value, op);
+    } else if (N == 32) {
       return atomic_read_modify_write_32(physical_address, value, op);
-    } else {
+    } else if (N == 64) {
       return atomic_read_modify_write_64(physical_address, value, op);
+    } else {
+      unreachable();
     }
 
   }
@@ -3033,6 +3136,15 @@ function write_memory {
     Boolean aligned = is_naturally_aligned(LEN, virtual_address);
     XReg physical_address;
 
+    if(LEN > 8 && endianness() == Endian::Big) {
+      U32 tmp;
+      for (U32 i=0; i < LEN/2; i = i+8) {
+        tmp = value[(i+7):i];
+        value[(i+7):i] = value[(LEN-1-i):(LEN-8-i)];
+        value[(LEN-1-i):(LEN-8-i)] = tmp[7:0];
+      }
+    }
+
     if (aligned) {
       write_memory_aligned(LEN, virtual_address, value, encoding, 1'b0, 1'b0);
       return;

data/.data/spec/std/isa/param/HCONTEXT_IMPLEMENTED.yaml

@@ -0,0 +1,29 @@
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../schemas/param_schema.json
+
+$schema: param_schema.json#
+kind: parameter
+name: HCONTEXT_IMPLEMENTED
+description: |
+  Specifies if the hcontext CSR is implemented
+long_name: hcontext CSR is implemented
+schema:
+  type: boolean
+definedBy:
+  allOf:
+    - extension:
+        name: Sdtrig
+    - extension:
+        name: H
+requirements:
+  if:
+    param:
+      name: HCONTEXT_IMPLEMENTED
+      equal: true
+  then:
+    param:
+      name: MCONTEXT_IMPLEMENTED
+      equal: true
+      reason: HCONTEXT cannot exist without MCONTEXT

data/.data/spec/std/isa/param/{MCONTEXT_AVAILABLE.yaml → MCONTEXT_IMPLEMENTED.yaml}

@@ -5,10 +5,10 @@
 
 $schema: param_schema.json#
 kind: parameter
-name: MCONTEXT_AVAILABLE
+name: MCONTEXT_IMPLEMENTED
 description: |
-  Specifies if MCONTEXT is available
-long_name: TODO
+  Specifies if the mcontext CSR is implemented
+long_name: mcontext CSR is implemented
 schema:
   type: boolean
 definedBy:

data/.data/spec/std/isa/param/MEDELEG_DELEGATABLE.yaml

@@ -0,0 +1,121 @@
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../schemas/param_schema.json
+
+$schema: param_schema.json#
+kind: parameter
+name: MEDELEG_DELEGATABLE
+description: |
+  Indicates which synchronous exceptions can be delegated via `medeleg`.
+
+  Entry _i_ corresponds to `medeleg` bit _i_, whose index is the exception code reported in `mcause`.
+  When an entry is true, the corresponding `medeleg` bit is writable.
+  When an entry is false, the corresponding `medeleg` bit is read-only zero.
+
+  An implementation may support any subset of the delegatable exceptions,
+  but no bit of `medeleg` may be read-only one.
+
+  `MEDELEG_DELEGATABLE[11]` (environment call from M-mode) and
+  `MEDELEG_DELEGATABLE[16]` (double trap) must always be false.
+long_name: Exceptions that can be delegated through medeleg
+schema:
+  type: array
+  items:
+    type: boolean
+  maxItems: 64
+  minItems: 64
+definedBy:
+  extension:
+    name: S
+requirements:
+  allOf:
+    # medeleg[11] (ECALL from M-mode) and medeleg[16] (double trap) are read-only zero
+    - param:
+        allOf:
+          - name: MEDELEG_DELEGATABLE
+            index: 11
+            equal: false
+          - name: MEDELEG_DELEGATABLE
+            index: 16
+            equal: false
+    # Reserved exception codes (14, 17, 32-47) cannot be delegated
+    - param:
+        allOf:
+          - name: MEDELEG_DELEGATABLE
+            index: 14
+            equal: false
+          - name: MEDELEG_DELEGATABLE
+            index: 17
+            equal: false
+          - name: MEDELEG_DELEGATABLE
+            index: 32
+            equal: false
+          - name: MEDELEG_DELEGATABLE
+            index: 33
+            equal: false
+          - name: MEDELEG_DELEGATABLE
+            index: 34
+            equal: false
+          - name: MEDELEG_DELEGATABLE
+            index: 35
+            equal: false
+          - name: MEDELEG_DELEGATABLE
+            index: 36
+            equal: false
+          - name: MEDELEG_DELEGATABLE
+            index: 37
+            equal: false
+          - name: MEDELEG_DELEGATABLE
+            index: 38
+            equal: false
+          - name: MEDELEG_DELEGATABLE
+            index: 39
+            equal: false
+          - name: MEDELEG_DELEGATABLE
+            index: 40
+            equal: false
+          - name: MEDELEG_DELEGATABLE
+            index: 41
+            equal: false
+          - name: MEDELEG_DELEGATABLE
+            index: 42
+            equal: false
+          - name: MEDELEG_DELEGATABLE
+            index: 43
+            equal: false
+          - name: MEDELEG_DELEGATABLE
+            index: 44
+            equal: false
+          - name: MEDELEG_DELEGATABLE
+            index: 45
+            equal: false
+          - name: MEDELEG_DELEGATABLE
+            index: 46
+            equal: false
+          - name: MEDELEG_DELEGATABLE
+            index: 47
+            equal: false
+    # Exception codes 10 and 20-23 are defined by H
+    - if:
+        not:
+          extension:
+            name: H
+      then:
+        param:
+          allOf:
+            - name: MEDELEG_DELEGATABLE
+              index: 10
+              equal: false
+            - name: MEDELEG_DELEGATABLE
+              index: 20
+              equal: false
+            - name: MEDELEG_DELEGATABLE
+              index: 21
+              equal: false
+            - name: MEDELEG_DELEGATABLE
+              index: 22
+              equal: false
+            - name: MEDELEG_DELEGATABLE
+              index: 23
+              equal: false

data/.data/spec/std/isa/param/MEI_INTR_IMPL.yaml

@@ -13,7 +13,7 @@ description: |
 
   true::
     Machine-level external interrupts are implemented.
-    `mie.MEIE` and `mideleg.MEI` are writable.
+    `mie.MEIE` is writable, and `mideleg.MEI` is writable if `MIDELEG_DELEGATABLE[11]` is true.
 
   false::
     Machine-level external interrupts are not implemented.

data/.data/spec/std/isa/param/MIDELEG_DELEGATABLE.yaml

@@ -0,0 +1,177 @@
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../schemas/param_schema.json
+
+$schema: param_schema.json#
+kind: parameter
+name: MIDELEG_DELEGATABLE
+description: |
+  Indicates which interrupts can be delegated via `mideleg`.
+
+  Entry _i_ corresponds to `mideleg` bit _i_, which uses the same bit layout as `mip`.
+  When an entry is true, the corresponding interrupt can be delegated: the `mideleg` bit is writable,
+  except for bits that are always delegated, which are read-only one.
+  When an entry is false, the corresponding `mideleg` bit is read-only zero.
+
+  An unimplemented interrupt cannot be delegated, i.e., if `STI_INTR_IMPL` is false,
+  `MIDELEG_DELEGATABLE[5]` must be false.
+
+  When the H extension is implemented, VSSI, VSTI, and VSEI are always delegated to HS-mode,
+  so `MIDELEG_DELEGATABLE[2]`, `[6]`, and `[10]` must be true.
+  SGEI is also always delegated when any guest external interrupts are implemented
+  (`NUM_EXTERNAL_GUEST_INTERRUPTS` is nonzero), so `MIDELEG_DELEGATABLE[12]` must then be true;
+  otherwise it must be false.
+  When H is not implemented, all four must be false.
+long_name: Interrupts that can be delegated through mideleg
+schema:
+  type: array
+  items:
+    type: boolean
+  maxItems: 64
+  minItems: 64
+definedBy:
+  extension:
+    name: S
+requirements:
+  allOf:
+    # Reserved interrupt codes (0, 4, 8, 14, 15) cannot be delegated
+    - param:
+        allOf:
+          - name: MIDELEG_DELEGATABLE
+            index: 0
+            equal: false
+          - name: MIDELEG_DELEGATABLE
+            index: 4
+            equal: false
+          - name: MIDELEG_DELEGATABLE
+            index: 8
+            equal: false
+          - name: MIDELEG_DELEGATABLE
+            index: 14
+            equal: false
+          - name: MIDELEG_DELEGATABLE
+            index: 15
+            equal: false
+    # An unimplemented interrupt cannot be delegated
+    - if:
+        param:
+          name: MIDELEG_DELEGATABLE
+          index: 1
+          equal: true
+      then:
+        param:
+          name: SSI_INTR_IMPL
+          equal: true
+    - if:
+        param:
+          name: MIDELEG_DELEGATABLE
+          index: 3
+          equal: true
+      then:
+        param:
+          name: MSI_INTR_IMPL
+          equal: true
+    - if:
+        param:
+          name: MIDELEG_DELEGATABLE
+          index: 5
+          equal: true
+      then:
+        param:
+          name: STI_INTR_IMPL
+          equal: true
+    - if:
+        param:
+          name: MIDELEG_DELEGATABLE
+          index: 7
+          equal: true
+      then:
+        param:
+          name: MTI_INTR_IMPL
+          equal: true
+    - if:
+        param:
+          name: MIDELEG_DELEGATABLE
+          index: 9
+          equal: true
+      then:
+        param:
+          name: SEI_INTR_IMPL
+          equal: true
+    - if:
+        param:
+          name: MIDELEG_DELEGATABLE
+          index: 11
+          equal: true
+      then:
+        param:
+          name: MEI_INTR_IMPL
+          equal: true
+    # LCOFI (bit 13) is defined by Sscofpmf
+    - if:
+        not:
+          extension:
+            name: Sscofpmf
+      then:
+        param:
+          name: MIDELEG_DELEGATABLE
+          index: 13
+          equal: false
+    # VSSI, VSTI, and VSEI are always delegated to HS-mode when H is implemented
+    - if:
+        extension:
+          name: H
+      then:
+        allOf:
+          # VSSI, VSTI, and VSEI are always delegated to HS-mode when H is implemented
+          - param:
+              allOf:
+                - name: MIDELEG_DELEGATABLE
+                  index: 2
+                  equal: true
+                - name: MIDELEG_DELEGATABLE
+                  index: 6
+                  equal: true
+                - name: MIDELEG_DELEGATABLE
+                  index: 10
+                  equal: true
+          # SGEI is always delegated to HS-mode when any guest external interrupts are implemented (GEILEN nonzero)
+          - if:
+              not:
+                param:
+                  name: NUM_EXTERNAL_GUEST_INTERRUPTS
+                  equal: 0
+            then:
+              param:
+                name: MIDELEG_DELEGATABLE
+                index: 12
+                equal: true
+          - if:
+              param:
+                name: NUM_EXTERNAL_GUEST_INTERRUPTS
+                equal: 0
+            then:
+              param:
+                name: MIDELEG_DELEGATABLE
+                index: 12
+                equal: false
+    - if:
+        not:
+          extension:
+            name: H
+      then:
+        param:
+          allOf:
+            - name: MIDELEG_DELEGATABLE
+              index: 2
+              equal: false
+            - name: MIDELEG_DELEGATABLE
+              index: 6
+              equal: false
+            - name: MIDELEG_DELEGATABLE
+              index: 10
+              equal: false
+            - name: MIDELEG_DELEGATABLE
+              index: 12
+              equal: false

data/.data/spec/std/isa/param/MSI_INTR_IMPL.yaml

@@ -13,7 +13,7 @@ description: |
 
   true::
     Machine-level software interrupts are implemented.
-    `mie.MSIE` and `mideleg.MSI` are writable.
+    `mie.MSIE` is writable, and `mideleg.MSI` is writable if `MIDELEG_DELEGATABLE[3]` is true.
 
   false::
     Machine-level software interrupts are not implemented.

data/.data/spec/std/isa/param/MTI_INTR_IMPL.yaml

@@ -13,7 +13,7 @@ description: |
 
   true::
     Machine-level timer interrupts are implemented.
-    `mie.MTIE`, `mideleg.MTI`, and `mtimecmp` are writable.
+    `mie.MTIE` and `mtimecmp` are writable, and `mideleg.MTI` is writable if `MIDELEG_DELEGATABLE[7]` is true.
 
   false::
     Machine-level timer interrupts are not implemented.

data/.data/spec/std/isa/param/SCONTEXT_IMPLEMENTED.yaml

@@ -0,0 +1,18 @@
+# Copyright (C) 2026 Harvey Mudd College
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../schemas/param_schema.json
+
+$schema: param_schema.json#
+kind: parameter
+name: SCONTEXT_IMPLEMENTED
+description: |
+  Specifies if the scontext CSR is implemented
+long_name: scontext CSR is implemented
+schema:
+  type: boolean
+definedBy:
+  extension:
+    allOf:
+      - name: Sdtrig
+      - name: S

data/.data/spec/std/isa/param/SDTRIG_BREAKPOINT_REENTRANCY.yaml

@@ -0,0 +1,45 @@
+# Copyright (C) 2026 Harvey Mudd College
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../schemas/param_schema.json
+
+$schema: param_schema.json#
+kind: parameter
+name: SDTRIG_BREAKPOINT_REENTRANCY
+description: |
+  How the hart prevents triggers with action=0 (breakpoint exception) from re-firing
+  inside their own handler (Debug spec 1.0, Sdtrig "Native Triggers").
+
+  * No_reentrancy_support: no specific support for reentrancy.
+  * Use_interrupt_enables: triggers with action=0 do not match or fire in M-mode while
+    mstatus.MIE is 0 (and likewise S/VS-mode with sstatus.SIE / vsstatus.SIE when delegated).
+  * Use_tcontrol: tcontrol.mte and tcontrol.mpte are implemented, and medeleg[3] is hard-wired to 0.
+long_name: Breakpoint reentrancy mechanism
+schema:
+  type: string
+  enum:
+    - No_reentrancy_support
+    - Use_interrupt_enables
+    - Use_tcontrol
+requirements:
+  if:
+    param:
+      name: SDTRIG_BREAKPOINT_REENTRANCY
+      equal: Use_tcontrol
+  then:
+    allOf:
+      - param:
+          name: TCONTROL_IMPLEMENTED
+          equal: true
+          reason: The Use_tcontrol mechanism requires the tcontrol CSR.
+      - if:
+          extension:
+            name: S
+        then:
+          param:
+            name: MEDELEG_DELEGATABLE
+            index: 3
+            equal: false
+definedBy:
+  extension:
+    name: Sdtrig

data/.data/spec/std/isa/param/SDTRIG_ETRIGGER_SUPPORTED_EXCEPTIONS.yaml

@@ -0,0 +1,37 @@
+# Copyright (C) 2026 Harvey Mudd College
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../schemas/param_schema.json
+
+$schema: param_schema.json#
+kind: parameter
+name: SDTRIG_ETRIGGER_SUPPORTED_EXCEPTIONS
+description: |
+  The set of exception codes (mcause Exception Code) that etrigger can be enabled for, i.e. the bits of
+  etrigger.tdata2 that are writable as 1.
+
+  Debug spec 1.0, etrigger: "Hardware may support only a subset of exceptions."
+long_name: List of exceptions supported by etrigger
+schema:
+  type: array
+  items:
+    type: integer
+    minimum: 0
+    maximum: 63
+  maxItems: 64
+  minItems: 1
+  uniqueItems: true
+requirements:
+  idl(): |
+    for (U32 i = 32; i < 64; i++) {
+      (MXLEN == 32) -> !$array_includes?(SDTRIG_ETRIGGER_SUPPORTED_EXCEPTIONS, i);
+    }
+  reason: etrigger.tdata2 is XLEN bits wide, so codes above 31 cannot be selected when XLEN is 32.
+definedBy:
+  allOf:
+    - extension:
+        name: Sdtrig
+    - param:
+        name: SDTRIG_ETRIGGER_SUPPORTED_TRIGGERS
+        includes: true
+        reason: Only relevant if at least one trigger supports etrigger.

data/.data/spec/std/isa/param/SDTRIG_ETRIGGER_SUPPORTED_TRIGGERS.yaml

@@ -0,0 +1,25 @@
+# Copyright (C) 2026 Harvey Mudd College
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../schemas/param_schema.json
+
+$schema: param_schema.json#
+kind: parameter
+name: SDTRIG_ETRIGGER_SUPPORTED_TRIGGERS
+description: |
+  Indicates which triggers support etrigger. Entry i is true if the trigger selected by
+  tselect=i supports etrigger. Must have exactly SDTRIG_NUM_TRIGGERS entries.
+long_name: List of triggers that support etrigger
+schema:
+  type: array
+  items:
+    type: boolean
+  maxItems: 18446744073709551616 # 2**64, max tselect values (2**XLEN)
+  minItems: 0
+definedBy:
+  extension:
+    name: Sdtrig
+# TODO: uncomment when we have support for parameter comparison to other parameters
+# requirements:
+#   idl(): |
+#     -> $array_size(SDTRIG_ETRIGGER_SUPPORTED_TRIGGERS) == SDTRIG_NUM_TRIGGERS;

data/.data/spec/std/isa/param/SDTRIG_ICOUNT_COUNT_HARDWIRED_1.yaml

@@ -0,0 +1,23 @@
+# Copyright (C) 2026 Harvey Mudd College
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../schemas/param_schema.json
+
+$schema: param_schema.json#
+kind: parameter
+name: SDTRIG_ICOUNT_COUNT_HARDWIRED_1
+description: |
+  If true then icount.count is hard-wired to 1 for all icount triggers: it does not become 0 when the
+  trigger matches, and icount.m, icount.s, icount.u, icount.vs, and icount.vu are cleared when the trigger fires.
+  If false, icount.count is writable and becomes 0 when the trigger matches with a count of 1.
+long_name: icount.COUNT is hard-wired to 1
+schema:
+  type: boolean
+definedBy:
+  allOf:
+    - extension:
+        name: Sdtrig
+    - param:
+        name: SDTRIG_ICOUNT_SUPPORTED_TRIGGERS
+        includes: true
+        reason: Only relevant if at least one trigger supports icount.