badline 0.16.1 → 0.18.0

data/lib/badline/cbm2/model.rb

@@ -0,0 +1,44 @@
+# frozen_string_literal: true
+
+module Badline
+  class CBM2
+    # The B series models badline builds by name, after xcbm2's -model
+    # names: the segments the RAM board fills, the BASIC that fits it, the
+    # character ROM, and whether the board's PC7 jumper tells the editor
+    # it drives the 700's monitor.
+    module Model
+      Profile = Data.define(:name, :ram_segments, :basic, :characters, :high_profile) do
+        def ram_kb = ram_segments.length * 64
+      end
+
+      M610 = Profile.new(name: "610", ram_segments: [1, 2].freeze, basic: "cbm2/basic128.rom",
+                         characters: "cbm2/characters-600.rom", high_profile: false)
+      M620 = Profile.new(name: "620", ram_segments: [1, 2, 3, 4].freeze, basic: "cbm2/basic256.rom",
+                         characters: "cbm2/characters-600.rom", high_profile: false)
+      M710 = Profile.new(name: "710", ram_segments: [1, 2].freeze, basic: "cbm2/basic128.rom",
+                         characters: "cbm2/characters-700.rom", high_profile: true)
+      M720 = Profile.new(name: "720", ram_segments: [1, 2, 3, 4].freeze, basic: "cbm2/basic256.rom",
+                         characters: "cbm2/characters-700.rom", high_profile: true)
+
+      ALL = [M610, M620, M710, M720].freeze
+      DEFAULT = "610"
+
+      # The KERNALs a B series board takes: 901244-04a, VICE's, and
+      # 901244-03b, the 1983 release.
+      KERNALS = { "04a" => "cbm2/kernal-04a.rom", "03b" => "cbm2/kernal-03b.rom" }.freeze
+
+      def self.named(name)
+        model = ALL.find { |candidate| candidate.name == name }
+        raise ArgumentError, "no CBM-II model named #{name}" if model.nil?
+
+        model
+      end
+
+      # The BASIC +model+ runs with +kernal+: BASIC 128 of the 1983
+      # release, 02b, with 03b.
+      def self.basic(model, kernal)
+        kernal == "03b" && model.basic == "cbm2/basic128.rom" ? "cbm2/basic128-02b.rom" : model.basic
+      end
+    end
+  end
+end

data/lib/badline/cbm2/p500/control_ports.rb

@@ -0,0 +1,80 @@
+# frozen_string_literal: true
+
+module Badline
+  class CBM2
+    class P500
+      # The P500's two control ports on the CIA at $DC00, as its schematic's
+      # game port interface wires them (sheets 9 and 10): port 1's
+      # directions on PB0-PB3 and its fire button on PA6, which is the VIC's
+      # light pen input too, and port 2's on PB4-PB7 and PA7. Every switch
+      # pulls its line low. Port A carries the IEEE-488 bus's data lines as
+      # well (IEEEPorts::Data), which pull it low too.
+      #
+      # A device on a port, a pair of paddles or a mouse, adds its buttons
+      # to the port's lines, and its pots reach the SID through the analog
+      # switches PA0 (port 1) and PA1 (port 2) close, as PA6 and PA7 do on
+      # the C64 (Input::ControlPorts).
+      class ControlPorts
+        DIRECTIONS = 0x0f
+        FIRE = 0x10
+        PORT1_POTS = 0x01
+        PORT2_POTS = 0x02
+
+        attr_reader :joystick1, :joystick2
+        attr_accessor :device1, :device2
+
+        def initialize(joystick1, joystick2, ieee)
+          @joystick1 = joystick1
+          @joystick2 = joystick2
+          @ieee = ieee
+          @device1 = nil
+          @device2 = nil
+          @cia = nil
+        end
+
+        # The CIA whose PA0 and PA1 close the pots' switches.
+        def connect(cia)
+          @cia = cia
+        end
+
+        def read_a(port_a, port_b)
+          fire1 = port1.anybits?(FIRE) ? 0x40 : 0
+          fire2 = port2.anybits?(FIRE) ? 0x80 : 0
+          (0x3f | fire1 | fire2) & @ieee.read_a(port_a, port_b)
+        end
+
+        def read_b(_port_a, _port_b)
+          (port1 & DIRECTIONS) | ((port2 & DIRECTIONS) << 4)
+        end
+
+        # PB4 is port 2's up line here, not a light pen input.
+        def port_b4_high? = true
+
+        # Whether port 1's fire line is high, the light pen input's.
+        def fire1_high? = port1.anybits?(FIRE)
+
+        def pot_x = selected_devices.map(&:pot_x).min || 0xff
+
+        def pot_y = selected_devices.map(&:pot_y).min || 0xff
+
+        private
+
+        def port1 = port_bits(@joystick1, @device1)
+
+        def port2 = port_bits(@joystick2, @device2)
+
+        def port_bits(joystick, device)
+          device ? joystick.port_bits & device.port_bits : joystick.port_bits
+        end
+
+        def selected_devices
+          lines = @cia&.port_a_lines || 0x00
+          devices = []
+          devices << @device1 if @device1 && lines.anybits?(PORT1_POTS)
+          devices << @device2 if @device2 && lines.anybits?(PORT2_POTS)
+          devices
+        end
+      end
+    end
+  end
+end

data/lib/badline/cbm2/p500/ieee_layout.rb

@@ -0,0 +1,41 @@
+# frozen_string_literal: true
+
+module Badline
+  class CBM2
+    class P500
+      # Where the P500's KERNAL, 901234-02, keeps the eight IEEE-488
+      # primitives: each seven bytes above the B series' (CBM2::IEEELayout),
+      # with the same file variables in segment 15's zero page. It drives
+      # the bus from the same ports, but leaves TPI1's PA2 an input, so its
+      # writes to TPI1's port A and its direction register differ in that
+      # bit: TALK and LISTEN set DDRA to $3B and PA to $FE, TKSA and ACPTR
+      # keep $3D of PA and set DDRA to $C3, ACPTR keeps $3D of PA and sets
+      # PA0, and UNTALK and UNLISTEN leave PA $FD before letting ATN go.
+      module IEEELayout
+        LineStep = KernalTrap::IEEELineStep
+
+        def self.write(address, value) = CBM2::IEEELayout.write(address, value)
+
+        def self.update(address, keep, set) = CBM2::IEEELayout.update(address, keep, set)
+
+        ATTENTION = [write(0xde03, 0x3b), write(0xdc00, 0xff), write(0xdc02, 0xff), write(0xde00, 0xfe),
+                     update(0xde00, 0xf7, 0)].freeze
+        LISTEN_TO_TALKER = [update(0xde00, 0x3d, 0), write(0xde03, 0xc3), write(0xdc02, 0x00)].freeze
+
+        LINES = KernalTrap::IEEELines.new(
+          timer: CBM2::IEEELayout::TIMER, attention: ATTENTION, byte_sent: CBM2::IEEELayout::BYTE_SENT,
+          release_attention: CBM2::IEEELayout::RELEASE_ATTENTION, listen_to_talker: LISTEN_TO_TALKER,
+          byte_received: [update(0xde00, 0x3d, 0x01)].freeze,
+          release: (ATTENTION + CBM2::IEEELayout::BYTE_SENT + [write(0xde00, 0xfd)] + LISTEN_TO_TALKER.drop(1) +
+                    CBM2::IEEELayout::RELEASE_ATTENTION).freeze
+        )
+
+        LAYOUT = KernalTrap::IEEELayout.new(
+          talk: 0xf237, listen: 0xf23b, second: 0xf27b, tksa: 0xf287, ciout: 0xf29e, untalk: 0xf2b2,
+          unlisten: 0xf2b6, acptr: 0xf311, overwrites_device: false, device_in_a: true,
+          zero_page: CBM2::IEEELayout::ZERO_PAGE, lines: LINES
+        )
+      end
+    end
+  end
+end

data/lib/badline/cbm2/p500/keyed_state.rb

@@ -0,0 +1,85 @@
+# frozen_string_literal: true
+
+module Badline
+  class CBM2
+    class P500
+      # The machine's own fields as the B series keeps them (CBM2::KeyedState),
+      # and the whole machine as keyed snapshot modules (Snapshot::Keyed), in
+      # the order a load applies them: BL-MACHINE with the setup, the RAM
+      # with the segment registers, the colour RAM, the VIC, the SID, the
+      # CIA, the ACIA, both TPIs, the CPU, device 8 through the traps and a
+      # true 2031 on the IEEE-488 bus.
+      #
+      # A load lays the pages out before the chips load, and works out what
+      # each unit derives from its fields, the VIC's view of memory among
+      # them, once every unit is loaded.
+      module KeyedModules
+        # The SID's deferred cycles and writes, run up to this cycle, and the
+        # VIC's sprite collisions latched up to the beam.
+        def settle_chips_for_snapshot
+          @sid.catch_up!
+          @vic.fold_collisions!
+        end
+
+        def save_modules
+          bus = @bus
+          sections = [Snapshot::Keyed.section("BL-MACHINE") { |out| save_machine_fields(out) }]
+          sections << Snapshot::Keyed.section("BL-CPU") { |out| @cpu.save_fields(out) }
+          sections << Snapshot::Keyed.section("BL-RAM") { |out| bus.save_fields(out) }
+          sections << Snapshot::Keyed.section("BL-COLORRAM") { |out| @color_ram.save_fields(out, "ram") }
+          sections << Snapshot::Keyed.section("BL-VIC") { |out| @vic.save_fields(out) }
+          sections << Snapshot::Keyed.section("BL-SID") { |out| @sid.save_fields(out) }
+          sections << Snapshot::Keyed.section("BL-CIA") { |out| @cia.save_fields(out) }
+          sections << Snapshot::Keyed.section("BL-ACIA") { |out| @acia.save_fields(out) }
+          sections << Snapshot::Keyed.section("BL-TPI1") { |out| @tpi1.save_fields(out) }
+          sections << Snapshot::Keyed.section("BL-TPI2") { |out| @tpi2.save_fields(out) }
+          sections << Snapshot::Keyed.section("BL-TRAPDOS") { |out| save_trap_dos_fields(out) } if mounted?
+          save_drive_modules(sections)
+        end
+
+        # Raises Snapshot::FormatError for the modules of a machine built
+        # another way.
+        def load_modules(modules)
+          check_snapshot_setup(Snapshot::CBM2Setup.read_fields(modules.machine))
+          load_machine_fields(modules.machine)
+          @bus.load_fields(modules.required("BL-RAM"))
+          @bus.restored!
+          @color_ram.load_fields(modules.required("BL-COLORRAM"), "ram")
+          @vic.load_fields(modules.required("BL-VIC"))
+          @sid.load_fields(modules.required("BL-SID"))
+          @cia.load_fields(modules.required("BL-CIA"))
+          @acia.load_fields(modules.required("BL-ACIA"))
+          @tpi1.load_fields(modules.required("BL-TPI1"))
+          @tpi2.load_fields(modules.required("BL-TPI2"))
+          @cpu.load_fields(modules.required("BL-CPU"))
+          trap_dos = modules.optional("BL-TRAPDOS")
+          trap_dos ? load_trap_dos_fields(trap_dos, detached: modules.detached?) : unmount
+          load_drive_modules(modules)
+          restored!
+          self
+        end
+
+        private
+
+        def restored!
+          @cpu.restored!
+          @vic.restored!
+          @sid.restored!
+          @cia.restored!
+          @acia.restored!
+          update_video_bus
+        end
+
+        def check_snapshot_setup(setup)
+          ours = Snapshot::CBM2Setup.of(self)
+          return if setup == ours
+
+          raise Snapshot::FormatError, "the snapshot is of a #{setup}, not a #{ours}"
+        end
+      end
+
+      include CBM2::KeyedState
+      include KeyedModules
+    end
+  end
+end

data/lib/badline/cbm2/p500/model.rb

@@ -0,0 +1,39 @@
+# frozen_string_literal: true
+
+module Badline
+  class CBM2
+    class P500
+      # The P500s badline builds by name: the 510 of xcbm5x0's -model, PAL
+      # with the 6569 and NTSC with the 6567R8, each with its own region's
+      # mains unless told otherwise. Both have 128K of RAM, segments 0 and 1,
+      # and the one KERNAL and BASIC.
+      module Model
+        Profile = Data.define(:name, :region) do
+          def ram_kb = RAM_SEGMENTS.length * 64
+        end
+
+        M510 = Profile.new(name: "510", region: Region::PAL)
+        M510_NTSC = Profile.new(name: "510ntsc", region: Region::NTSC)
+
+        ALL = [M510, M510_NTSC].freeze
+        DEFAULT = "510"
+
+        RAM_SEGMENTS = [0, 1].freeze
+
+        # 901234-02, the KERNAL xcbm5x0 runs, and its BASIC 128, 901236-02
+        # and 901235-02.
+        KERNALS = { "02" => "cbm2/p500-kernal.rom" }.freeze
+        BASIC = "cbm2/p500-basic.rom"
+
+        def self.named(name)
+          model = ALL.find { |candidate| candidate.name == name }
+          raise ArgumentError, "no P500 model named #{name}" if model.nil?
+
+          model
+        end
+
+        def self.include?(name) = ALL.any? { |model| model.name == name }
+      end
+    end
+  end
+end

data/lib/badline/cbm2/p500/pages.rb

@@ -0,0 +1,57 @@
+# frozen_string_literal: true
+
+module Badline
+  class CBM2
+    class P500
+      # Page $D8 of segment 15: the VIC-II's 64 registers, repeated over the
+      # page.
+      class VICPage
+        def initialize(vic)
+          @vic = vic
+        end
+
+        def peek(addr) = @vic.peek(0xd000 | (addr & 0x3f))
+
+        def poke(addr, value)
+          @vic.poke(0xd000 | (addr & 0x3f), value)
+        end
+      end
+
+      # The colour RAM's four bits at $D400-$D7FF of segment 15, which the
+      # CPU reads with 0 in the high four, as xcbm5x0 does.
+      class ColorPages
+        def initialize(color_ram)
+          @color_ram = color_ram
+        end
+
+        def peek(addr) = @color_ram.nibble(addr)
+
+        def poke(addr, value)
+          @color_ram.poke(addr, value)
+        end
+      end
+
+      # A TPI's page, $DE or $DF of segment 15. TPI1's CA and CB are STATVID
+      # and VICDOTSEL, and TPI2's PC6 and PC7 the VIC's bank lines, which
+      # an access to either chip can move, so the machine takes them again
+      # after each one (P500#update_video_bus).
+      class TPIPage
+        def initialize(tpi, machine)
+          @tpi = tpi
+          @machine = machine
+        end
+
+        def peek(addr)
+          value = @tpi.peek(addr)
+          @machine.update_video_bus
+          value
+        end
+
+        def poke(addr, value)
+          @tpi.poke(addr, value)
+          @machine.update_video_bus
+        end
+      end
+    end
+  end
+end

data/lib/badline/cbm2/p500.rb

@@ -0,0 +1,264 @@
+# frozen_string_literal: true
+
+require "badline/cbm2/p500/model"
+require "badline/cbm2/p500/pages"
+require "badline/cbm2/p500/control_ports"
+require "badline/cbm2/p500/ieee_layout"
+require "badline/cbm2/p500/keyed_state"
+
+module Badline
+  class CBM2
+    # The P500, the CBM 510: the B series' 6509, SID, CIA, ACIA and TPIs on
+    # the same segment bus (Bus, CPU), at the VIC-II's clock of about
+    # 1 MHz, with a VIC-II at $D800 in place of the 6845. RAM fills segments
+    # 0 and 1.
+    #
+    # Segment 15 holds what the B series' does but for $C000-$D7FF: the
+    # character ROM at $C000, which the CPU reads too, the 1K static video
+    # matrix at $D000 and the colour RAM's nibbles at $D400. What the VIC
+    # reads follows the P500's video bus (Chips::VIC::Bank#map_video_bus):
+    # TPI1's CA is STATVID and its CB VICDOTSEL, and TPI2's PC6 and PC7
+    # drive VA14 and VA15, which pick the 16K of segment 0 the VIC sees.
+    # BA halts the CPU as on the C64, and the VIC's IRQ reaches the CPU
+    # along with TPI1's.
+    #
+    # TPI1 is the interrupt controller as on the B series, with the mains
+    # on I0, the CIA on I2 and the ACIA on I4. TPI2 scans the B series'
+    # key matrix (KeyboardPorts), and the CIA reads the two control ports
+    # (ControlPorts), whose paddles reach the SID's pots and whose port 1
+    # fire line is the VIC's light pen input. Device 8 answers through traps on the KERNAL's
+    # IEEE-488 primitives as on the B series (IEEETraps, with the P500's
+    # IEEELayout), or a true 2031, 8050 or 8250 on the bus answers, on the
+    # same ports as the B series' (IEEEPorts, IEEEDrive).
+    class P500
+      include Machine::KeyboardBuffer
+      include Machine::Clocking
+      include Machine::Settling
+      include IEEETraps
+      include IEEEDrive
+
+      # The segment BASIC keeps its program text in.
+      TEXT_SEGMENT = 0
+
+      # The ACIA at $DD00, whose IRQ reaches TPI1's I4.
+      class ACIA < Chips::ACIA
+      end
+
+      attr_reader :model, :bus, :cpu, :vic, :sid, :cia, :acia, :tpi1, :tpi2, :keyboard, :joystick1, :joystick2,
+                  :control_ports, :color_ram, :ieee, :mains_hz, :kernal, :cycles, :init_threshold
+
+      def ram = @bus.ram
+
+      # The VIC refreshes the DRAM in its own half of the cycle, so the
+      # refresh takes none of the CPU's.
+      def refresh? = false
+
+      def family = :cbm2
+
+      def peek(addr) = @bus.peek(addr)
+
+      def poke(addr, value) = @bus.poke(addr, value)
+
+      def install_debug_register(&) = @bus.install_debug_register(&)
+
+      def keyboard_buffer = CBM2::KEYBOARD_LAYOUT
+
+      def sound_source = @sid
+
+      # The VIC, whose display a front end shows.
+      def video = @vic
+
+      def region = @model.region
+
+      # +model+ names one of Model::ALL, and +mains_hz+ the mains, 50 or
+      # 60, the model's region's unless given. +true_drive_model+ names the
+      # drive plug_true_drive plugs in (Drives::IEEEModels).
+      def initialize(model: Model::DEFAULT, mains_hz: nil, debug: false, true_drive_model: Drives::IEEEModels::DEFAULT)
+        @model = Model.named(model)
+        @mains_hz = mains_hz || @model.region.mains_hz
+        raise ArgumentError, "the mains is 50 or 60 Hz, not #{@mains_hz}" unless [50, 60].include?(@mains_hz)
+
+        @kernal = Model::KERNALS.keys.first
+        clock_hz = @model.region.clock_hz
+        @bus = Bus.new(basic: Model::BASIC, kernal: Model::KERNALS.fetch(@kernal), ram_segments: Model::RAM_SEGMENTS,
+                       screen_length: 0x400)
+        @vic = Chips::VIC.new(model: :mos6569, region: @model.region)
+        @color_ram = C64::ColorMemory.new(@vic, start: 0xd400)
+        map_video
+        @ieee = IEEEPorts.new(Drives::IEEEBus.new)
+        @tpi1 = Chips::TPI.new(peripheral: @ieee)
+        @joystick1 = Input::Joystick.new
+        @joystick2 = Input::Joystick.new
+        @control_ports = ControlPorts.new(@joystick1, @joystick2, @ieee.data)
+        @sid = Chips::SID.new(model: :mos6581, pots: @control_ports, at: 0xda00)
+        @cia = Chips::CIA.new(start: 0xdc00, peripheral: @control_ports, region: @model.region, tod_hz: @mains_hz)
+        @control_ports.connect(@cia)
+        @ieee.connect(@cia, @tpi1)
+        @lightpen_high = true
+        @acia = ACIA.new(self, clock_hz)
+        @keyboard = Input::Keyboard.new(matrix: KeyboardPorts::MATRIX)
+        keyboard_ports = KeyboardPorts.new(@keyboard, 0xc0)
+        @tpi2 = Chips::TPI.new(peripheral: keyboard_ports)
+        keyboard_ports.connect(@tpi2)
+        map_io
+        @cpu = CPU.new(@bus, debug:)
+        @cycles = 0
+        @mains_half_period = clock_hz / (2 * @mains_hz)
+        @mains_countdown = @mains_half_period
+        @mains_high = true
+        # The B series' refresh counter, which CBM2::KeyedState saves: 0
+        # here, where the VIC refreshes the DRAM.
+        @refresh = 0
+        @acia_irq = false
+        @acia_due = Chips::ACIA::NEVER
+        @init_handlers = []
+        @pending_keys = nil
+        @init_keys = nil
+        @dos = nil
+        @ieee_trap = nil
+        @capture_output = nil
+        init_ieee_drives(true_drive_model)
+        @init_threshold = INIT_THRESHOLD
+        update_video_bus
+      end
+
+      # The model, its RAM and its mains as the pause menu names them, such
+      # as "510, 128K RAM, 50 HZ".
+      def model_label = "#{@model.name}, #{@model.ram_kb}K RAM, #{@mains_hz} HZ"
+
+      def timing
+        region = @model.region
+        Timing.new(clock_hz: region.clock_hz, cycles_per_line: region.cycles_per_line,
+                   lines_per_frame: region.lines_per_frame, crop: region.crop, pixel_width: 1, dots: 1)
+      end
+
+      # The VIC and the mains ahead of the chips, then TPI1's inputs from
+      # the CIA and the ACIA, and the CPU last, halted while BA is low on a
+      # read.
+      def cycle!
+        handle_init if @cycles == @init_threshold
+        feed_keyboard if @pending_keys
+
+        vic = @vic
+        vic.cycle!
+        tick_mains
+        @cia.cycle!
+        sample_lightpen
+        @sid.cycle!
+        @acia.run!(@cycles) if @cycles >= @acia_due
+        tpi1 = @tpi1
+        tpi1.interrupt_line(2, !@cia.interrupted?)
+        tpi1.interrupt_line(4, !@acia_irq)
+        cpu = @cpu
+        cpu.irq = tpi1.irq? || vic.interrupted?
+        cpu.pending_write? || !vic.ba_low? ? cpu.cycle! : cpu.stall!
+        clock_ieee_drives
+
+        @cycles += 1
+      end
+
+      # The ACIA's IRQ line, and the cycle it next has something to do at.
+      def acia_changed(irq, due)
+        @acia_irq = irq
+        @acia_due = due
+      end
+
+      # STATVID and VICDOTSEL from TPI1's CA and CB, PC6 and PC7 in mode 0,
+      # and VA14 and VA15 from TPI2's PC6 and PC7, to the VIC's bank.
+      def update_video_bus
+        lines = @tpi1.port_c_output
+        @vic.vic_bank.video_bus_lines(lines.anybits?(0x40), lines.anybits?(0x80), @tpi2.port_c_output >> 6)
+      end
+
+      # The RES line reaches the CPU and its segment registers, the SID, the
+      # CIA, the ACIA and both TPIs. The VIC has no reset pin.
+      def reset!
+        @sid.reset!
+        @cia.reset!
+        @acia.reset!
+        @tpi1.reset!
+        @tpi2.reset!
+        update_video_bus
+        @bus.reset!
+        @cpu.reset!
+        reset_ieee_drives
+      end
+
+      # Puts a program file's bytes where its first two say in BASIC's text
+      # segment, segment 0, and returns that address.
+      def load_prg(data)
+        load_addr = data[0] | (data[1] << 8)
+        bytes = data[2..] || []
+        bytes = bytes[0, 0x10000 - load_addr] if load_addr + bytes.length > 0x10000
+        bytes.each_with_index { |byte, i| @bus.poke_bank(TEXT_SEGMENT, load_addr + i, byte) }
+        load_addr
+      end
+
+      # The IEEELayout of 901234-02.
+      def trap_layout = IEEELayout::LAYOUT
+
+      # Puts a cartridge's ROM chips in (Bus#attach_cartridge) and switches
+      # the machine off and on, for the KERNAL to find it as it starts.
+      def attach_cartridge(chips)
+        @bus.attach_cartridge(chips)
+        power_cycle!
+      end
+
+      # Switches the machine off and on: RAM starts cleared, the VIC starts
+      # over, and the RES line resets everything else.
+      def power_cycle!
+        @bus.power_on!
+        @color_ram.clear!
+        @vic.power_on!
+        reset!
+      end
+
+      # The cycle by which the KERNAL has tested segments 0 and 1 and BASIC
+      # printed READY, with a margin.
+      INIT_THRESHOLD = 8_600_000
+
+      private
+
+      # The character ROM at $C000 and the colour RAM at $D400 of segment
+      # 15, and what the VIC reads.
+      def map_video
+        character_rom = ROM.load("character.rom", 0xc000)
+        @bus.map_video(character_rom, 0xc0, 0x10)
+        @bus.map_video(ColorPages.new(@color_ram), 0xd4, 0x04, writable: true)
+        bank = @vic.vic_bank
+        bank.map_character_rom(character_rom, base: 0xc000)
+        bank.map_video_bus(@bus.segment_ram[0], @bus.screen, @color_ram, 0xd400)
+      end
+
+      def map_io
+        @bus.map_io(0xd8, VICPage.new(@vic))
+        @bus.map_io(0xda, SIDPage.new(@sid))
+        @bus.map_io(0xdc, @cia)
+        @bus.map_io(0xdd, @acia)
+        @bus.map_io(0xde, TPIPage.new(@tpi1, self))
+        @bus.map_io(0xdf, TPIPage.new(@tpi2, self))
+      end
+
+      # The VIC's light pen input, CIA PA6 as the CIA drives it and control
+      # port 1's fire line pulls it, whose falling edge latches the beam.
+      def sample_lightpen
+        high = @cia.port_a_lines.anybits?(0x40) && @control_ports.fire1_high?
+        return if high == @lightpen_high
+
+        @lightpen_high = high
+        @vic.lightpen_level(high)
+      end
+
+      # The mains, low for half its period and high for the other half, on
+      # TPI1's I0, whose falling edge latches the tick.
+      def tick_mains
+        @mains_countdown -= 1
+        return unless @mains_countdown.zero?
+
+        @mains_countdown = @mains_half_period
+        @mains_high = !@mains_high
+        @tpi1.interrupt_line(0, @mains_high)
+      end
+    end
+  end
+end

data/lib/badline/cbm2/sid_page.rb

@@ -0,0 +1,19 @@
+# frozen_string_literal: true
+
+module Badline
+  class CBM2
+    # Page $DA of segment 15: the SID's 32 registers, repeated over the
+    # page.
+    class SIDPage
+      def initialize(sid)
+        @sid = sid
+      end
+
+      def peek(addr) = @sid.peek(0xda00 | (addr & 0x1f))
+
+      def poke(addr, value)
+        @sid.poke(0xda00 | (addr & 0x1f), value)
+      end
+    end
+  end
+end