badline 0.16.1 → 0.18.0

data/lib/badline/drives/model9060/parts.rb

@@ -0,0 +1,98 @@
+# frozen_string_literal: true
+
+module Badline
+  module Drives
+    class Model9060
+      # The SASI host's VIA, at $0080, a class of its own so it keeps one
+      # type of peripheral.
+      class SASIVIA < Chips::VIA
+      end
+
+      # The SASI host's 6502, on the SASIBus.
+      class SASICPU
+        include Badline::Chips::CPU::Core
+        include Engine::IdleCPU
+      end
+
+      # The VIA's lines to the controller (SASITarget), on the board's
+      # transceivers:
+      #
+      #   PA0-7  the data bus             PB0  SEL out
+      #   CA1    REQ, rising as it rises  PB1  RST out
+      #   CA2    ACK, pulsed on each      PB2  C/D in
+      #          read or write of ORA     PB3  BSY in
+      #   CB2    the transceivers'        PB4  jumper J14: high for four
+      #          direction                     heads (D9060), low for six
+      #                                   PB6  I/O in
+      #                                   PB7  MSG in
+      #
+      # The ports read and drive each line high while it is asserted, SEL
+      # and RST only while PB0 and PB1 are outputs.
+      # SEL raised selects the controller with the data bus as the host
+      # drives it, and RST raised resets it. ACK falling hands it the byte
+      # on the data bus.
+      class SASILines
+        SEL = 0x01
+        RST = 0x02
+        CD = 0x04
+        BSY = 0x08
+        J14 = 0x10
+        IO = 0x40
+        MSG = 0x80
+
+        attr_reader :target
+        attr_writer :via
+
+        # `four_heads` is J14.
+        def initialize(target, four_heads:)
+          @target = target
+          @four_heads = four_heads
+          @via = nil
+          @ack_high = true
+          @reset_high = false
+        end
+
+        # The data bus: the controller's byte while it drives it.
+        def read_a(_lines)
+          target = @target
+          target.input? ? target.data : 0xff
+        end
+
+        def read_b(_lines)
+          target = @target
+          value = 0x23
+          value |= CD if target.control?
+          value |= BSY if target.busy?
+          value |= J14 if @four_heads
+          value |= IO if target.input?
+          value |= MSG if target.message?
+          value
+        end
+
+        # One cycle of the controller, then the host's ACK, RST and SEL to
+        # the controller, and REQ to CA1.
+        def cycle!
+          target = @target
+          via = @via
+          target.clock
+          ack_high = via.ca2_output
+          target.acknowledge(via.port_a_output) if @ack_high && !ack_high
+          @ack_high = ack_high
+          host = via.port_b_output & via.peek(0x82)
+          reset_high = host.anybits?(RST)
+          target.reset if reset_high && !@reset_high
+          @reset_high = reset_high
+          target.select(via.port_a_output) if host.anybits?(SEL)
+          via.ca1 = target.request?
+        end
+
+        # Everything the lines hold between cycles.
+        def state = [@ack_high, @reset_high]
+
+        def state=(values)
+          @ack_high, @reset_high = values
+        end
+      end
+    end
+  end
+end

data/lib/badline/drives/model9060/sasi_bus.rb

@@ -0,0 +1,88 @@
+# frozen_string_literal: true
+
+module Badline
+  module Drives
+    class Model9060
+      # The SASI host processor's bus on the DOS board (300010), where the
+      # 8050's floppy controller sits, with its decode and common RAM:
+      #
+      # $0000-$007F - the 6810's 128 bytes, mirrored at $0100 for the stack
+      # $0080-$008F - the VIA (SASILines)
+      # $0400-$13FF - the common RAM, 1 KB in each of the 8050's windows
+      # $F800-$FFFF - 300515, the host's program
+      #
+      # Writes to the ROM and to open bus go nowhere, and a read from open
+      # bus finds the last byte on the data bus.
+      class SASIBus
+        include Addressable
+
+        attr_reader :common, :ram, :via
+        attr_accessor :data
+
+        # How many writes have changed a byte of the common RAM
+        # (Model9060::Idle).
+        attr_reader :common_changes
+
+        # Whether a counter or an interrupt flag has been read since it was
+        # last cleared (Model9060::Idle).
+        attr_accessor :volatile
+
+        def initialize(rom:, common:, via:)
+          addressable_at(0, length: 2**16)
+          @rom = rom
+          @common = common
+          @via = via
+          @ram = Memory.new([], length: 0x80)
+          @data = 0
+          @volatile = false
+          @common_changes = 0
+        end
+
+        def peek(addr)
+          @data = if addr >= 0xf800
+                    @rom.peek(addr & 0x07ff)
+                  elsif addr < 0x0200
+                    peek_low(addr)
+                  elsif addr.between?(0x0400, 0x13ff)
+                    @common.peek(addr - 0x0400)
+                  else
+                    @data
+                  end
+        end
+
+        def poke(addr, value)
+          @data = value
+          if addr < 0x0200
+            poke_low(addr, value)
+          elsif addr.between?(0x0400, 0x13ff)
+            poke_common(addr - 0x0400, value)
+          end
+        end
+
+        private
+
+        def peek_low(addr)
+          return @ram.peek(addr & 0x7f) if addr.nobits?(0x80)
+          return @data if addr.anybits?(0x70)
+
+          register = addr & 0x0f
+          @volatile = true if register.between?(0x04, 0x0a) || register == 0x0d
+          @via.peek(0x80 | register)
+        end
+
+        def poke_low(addr, value)
+          if addr.nobits?(0x80)
+            @ram.poke(addr & 0x7f, value)
+          elsif addr.nobits?(0x70)
+            @via.poke(0x80 | (addr & 0x0f), value)
+          end
+        end
+
+        def poke_common(index, value)
+          @common_changes += 1 if @common.peek(index) != value
+          @common.poke(index, value)
+        end
+      end
+    end
+  end
+end

data/lib/badline/drives/model9060/sasi_commands.rb

@@ -0,0 +1,168 @@
+# frozen_string_literal: true
+
+module Badline
+  module Drives
+    class Model9060
+      # The commands the DOS board's SASI ROM (300515) sends, against the
+      # disk's blocks. A command's second to fourth bytes hold the drive
+      # (bits 5-7) and the block's LBA, its fifth the blocks to move.
+      #
+      # | Op | Command | Data |
+      # | --- | --- | --- |
+      # | $00 | Test Unit Ready | |
+      # | $01 | Recalibrate: seek to cylinder 0 | |
+      # | $03 | Request Sense: the last command's error and its LBA | 4 in |
+      # | $04 | Format Unit | |
+      # | $08 | Read | 256 a block in |
+      # | $0A | Write | 256 a block out |
+      # | $0B | Seek | |
+      # | $0C | Vendor: read the controller's block buffer (unverified) | 256 in |
+      # | $0E | Vendor: write the controller's block buffer (unverified) | 256 out |
+      # | $E3 | Vendor: four zero bytes from a drive that is there (unverified) | 4 in |
+      # | $C0 | Vendor: set the geometry (unverified) | |
+      #
+      # DOS 3.0 sends $E3 before it first reads a drive, and leaves a drive
+      # alone that fails it as DRIVE NOT READY, as drive 1 does here.
+      #
+      # $C0's fifth and sixth bytes are taken as the last head and the last
+      # sector of a head, as the ROM sends them (5 and 31 on a D9090 at
+      # boot). Its other bytes aren't used.
+      #
+      # An error's sense byte has its class in bits 4-5 and its code in bits
+      # 0-3, with bit 7 set when the LBA after it names the block. The ROM
+      # reads that byte from the message phase after a check condition,
+      # and the controller sends it there.
+      #
+      # Format Unit erases the disk at once and puts the controller in a
+      # fast mode, where Read, Write and Seek take no seek or rotation time,
+      # for the DOS's passes over the whole disk. Any other command ends
+      # it. Outside it a seek takes 3 ms a cylinder and 15 ms to settle, and
+      # the disk turns 32 blocks in 16.7 ms.
+      module SASICommands
+        DRIVE_NOT_READY = 0x04
+        WRITE_FAULT = 0x03
+        INVALID_COMMAND = 0x20
+        ILLEGAL_ADDRESS = 0xa1
+
+        BLOCK = 256
+        SECTOR_CYCLES = 521
+        STEP_CYCLES = 3_000
+        SETTLE_CYCLES = 15_000
+
+        DISK_COMMANDS = [0x00, 0x01, 0x04, 0x08, 0x0a, 0x0b, 0xe3].freeze
+        FAST_COMMANDS = [0x08, 0x0a, 0x0b].freeze
+
+        attr_reader :heads, :sectors, :cylinder
+
+        def fast? = @fast
+
+        private
+
+        def reset_geometry
+          @heads = 4
+          @sectors = 32
+          @block_buffer = Array.new(BLOCK, 0)
+        end
+
+        def execute
+          @fast = false unless FAST_COMMANDS.include?(@command[0])
+          case @command[0]
+          when 0x03 then enter(SASITarget::DATA_IN, @last_sense.dup, 1)
+          when 0x0c then enter(SASITarget::DATA_IN, @block_buffer.dup, 1)
+          when 0x0e then enter(SASITarget::DATA_OUT, Array.new(BLOCK, 0), 1)
+          when 0xc0 then set_geometry
+          else disk_command
+          end
+        end
+
+        def disk_command
+          return refuse(INVALID_COMMAND) unless DISK_COMMANDS.include?(@command[0])
+          return refuse(DRIVE_NOT_READY) unless @disk && (@command[1] >> 5).zero?
+
+          case @command[0]
+          when 0x00 then report
+          when 0x01 then report(travel(0))
+          when 0x04 then format_unit
+          when 0xe3 then enter(SASITarget::DATA_IN, [0, 0, 0, 0], 1)
+          else block_command
+          end
+        end
+
+        def block_command
+          return refuse(ILLEGAL_ADDRESS) unless @disk.blocks?(lba, @command[0] == 0x0b ? 1 : count)
+
+          case @command[0]
+          when 0x08 then read
+          when 0x0a then enter(SASITarget::DATA_OUT, Array.new(count * BLOCK, 0), 1)
+          else report(travel(cylinder_of(lba)))
+          end
+        end
+
+        def lba = ((@command[1] & 0x1f) << 16) | (@command[2] << 8) | @command[3]
+
+        def count = @command[4].zero? ? 256 : @command[4]
+
+        def cylinder_of(block) = block / (@heads * @sectors)
+
+        def set_geometry
+          @heads = @command[4] + 1
+          @sectors = @command[5] + 1
+          report
+        end
+
+        def read
+          bytes = @disk.read_blocks(lba, count)
+          @block_buffer = bytes.last(BLOCK)
+          enter(SASITarget::DATA_IN, bytes, access_cycles)
+        end
+
+        def data_received
+          if @command[0] == 0x0e
+            @block_buffer = @buffer.dup
+            report
+          else
+            @writing = true
+            @delay = access_cycles
+          end
+        end
+
+        def store_buffer
+          @disk.write_blocks(lba, @buffer)
+          @block_buffer = @buffer.last(BLOCK)
+          report
+        rescue Storage::WriteError
+          refuse(WRITE_FAULT)
+        end
+
+        def format_unit
+          blocks = @heads * @sectors
+          (0...@disk.block_count).step(blocks) do |first|
+            @disk.write_blocks(first, Array.new([blocks, @disk.block_count - first].min * BLOCK, 0))
+          end
+          @fast = true
+          report
+        rescue Storage::WriteError
+          refuse(WRITE_FAULT)
+        end
+
+        # The seek to the block's cylinder, the turn until the block comes
+        # under the head, and the blocks passing under it.
+        def access_cycles
+          return 1 if @fast
+
+          seek = travel(cylinder_of(lba))
+          slot = ((@cycle + seek) / SECTOR_CYCLES) % @sectors
+          seek + ((((lba % @sectors) - slot) % @sectors) * SECTOR_CYCLES) + (count * SECTOR_CYCLES)
+        end
+
+        def travel(target)
+          steps = (target - @cylinder).abs
+          @cylinder = target
+          return 1 if @fast || steps.zero?
+
+          (steps * STEP_CYCLES) + SETTLE_CYCLES
+        end
+      end
+    end
+  end
+end

data/lib/badline/drives/model9060/sasi_target.rb

@@ -0,0 +1,161 @@
+# frozen_string_literal: true
+
+require "badline/drives/model9060/sasi_commands"
+
+module Badline
+  module Drives
+    class Model9060
+      # The D9060's and D9090's hard disk controller (Tandon 188008) as the
+      # DOS board's SASI host sees it, at the level of the bus's lines.
+      #
+      # The host selects it by raising SEL with bit 0 on the data bus, and
+      # it answers with BSY. It then runs one command through the bus's
+      # phases, which C/D, I/O and MSG name: six command bytes from the
+      # host, the data in or out, a status byte and a message byte, after
+      # which it lets go of BSY. Each byte waits on REQ, which the host
+      # answers with ACK, and REQ rises again a cycle later for the next.
+      #
+      # The controller's work between the phases (a seek, the turn to the
+      # block, the block under the head) delays the next REQ. `clock`
+      # counts that time out, one cycle of the DOS board's 1 MHz at a time,
+      # and `quiet?` says when there is none left to count. SASICommands
+      # runs the commands against the disk, a Storage::D90Image, or nil
+      # with none inserted.
+      class SASITarget
+        include SASICommands
+
+        BUS_FREE = 0
+        COMMAND = 1
+        DATA_IN = 2
+        DATA_OUT = 3
+        STATUS = 4
+        MESSAGE = 5
+
+        COMMAND_LENGTH = 6
+
+        attr_accessor :disk
+        attr_reader :phase
+
+        def initialize(disk = nil)
+          @disk = disk
+          @cycle = 0
+          @cylinder = 0
+          reset_geometry
+          reset
+        end
+
+        # RST: the controller drops whatever it was doing and frees the bus.
+        def reset
+          @phase = BUS_FREE
+          @request = false
+          @delay = 0
+          @command = []
+          @buffer = []
+          @index = 0
+          @writing = false
+          @sense = [0, 0, 0, 0]
+          @last_sense = @sense
+          @fast = false
+        end
+
+        def busy? = @phase != BUS_FREE
+
+        def request? = @request
+
+        # C/D: a command, status or message byte rather than data.
+        def control? = [COMMAND, STATUS, MESSAGE].include?(@phase)
+
+        # I/O: a byte from the controller to the host.
+        def input? = [DATA_IN, STATUS, MESSAGE].include?(@phase)
+
+        def message? = @phase == MESSAGE
+
+        def quiet? = @delay.zero?
+
+        # The byte the controller puts on the data bus, while I/O is set.
+        def data = input? ? @buffer[@index] || 0 : 0
+
+        # SEL with the host's data bus. The controller answers to bit 0
+        # while the bus is free.
+        def select(bus)
+          return if busy? || bus.nobits?(0x01)
+
+          enter(COMMAND, Array.new(COMMAND_LENGTH, 0), 1)
+        end
+
+        # ACK for the byte REQ asked for. The host's data bus carries a
+        # byte to the controller in the command and data out phases, and
+        # is ignored in the others.
+        def acknowledge(bus)
+          return unless @request
+
+          @request = false
+          @buffer[@index] = bus if @phase == COMMAND || @phase == DATA_OUT
+          @index += 1
+          @index < @buffer.length ? @delay = 1 : finish_phase
+        end
+
+        # Runs the clock on through cycles the controller has nothing to
+        # count down in.
+        def fast_forward(cycles)
+          @cycle += cycles
+        end
+
+        def clock
+          @cycle += 1
+          return if @delay.zero?
+
+          @delay -= 1
+          arrive if @delay.zero?
+        end
+
+        private
+
+        def enter(phase, bytes, delay)
+          @phase = phase
+          @buffer = bytes
+          @index = 0
+          @request = false
+          @delay = [delay, 1].max
+        end
+
+        def arrive
+          if @writing
+            @writing = false
+            store_buffer
+          else
+            @request = true
+          end
+        end
+
+        def finish_phase
+          case @phase
+          when COMMAND then start(@buffer.dup)
+          when DATA_IN then report
+          when DATA_OUT then data_received
+          when STATUS then enter(MESSAGE, [@sense[0]], 1)
+          else @phase = BUS_FREE
+          end
+        end
+
+        def start(command)
+          @command = command
+          @last_sense = @sense
+          @sense = [0, 0, 0, 0]
+          execute
+        end
+
+        # The status byte: 0 for a command that went well, $02 (check
+        # condition) for one that failed, whose error Request Sense reads.
+        def report(delay = 1)
+          enter(STATUS, [@sense[0].positive? ? 0x02 : 0x00], delay)
+        end
+
+        def refuse(error)
+          @sense = [error, (@command[1] & 0xe0) | ((lba >> 16) & 0x1f), (lba >> 8) & 0xff, lba & 0xff]
+          report
+        end
+      end
+    end
+  end
+end

data/lib/badline/drives/model9060.rb

@@ -0,0 +1,195 @@
+# frozen_string_literal: true
+
+require "badline/drives/model8050"
+require "badline/drives/model9060/sasi_target"
+require "badline/drives/model9060/sasi_bus"
+require "badline/drives/model9060/parts"
+require "badline/drives/model9060/idle"
+require "badline/drives/model9060/keyed_state"
+
+module Badline
+  module Drives
+    # The D9060 hard disk of the PET and CBM-II, one 5 MB drive on an
+    # IEEE-488 unit (technical manual PN 990441; DOS board 300010).
+    #
+    # The DOS board is the 8050's with the floppy half given over to a SASI
+    # host. The interface processor (IP) runs DOS 3.0 from 16 KB of ROM at
+    # $C000, with the 8050's two 6532s on the IEEE-488 bus (Model8050's
+    # IPBus and IEEEPort). The SASI host, a second 6502 in the floppy
+    # controller's place, runs 300515 from 2 KB at $F800, with a 6810 for
+    # its zero page and stack and a VIA facing the hard disk's controller
+    # (SASIBus, SASILines, SASITarget). The two meet in the 8050's 4 KB of
+    # common RAM, where the IP leaves jobs and the host turns each into a
+    # SASI command.
+    #
+    # Reset starts both. The host waits on the common RAM for the IP, which
+    # tests it and answers, and the DOS settles into its idle loop with the
+    # host polling the job queue.
+    #
+    # The interface processor's side of the board and the clocking against
+    # the host are the 8050's (Model8050::DOSBoard), and the unit sleeps
+    # through both processors' idle loops (Idle).
+    #
+    # N runs as the DOS runs it, but for the six passes that write and
+    # read back test patterns over every block, an hour of the hardware's
+    # time: once Format Unit has erased the disk, the IP goes from the first
+    # pass straight on to where they end, as if every block had passed.
+    # The DOS then writes the bad-block list, the BAM, the header and the
+    # directory as c1541 formats a .d90, byte for byte.
+    class Model9060
+      include Model8050::DOSBoard
+      include Idle
+
+      CLOCK_HZ = 1_000_000
+
+      # The host cycles by which a unit switched on with the machine has
+      # run its RAM tests and the host's start-up, and reads its jumpers.
+      BOOT_CYCLES = 1_500_000
+
+      # DOS 3.0's format: the first of its pattern passes (FORMAT_PASSES),
+      # where the pass number ($2D) is 0, and the code after the last
+      # (FORMAT_DONE), with the pass number at 6.
+      FORMAT_PASSES = 0xcb02
+      FORMAT_DONE = 0xcc15
+      PASS = 0x2d
+
+      def sasi_cpu = settled(@sasi_cpu)
+
+      def sasi_bus = settled(@sasi_bus)
+
+      def target = settled(@target)
+
+      def model_name = "9060"
+
+      # The heads the drive has, which J14 tells the DOS.
+      def heads = 4
+
+      def boot_cycles = BOOT_CYCLES
+
+      # Whether the unit is where VICE saves it: both processors between
+      # instructions, the host at the start of its job loop.
+      def settled_for_vice?
+        host = sasi_cpu
+        ip_cpu.boundary? && host.boundary? && host.program_counter == Idle::SASI_LOOP
+      end
+
+      # +dos_rom+ covers $C000-$FFFF and +sasi_rom+ $F800-$FFFF of the
+      # host's, each defaulting to the image in the ROM path. +device+ is
+      # the number the jumpers set, 8 to 15. Only the default DOS has its
+      # pattern passes skipped.
+      def initialize(dos_rom: nil, sasi_rom: nil, host_clock_hz: CLOCK_HZ, device: 8)
+        @device = device
+        @host_clock_hz = host_clock_hz
+        @phase = 0
+        @cycles = 0
+        @format_trap = dos_rom.nil?
+        build_ip(dos_rom || ROM.load("9060/dos-3.0.rom", 0xc000))
+        build_sasi(sasi_rom || ROM.read("9060/sasi-300515-revb.rom"))
+        @ip_cpu = Model8050::IPCPU.new(@ip_bus)
+        @sasi_cpu = SASICPU.new(@sasi_bus)
+        init_idle
+        @ieee_bus.attach(self)
+      end
+
+      # Whether the activity LED is lit: of the LEDs, bit 1 is the
+      # activity LED and bit 2 the status LED.
+      def led_on? = leds.anybits?(0x02)
+
+      # Puts the Storage::D90Image in the drive. Nil takes it out.
+      def insert(image)
+        settle!
+        @target.disk = image
+      end
+
+      # Puts in the .d90 image at +path+, write-protected with `read_only`.
+      # An image of neither drive's size takes this drive's heads.
+      def insert_image(path, read_only: false)
+        image_heads = Storage::D90Image.heads_for(File.size(path)) || heads
+        insert(Storage::D90Image.new(path, read_only:, heads: image_heads))
+      end
+
+      # The image in the drive, or nil.
+      def disk = @target.disk
+
+      # Writes reach the image as each Write ends, so there is nothing to
+      # store.
+      def flush = nil
+
+      # The bus's IFC line resets both processors and every chip. RAM keeps
+      # its contents, and the hard disk's controller runs on.
+      def reset!
+        settle!
+        @data_riot.reset!
+        @control_riot.reset!
+        @via.reset!
+        @ip_cpu.reset!
+        @sasi_cpu.reset!
+      end
+
+      def inspect
+        "#<#{self.class.name} cycles=#{@cycles} ip=(#{@ip_cpu.inspect}) sasi=(#{@sasi_cpu.inspect})>"
+      end
+
+      private
+
+      def run_cycle
+        step
+        skip_format_passes if @format_trap && @target.fast?
+        watch_loops if @idle_skip
+      end
+
+      def build_ip(rom)
+        @common = Memory.new([], length: 0x1000)
+        @ieee_bus = IEEEBus.new
+        @ieee_port = Model8050::IEEEPort.new(device: @device, bus: @ieee_bus)
+        @data_riot = Model8050::DataRIOT.new(peripheral: Model8050::DataLines.new(@ieee_port))
+        @control_riot = Model8050::ControlRIOT.new(peripheral: Model8050::ControlLines.new(@ieee_port))
+        @ieee_port.data_riot = @data_riot
+        @ieee_port.control_riot = @control_riot
+        @ip_bus = Model8050::IPBus.new(rom:, common: @common, data_riot: @data_riot, control_riot: @control_riot)
+      end
+
+      def build_sasi(rom)
+        @target = SASITarget.new
+        @lines = SASILines.new(@target, four_heads: heads == 4)
+        @via = SASIVIA.new(start: 0x0080, peripheral: @lines)
+        @lines.via = @via
+        @sasi_bus = SASIBus.new(rom: ROM.new(rom, length: rom.length), common: @common, via: @via)
+      end
+
+      # One cycle of the board: the controller and the chips, then the IP
+      # and the host, each in its own half of the cycle. ATN reaches UE1's
+      # PA7 as the port latched it. UE1 pulls the IP's IRQ and the VIA the
+      # host's.
+      def step
+        @control_riot.pa7 = @ieee_port.atn_low?
+        @data_riot.cycle!
+        @control_riot.cycle!
+        @via.cycle!
+        @lines.cycle!
+        @ip_cpu.irq = @control_riot.irq?
+        @ip_cpu.cycle!
+        @sasi_cpu.irq = @via.irq?
+        @sasi_cpu.cycle!
+        @cycles += 1
+      end
+
+      # Sends the IP from the first pattern pass on to the end of the last.
+      def skip_format_passes
+        ip = @ip_cpu
+        return unless ip.program_counter == FORMAT_PASSES && ip.boundary? && @ip_bus.peek(PASS).zero?
+
+        @ip_bus.poke(PASS, 6)
+        ip.program_counter = FORMAT_DONE
+      end
+    end
+
+    # The D9090: the D9060's board on a six-head drive, 7.5 MB, with J14
+    # telling the DOS so.
+    class Model9090 < Model9060
+      def model_name = "9090"
+
+      def heads = 6
+    end
+  end
+end