badline 0.16.1 → 0.18.0

data/lib/badline/drives/model4040.rb

@@ -0,0 +1,179 @@
+# frozen_string_literal: true
+
+require "badline/drives/model8050"
+require "badline/drives/model4040/ip_bus"
+require "badline/drives/model4040/parts"
+require "badline/drives/model4040/disk"
+require "badline/drives/model4040/mechanism"
+require "badline/drives/model4040/keyed_state"
+
+module Badline
+  module Drives
+    # The 4040 dual disk drive of the PET and CBM-II, two Shugart SA390
+    # drives on one IEEE-488 unit (schematic 320806, the 8050's parent).
+    #
+    # The board is the 8050's (Model8050::Board) with an older floppy side.
+    # A 16 MHz crystal clocks both processors at 1 MHz on opposite phases.
+    # The interface processor runs DOS 2.1 from 12 KB of ROM at $D000, with
+    # the 8050's 6532s on the bus and the same common RAM, on a bus that
+    # doesn't decode A15 (IPBus). The floppy controller is a 6504, with no
+    # SO pin, on the 8050's map (Model8050::FDCBus): it runs the program in
+    # its 6530 (901466-04) and polls the VIA for byte ready, whose own
+    # interrupt line goes nowhere, so only the 6530's timer interrupts it
+    # (Mechanism). The disks are the 1541's, 35 tracks of 17 to 21
+    # sectors, a .d64 each (Disk).
+    #
+    # At reset the controller waits for the common RAM's $0400 to read 0,
+    # starts, and writes its timer's period there. The interface processor
+    # tests its RAM and ROMs, has the controller reset its drives, and
+    # bumps both heads to track 1.
+    class Model4040
+      include Model8050::Board
+      include Model8050::Idle
+      include Model8050::KeyedState
+
+      CLOCK_HZ = Model8050::CLOCK_HZ
+
+      # The host cycles by which a unit switched on with the machine has
+      # run the IP's tests and bumped both heads, and reads its jumpers.
+      BOOT_CYCLES = 2_500_000
+
+      # Where DOS 2.1's idle loop and the controller's job loop start over
+      # (Model8050::Idle).
+      IP_LOOP = 0xd4b7
+      FDC_LOOP = 0xfc54
+
+      def model_name = "4040"
+
+      def boot_cycles = BOOT_CYCLES
+
+      def sides = 1
+
+      # +dos_rom+ covers $D000-$FFFF and +fdc_rom+ is the 6530's mask, each
+      # defaulting to the image in the ROM path: the revised DOS 2.1 that
+      # xpet's 4040 runs, and 901466-04. +device+ is the number the jumpers
+      # set, 8 to 15.
+      def initialize(dos_rom: nil, fdc_rom: nil, host_clock_hz: CLOCK_HZ, device: 8)
+        @device = device
+        @host_clock_hz = host_clock_hz
+        @phase = 0
+        @cycles = 0
+        build_ip(dos_rom || ROM.load(dos_file, dos_start))
+        build_fdc(fdc_rom || ROM.read(fdc_file))
+        @ip_cpu = IPCPU.new(@ip_bus)
+        @fdc_cpu = FDCCPU.new(@fdc_bus)
+        init_idle(ip_loop, fdc_loop)
+        @ieee_bus.attach(self)
+      end
+
+      # Puts in the .d64 image at +path+, or the DOS 1 disk a .d67 holds,
+      # write-protected with `read_only`.
+      def insert_image(path, drive: 0, read_only: false)
+        image = if File.extname(path).casecmp?(".d67")
+                  Storage::D67Image.new(path, read_only:)
+                else
+                  Storage::D64Image.new(path, read_only:)
+                end
+        insert(Disk.new(image), drive:)
+      end
+
+      private
+
+      def dos_file = "4040/dos-2.1-rev.rom"
+
+      def dos_start = 0xd000
+
+      def fdc_file = "4040/fdc-901466-04.rom"
+
+      def ip_loop = IP_LOOP
+
+      def fdc_loop = FDC_LOOP
+
+      def build_ip(rom)
+        @common = Memory.new([], length: 0x1000)
+        @ieee_bus = IEEEBus.new
+        @ieee_port = Model8050::IEEEPort.new(device: @device, bus: @ieee_bus)
+        @data_riot = Model8050::DataRIOT.new(peripheral: Model8050::DataLines.new(@ieee_port))
+        @control_riot = Model8050::ControlRIOT.new(peripheral: Model8050::ControlLines.new(@ieee_port))
+        @ieee_port.data_riot = @data_riot
+        @ieee_port.control_riot = @control_riot
+        @ip_bus = IPBus.new(rom:, common: @common, data_riot: @data_riot, control_riot: @control_riot)
+      end
+
+      def build_fdc(rom)
+        @mechanism = Mechanism.new
+        @via = Model8050::ControllerVIA.new(start: 0x0040, peripheral: ReadLines.new(@mechanism))
+        @rriot = Model8050::ControllerRRIOT.new(rom:, peripheral: StatusLines.new(@mechanism))
+        @fdc_bus = Model8050::FDCBus.new(common: @common, via: @via, rriot: @rriot)
+        @mechanism.via = @via
+        @mechanism.rriot = @rriot
+      end
+
+      # The disk a BL-D8-DISK module holds (Model8050::KeyedState).
+      def disk_from_fields(input, detached) = Disk.from_fields(input, detached:)
+
+      # One cycle of the board: the drives, then the chips, then the IP and
+      # the FDC, each in its own half of the cycle, as on the 8050. Only the
+      # 6530 pulls the FDC's IRQ, and the FDC finds byte ready by polling.
+      def step
+        @mechanism.cycle!
+        @control_riot.pa7 = @ieee_port.atn_low?
+        @data_riot.cycle!
+        @control_riot.cycle!
+        @via.cycle!
+        @rriot.cycle!
+        @ip_cpu.irq = @control_riot.irq?
+        @ip_cpu.cycle!
+        @fdc_cpu.irq = @rriot.irq?
+        @fdc_cpu.cycle!
+        @cycles += 1
+      end
+    end
+
+    # The 3040: the 4040's board with the first DOS 2.1, as xpet's 3040
+    # runs it, 901468-11 to -13.
+    class Model3040 < Model4040
+      # Where the first DOS 2.1's idle loop starts over.
+      IP_LOOP = 0xd4b8
+
+      def model_name = "3040"
+
+      private
+
+      def dos_file = "4040/dos-2.1.rom"
+
+      def ip_loop = IP_LOOP
+    end
+
+    # The 2040: the 4040's board with DOS 1.2 in the sockets at $E000 and
+    # $F000, UJ1 at $D000 left empty, and 901466-02 in the controller's
+    # 6530, as the 3040 with DOS 1 has it too. Its disks are DOS 1's .d67,
+    # with 20 sectors on tracks 18 to 24 (Storage::D67Image). The
+    # controller starts at once, with no handshake on the common RAM, and
+    # the interface processor leaves the common RAM alone at boot.
+    class Model2040 < Model4040
+      # Where DOS 1.2's idle loop and its controller's job loop start over.
+      IP_LOOP = 0xe27e
+      FDC_LOOP = 0xfc47
+
+      def model_name = "2040"
+
+      # Puts in the .d67 image at +path+, write-protected with `read_only`.
+      def insert_image(path, drive: 0, read_only: false)
+        insert(Disk.new(Storage::D67Image.new(path, read_only:)), drive:)
+      end
+
+      private
+
+      def dos_file = "4040/dos-1.2.rom"
+
+      def dos_start = 0xe000
+
+      def fdc_file = "4040/fdc-901466-02.rom"
+
+      def ip_loop = IP_LOOP
+
+      def fdc_loop = FDC_LOOP
+    end
+  end
+end

data/lib/badline/drives/model8050/board.rb

@@ -0,0 +1,77 @@
+# frozen_string_literal: true
+
+module Badline
+  module Drives
+    class Model8050
+      # The board of a unit with two processors on the IEEE-488 bus, as the
+      # 8050 family and the 4040 family share it: the DOS board's interface
+      # processor side (DOSBoard), and the floppy controller with its VIA
+      # and 6530 facing the drives. Each unit's class includes it, with
+      # Idle and KeyedState, and builds its own chips, so no call it makes
+      # on them is a union: the class sets DOSBoard's fields and @fdc_cpu,
+      # @fdc_bus, @rriot and @mechanism, and runs one cycle of the board in
+      # its own step. While both processors idle, it sleeps (Idle).
+      module Board
+        include DOSBoard
+
+        def fdc_cpu = settled(@fdc_cpu)
+
+        def fdc_bus = settled(@fdc_bus)
+
+        def rriot = settled(@rriot)
+
+        def mechanism = settled(@mechanism)
+
+        # Whether the unit is where VICE saves it: both processors between
+        # instructions, the FDC at the start of its idle loop.
+        def settled_for_vice?
+          fdc = fdc_cpu
+          ip_cpu.boundary? && fdc.boundary? && fdc.program_counter == @fdc_loop
+        end
+
+        # Whether a drive's LED is lit: of the LEDs, bit 0 is drive 1's,
+        # bit 1 drive 0's, and bit 2 the error LED.
+        def led_on? = leds.anybits?(0x03)
+
+        # Puts a Disk in +drive+, 0 or 1. Nil takes the disk out.
+        def insert(disk, drive: 0)
+          settle!
+          @mechanism.insert(disk, drive)
+        end
+
+        # The Disk in +drive+, or nil.
+        def disk(drive = 0) = @mechanism.disk(drive)
+
+        # Stores what the heads wrote in the disks' images, as the motors
+        # stopping do.
+        def flush
+          settle!
+          @mechanism.flush
+        end
+
+        # The bus's IFC line resets both processors and every chip. RAM keeps
+        # its contents.
+        def reset!
+          settle!
+          @data_riot.reset!
+          @control_riot.reset!
+          @via.reset!
+          @rriot.reset!
+          @ip_cpu.reset!
+          @fdc_cpu.reset!
+        end
+
+        def inspect
+          "#<#{self.class.name} cycles=#{@cycles} ip=(#{@ip_cpu.inspect}) fdc=(#{@fdc_cpu.inspect})>"
+        end
+
+        private
+
+        def run_cycle
+          step
+          watch_loops if @idle_skip
+        end
+      end
+    end
+  end
+end

data/lib/badline/drives/model8050/disk.rb

@@ -0,0 +1,163 @@
+# frozen_string_literal: true
+
+module Badline
+  module Drives
+    class Model8050
+      # A .d80 or .d82 image as the floppy controller finds it on the disk:
+      # each track a ring of byte cells, each cell ten bit cells the GCR ROM
+      # turns into a data byte (Track::SYNC for a run of ones), so the
+      # mechanism needs no GCR. A track is laid out as the DOS's format code
+      # writes it ($C000-$C363 of DOS 2.7, run on the controller), sector
+      # after sector:
+      #
+      #   4 sync, $08, checksum, sector, track, ID 2, ID 1, $0F,
+      #   19 x $0F, 5 sync, $07, 256 data bytes, checksum, then $00
+      #
+      # the header checksum the EOR of the track, sector and IDs, and the
+      # data block's that of its bytes. The $00 gaps share out what the
+      # track has left over.
+      #
+      # Tracks come off the image as the head first reaches them. What the
+      # head writes goes back to the image when the motor stops (flush):
+      # every data block found on a written track whose header and checksum
+      # read cleanly.
+      class Disk
+        SYNC = 0x100
+
+        attr_reader :image
+
+        def initialize(image)
+          @image = image
+          @tracks = {}
+          @written = {}
+        end
+
+        def write_protected? = @image.read_only?
+
+        # The image's host file.
+        def path = @image.path
+
+        # How many tracks a side holds: 77.
+        def side_tracks = Storage::D80Image::SIDE_TRACKS
+
+        def sides = @image.is_a?(Storage::D82Image) ? 2 : 1
+
+        # The cells of +track+, 1 to 77 on the first side and 78 to 154 on
+        # the second, or nil past the disk's last.
+        def track(number)
+          return nil unless number.between?(1, side_tracks * sides)
+
+          @tracks[number] ||= build(number)
+        end
+
+        # The cells a track of the zone holds in one turn at 300 rpm: the
+        # 200,000 cycles of a turn over the zone's ten bit cells a byte at
+        # 6 MHz / (16 - zone).
+        def self.cells_in(zone) = 120_000 / (16 - zone)
+
+        # The zone a track is recorded in, 3 outermost to 0 innermost.
+        def self.zone_of(track)
+          cylinder = ((track - 1) % Storage::D80Image::SIDE_TRACKS) + 1
+          3 - Storage::D80Image::ZONE_LAST_TRACKS.count { |last| cylinder > last }
+        end
+
+        # The head wrote to +track+.
+        def written(number)
+          @written[number] = true
+        end
+
+        # Stores the blocks the head wrote in the image.
+        def flush
+          return if @written.empty?
+
+          blocks = []
+          @written.each_key { |number| blocks.concat(read_blocks(@tracks[number])) }
+          @written.clear
+          @image.store_blocks(blocks) unless blocks.empty?
+        end
+
+        private
+
+        def build(number)
+          id1, id2 = disk_id
+          cells = []
+          sectors = @image.sectors_in(number)
+          sectors.times do |sector|
+            data = @image.read_block(number, sector)
+            cells.push(SYNC, SYNC, SYNC, SYNC, 0x08, number ^ sector ^ id1 ^ id2, sector, number, id2, id1)
+            cells.concat(Array.new(20, 0x0f))
+            cells.push(SYNC, SYNC, SYNC, SYNC, SYNC, 0x07)
+            cells.concat(data)
+            cells << checksum(data)
+          end
+          pad(cells, sectors, self.class.cells_in(self.class.zone_of(number)))
+        end
+
+        # Shares the $00 gap out after each sector.
+        def pad(cells, sectors, length)
+          sector_length = cells.length / sectors
+          gap = (length - cells.length) / sectors
+          padded = []
+          sectors.times do |sector|
+            padded.concat(cells[sector * sector_length, sector_length])
+            padded.concat(Array.new(sector == sectors - 1 ? length - padded.length : gap, 0x00))
+          end
+          padded
+        end
+
+        def checksum(bytes)
+          sum = 0
+          bytes.each { |byte| sum ^= byte }
+          sum
+        end
+
+        # The ID the header block holds at $18.
+        def disk_id
+          header = @image.read_block(*@image.header_block)
+          [header[0x18], header[0x19]]
+        end
+
+        # Every block whose header and data read cleanly off +cells+, as
+        # [track, sector, data, nil].
+        def read_blocks(cells)
+          blocks = []
+          index = 0
+          length = cells.length
+          while (index = next_block(cells, index, 0x08))
+            header = Array.new(5) { |offset| cells[(index + offset) % length] }
+            index = next_block(cells, index, 0x07)
+            break unless index
+
+            block = data_block(cells, index, header)
+            blocks << block if block
+            break if index + 260 >= length
+          end
+          blocks
+        end
+
+        # The cell after the next sync run followed by +mark+, from
+        # +index+, or nil.
+        def next_block(cells, index, mark)
+          length = cells.length
+          while index < length
+            return index + 2 if cells[index] == SYNC && cells[(index + 1) % length] == mark
+
+            index += 1
+          end
+          nil
+        end
+
+        def data_block(cells, index, header)
+          checksum, sector, track, id2, id1 = header
+          return nil unless checksum == (track ^ sector ^ id1 ^ id2)
+
+          length = cells.length
+          data = Array.new(256) { |offset| cells[(index + offset) % length] }
+          return nil if data.include?(SYNC) || checksum(data) != cells[(index + 256) % length]
+
+          [track, sector, data, nil]
+        end
+      end
+    end
+  end
+end

data/lib/badline/drives/model8050/dos_board.rb

@@ -0,0 +1,91 @@
+# frozen_string_literal: true
+
+module Badline
+  module Drives
+    class Model8050
+      # The half of the DOS board every unit with an interface processor
+      # shares: the interface processor with its two 6532s on the IEEE-488
+      # bus, the common RAM, and the second processor's VIA, whichever side
+      # the second processor runs. Board adds the floppy controller's side
+      # to it, and Model9060 the SASI host's. Each unit's class sets
+      # @ip_cpu, @ip_bus, @common, @data_riot, @control_riot, @via,
+      # @ieee_bus and @ieee_port, and has its own run_cycle and settle!.
+      #
+      # The unit clocks against the host through a phase accumulator, as
+      # Drives::Engine::Core does: each host cycle adds 1 MHz of phase, and
+      # every whole host period in it runs a cycle of both processors. While
+      # both processors idle, it sleeps instead, and the readers of its
+      # parts catch it up first.
+      module DOSBoard
+        attr_reader :device, :ieee_bus
+
+        def ip_cpu = settled(@ip_cpu)
+
+        def ip_bus = settled(@ip_bus)
+
+        def common = settled(@common)
+
+        def data_riot = settled(@data_riot)
+
+        def control_riot = settled(@control_riot)
+
+        def via = settled(@via)
+
+        def cycles
+          settle!
+          @cycles
+        end
+
+        attr_writer :host_clock_hz
+
+        # Plugs the unit into an IEEE-488 bus, leaving the one it was on.
+        def connect(ieee_bus)
+          settle!
+          @ieee_bus.detach(self)
+          @ieee_bus = ieee_bus
+          @ieee_port.bus = ieee_bus
+          ieee_bus.attach(self)
+        end
+
+        # The lines the unit pulls on the bus while ATN is low or not
+        # (IEEEPort).
+        def ieee_low_lines(atn) = @ieee_port.ieee_low_lines(atn)
+
+        # The controller pushed its lines into the bus.
+        def host_written! = nil
+
+        # Which LEDs are lit, as the unit's port drives them. They hold
+        # still while the unit sleeps, so reading them leaves it asleep.
+        def leds = @ieee_port.leds
+
+        def power_led_on? = true
+
+        # Runs the drive cycles that fall in one host cycle, then takes the
+        # controller's lines for the next. Asleep, the unit owes the cycles
+        # instead, and wakes once the controller has moved a line.
+        def host_cycle!
+          phase = @phase + CLOCK_HZ
+          while phase >= @host_clock_hz
+            @asleep ? owe_cycle : run_cycle
+            phase -= @host_clock_hz
+          end
+          @phase = phase
+          settle! if @asleep && @ieee_port.lines_moved?
+          @ieee_port.latch_host
+        end
+
+        def cycle!
+          settle!
+          run_cycle
+        end
+
+        private
+
+        def settled(part)
+          settle!
+          part
+        end
+      end
+    end
+  end
+end

data/lib/badline/drives/model8050/fdc_bus.rb

@@ -0,0 +1,102 @@
+# frozen_string_literal: true
+
+module Badline
+  module Drives
+    class Model8050
+      # The floppy controller's bus (schematic 8050001, sheet 2), which
+      # decodes A0-A12 only, so it repeats every 8 KB. A 74LS42 on A10-A12
+      # picks a 1 KB block:
+      #
+      # $0000-$03FF - the 6530 and the VIA: with A7 set the 6530's
+      #               registers, else with A6 set the VIA's, else the
+      #               6530's 64 bytes of RAM, which the controller also
+      #               uses as its stack at $0100
+      # $0400-$13FF - the common RAM
+      # $1400-$1BFF - nothing: open bus
+      # $1C00-$1FFF - the 6530's ROM
+      #
+      # Writes to the ROM and to open bus go nowhere, and a read from open
+      # bus finds the last byte on the data bus.
+      class FDCBus
+        include Addressable
+
+        attr_reader :common, :via, :rriot
+        attr_accessor :data
+
+        # How many writes have changed a byte of the common RAM
+        # (Model8050::Idle).
+        attr_reader :common_changes
+
+        # Whether a counter or an interrupt flag has been read since it was
+        # last cleared (Model8050::Idle).
+        attr_accessor :volatile
+
+        def initialize(common:, via:, rriot:)
+          addressable_at(0, length: 2**16)
+          @common = common
+          @via = via
+          @rriot = rriot
+          @data = 0
+          @volatile = false
+          @common_changes = 0
+        end
+
+        def peek(addr)
+          addr &= 0x1fff
+          @data = if addr < 0x0400
+                    peek_chips(addr)
+                  elsif addr < 0x1400
+                    @common.peek(addr - 0x0400)
+                  elsif addr >= 0x1c00
+                    @rriot.read_rom(addr)
+                  else
+                    @data
+                  end
+        end
+
+        def poke(addr, value)
+          @data = value
+          addr &= 0x1fff
+          if addr < 0x0400
+            poke_chips(addr, value)
+          elsif addr < 0x1400
+            poke_common(addr - 0x0400, value)
+          end
+        end
+
+        private
+
+        def poke_common(index, value)
+          @common_changes += 1 if @common.peek(index) != value
+          @common.poke(index, value)
+        end
+
+        def peek_chips(addr)
+          if addr.anybits?(0x80)
+            @volatile = true if addr.anybits?(0x04)
+            return @rriot.peek(addr & 0x0f)
+          end
+          return peek_via(addr & 0x0f) if addr.anybits?(0x40)
+
+          @rriot.read_ram(addr)
+        end
+
+        # The VIA's counters, shift register and flags move on their own.
+        def peek_via(register)
+          @volatile = true if register.between?(0x04, 0x0a) || register == 0x0d
+          @via.peek(0x40 | register)
+        end
+
+        def poke_chips(addr, value)
+          if addr.anybits?(0x80)
+            @rriot.poke(addr & 0x0f, value)
+          elsif addr.anybits?(0x40)
+            @via.poke(0x40 | (addr & 0x0f), value)
+          else
+            @rriot.write_ram(addr, value)
+          end
+        end
+      end
+    end
+  end
+end