badline 0.16.1 → 0.18.0

data/lib/badline/drives/model8050/mechanism.rb

@@ -0,0 +1,230 @@
+# frozen_string_literal: true
+
+module Badline
+  module Drives
+    class Model8050
+      # The unit's two drives as the floppy controller sees them through
+      # the VIA and the 6530 (schematic 8050001, sheets 2 and 3).
+      #
+      # VIA port B runs the drives: PB5 drive 0's motor and PB4 drive 1's,
+      # each on while low, PB2-3 drive 0's stepper phases and PB0-1 drive
+      # 1's, and PB7 reads SYNC, low while ten one bits sit in the shift
+      # register. The 6530's port B picks the drive on PB0, the zone on
+      # PB1-2 and the side on PB4, low for the second, and reads write
+      # protect on PB3, high while the disk can't be written, and the sides
+      # on PB6, low for two, which jumper E3 grounds on the 8250. Its port
+      # A holds the byte to write.
+      #
+      # Each phase change moves the head a track: the controller steps
+      # through the Gray code 00, 10, 11, 01 outward and back the other way
+      # inward ($FF9C), and bumps the head against track 1 with 92 steps
+      # out.
+      #
+      # A turning disk passes one byte cell under the head every ten bit
+      # cells, at 6 MHz divided by 16 less the track's zone, and the byte
+      # cells come round 300 times a minute (Disk). Each data cell ends in
+      # byte ready, which latches the GCR ROM's byte into VIA port A through
+      # CA1 and pulses the controller's SO pin; a sync cell holds SYNC low
+      # for the cell after it instead. While the VIA's CB2 is low the drive
+      # writes: each cell takes the 6530's port A, or a sync while CA2 is
+      # high, and still ends in byte ready.
+      #
+      # A disk going in or out passes the write-protect sensor, which the
+      # controller watches for a disk change: it reads high for a while.
+      class Mechanism
+        WRITE_PROTECT = 0x08
+        ONE_SIDE = 0x40
+
+        # The cycles the write-protect sensor reads high as a disk goes in
+        # or out, ten of the controller's 5 ms interrupts.
+        CHANGE_CYCLES = 50_000
+
+        attr_reader :sides, :data_in, :cylinders, :so_pending
+        attr_accessor :via, :rriot
+
+        def initialize(sides:)
+          @sides = sides
+          @via = nil
+          @rriot = nil
+          @disks = [nil, nil]
+          @cylinders = [0, 0]
+          @phases = [0, 0]
+          @positions = [0, 0]
+          @clocks = [0, 0]
+          @changing = [0, 0]
+          @motors = [false, false]
+          @so_pending = false
+          @data_in = 0xff
+          @syncs = [false, false]
+          @ca1_low = false
+        end
+
+        # The Disk in +drive+, 0 or 1, or nil.
+        def disk(drive = 0) = @disks[drive]
+
+        def insert(disk, drive = 0)
+          @disks[drive]&.flush
+          @disks[drive] = disk
+          @changing[drive] = CHANGE_CYCLES
+        end
+
+        def flush
+          @disks.each { |disk| disk&.flush }
+        end
+
+        def motor_on?(drive = 0) = @motors[drive]
+
+        # The track under +drive+'s head on the side the 6530 picks.
+        def track(drive = 0)
+          side = drive == selected_drive ? selected_side : 0
+          @cylinders[drive] + 1 + (side * Storage::D80Image::SIDE_TRACKS)
+        end
+
+        def cycle!
+          if @ca1_low
+            @ca1_low = false
+            @via.ca1 = true
+          end
+          drives = @via.port_b_output
+          turn(0, drives.nobits?(0x20), (drives >> 2) & 0x03)
+          turn(1, drives.nobits?(0x10), drives & 0x03)
+        end
+
+        # Whether a cycle would change nothing: both motors off, no disk
+        # going in or out, and no byte ready under way.
+        def quiet?
+          !@motors[0] && !@motors[1] && @changing[0].zero? && @changing[1].zero? && !@ca1_low && !@so_pending
+        end
+
+        # What the drives hold, for comparing them at two points.
+        def idle_state = [*@cylinders, *@phases, *@motors, *@syncs, @data_in]
+
+        # Whether byte ready pulses the controller's SO pin this cycle,
+        # which takes the pulse.
+        def take_so
+          so = @so_pending
+          @so_pending = false
+          so
+        end
+
+        # Whether ten one bits sit in the shift register, off the selected
+        # drive's head.
+        def sync? = @syncs[selected_drive]
+
+        # The 6530's port B inputs.
+        def status_lines
+          lines = 0xff
+          lines &= ~WRITE_PROTECT unless write_protected?(selected_drive)
+          @sides == 2 ? lines & ~ONE_SIDE : lines
+        end
+
+        private
+
+        def selected_drive = @rriot.port_b_output & 0x01
+
+        def selected_side = @sides == 2 && @rriot.port_b_output.nobits?(0x10) ? 1 : 0
+
+        def write_protected?(drive)
+          return true if @changing[drive].positive?
+
+          disk = @disks[drive]
+          disk ? disk.write_protected? : false
+        end
+
+        def turn(drive, motor, phase)
+          @changing[drive] -= 1 if @changing[drive].positive?
+          step(drive, phase) if phase != @phases[drive]
+          motor_off(drive) if @motors[drive] && !motor
+          @motors[drive] = motor
+          return @syncs[drive] = false unless motor && @disks[drive]
+
+          clock = @clocks[drive] + 6
+          byte = 10 * (16 - Disk.zone_of(track(drive)))
+          if clock >= byte
+            clock -= byte
+            pass_cell(drive)
+          end
+          @clocks[drive] = clock
+        end
+
+        # Gray code index of a phase pair: 00, 10, 11, 01.
+        def phase_index(phase) = [0, 3, 1, 2][phase]
+
+        def step(drive, phase)
+          change = (phase_index(phase) - phase_index(@phases[drive])) & 0x03
+          @phases[drive] = phase
+          cylinder = @cylinders[drive]
+          if change == 1
+            cylinder -= 1
+          elsif change == 3
+            cylinder += 1
+          end
+          @cylinders[drive] = cylinder.clamp(0, Storage::D80Image::SIDE_TRACKS - 1)
+        end
+
+        def motor_off(drive)
+          @disks[drive]&.flush
+        end
+
+        # A cell has passed under +drive+'s head.
+        def pass_cell(drive)
+          disk = @disks[drive]
+          number = track(drive)
+          cells = disk.track(number)
+          return unless cells
+
+          position = @positions[drive] % cells.length
+          @positions[drive] = position + 1
+          return unless drive == selected_drive
+
+          writing? ? write_cell(drive, disk, number, cells, position) : read_cell(drive, cells, position)
+        end
+
+        def writing? = (@via.pcr & 0xe0) == 0xc0
+
+        def read_cell(drive, cells, position)
+          cell = cells[position]
+          @syncs[drive] = cell == Disk::SYNC
+          byte_ready(cell) unless cell == Disk::SYNC
+        end
+
+        def write_cell(drive, disk, number, cells, position)
+          cells[position] = @via.pcr.allbits?(0x0e) ? Disk::SYNC : @rriot.port_a_output
+          disk.written(number)
+          @syncs[drive] = false
+          byte_ready(@data_in)
+        end
+
+        def byte_ready(byte)
+          @data_in = byte
+          @via.ca1 = false
+          @ca1_low = true
+          @so_pending = true
+        end
+      end
+
+      # VIA port A reads the decoded byte, and PB7 SYNC, low while the
+      # shift register holds a sync.
+      class ReadLines
+        def initialize(mechanism)
+          @mechanism = mechanism
+        end
+
+        def read_a(_lines) = @mechanism.data_in
+
+        def read_b(_lines) = @mechanism.sync? ? 0x7f : 0xff
+      end
+
+      # The 6530's port B inputs from the drives.
+      class StatusLines
+        def initialize(mechanism)
+          @mechanism = mechanism
+        end
+
+        def read_a(_lines) = 0xff
+
+        def read_b(_lines) = @mechanism.status_lines
+      end
+    end
+  end
+end

data/lib/badline/drives/model8050/parts.rb

@@ -0,0 +1,37 @@
+# frozen_string_literal: true
+
+module Badline
+  module Drives
+    class Model8050
+      # Each chip a class of its own, so each keeps one type of peripheral.
+
+      # UC1, on the IEEE-488 data lines.
+      class DataRIOT < Chips::RIOT
+      end
+
+      # UE1, on the control lines, the jumpers and the LEDs.
+      class ControlRIOT < Chips::RIOT
+      end
+
+      # UM3, the controller's VIA, at $0040.
+      class ControllerVIA < Chips::VIA
+      end
+
+      # UK3, the controller's 6530, its ROM the controller's program.
+      class ControllerRRIOT < Chips::RRIOT
+      end
+
+      # The interface processor's 6502, UN1, on the IPBus.
+      class IPCPU
+        include Badline::Chips::CPU::Core
+        include Engine::IdleCPU
+      end
+
+      # The floppy controller's 6502, UH3, on the FDCBus.
+      class FDCCPU
+        include Badline::Chips::CPU::Core
+        include Engine::IdleCPU
+      end
+    end
+  end
+end

data/lib/badline/drives/model8050.rb

@@ -0,0 +1,131 @@
+# frozen_string_literal: true
+
+require "badline/chips/riot"
+require "badline/chips/rriot"
+require "badline/drives/ieee_bus"
+require "badline/drives/engine"
+require "badline/drives/model8050/ip_bus"
+require "badline/drives/model8050/fdc_bus"
+require "badline/drives/model8050/parts"
+require "badline/drives/model8050/ieee_port"
+require "badline/drives/model8050/disk"
+require "badline/drives/model8050/mechanism"
+require "badline/drives/model8050/dos_board"
+require "badline/drives/model8050/board"
+require "badline/drives/model8050/idle"
+require "badline/drives/model8050/keyed_state"
+
+module Badline
+  module Drives
+    # The 8050 dual disk drive of the PET and CBM-II, two drives on one
+    # IEEE-488 unit (schematic 8050001; the 8050/8250 service manual).
+    #
+    # Two 6502s share the board (Board), clocked at 1 MHz from one 12 MHz
+    # crystal on opposite phases. The interface processor (IP) runs DOS 2.7
+    # from 16 KB of ROM at $C000, with two 6532s (IPBus): their RAM is its
+    # zero page and stack, and their ports face the IEEE-488 bus
+    # (IEEEPort). The floppy controller (FDC) runs the 1 KB program in its
+    # 6530's ROM, with a VIA and the 6530 facing the drives (FDCBus,
+    # Mechanism). The two meet in 4 KB of common RAM, which each reaches in
+    # its own half of the cycle: the IP leaves jobs there, and the FDC runs
+    # them.
+    #
+    # Reset starts both. The FDC waits on the common RAM for the IP, which
+    # tests it, copies the FDC's start-up code into it ($C370) and waits for
+    # the FDC to answer, before both settle into their idle loops.
+    class Model8050
+      include Board
+      include Idle
+
+      CLOCK_HZ = 1_000_000
+
+      # The host cycles by which a unit switched on with the machine has
+      # run the IP's RAM test and the FDC's start-up and reads its jumpers.
+      BOOT_CYCLES = 1_500_000
+
+      def model_name = "8050"
+
+      def boot_cycles = BOOT_CYCLES
+
+      # The sides each drive's disk has.
+      def sides = 1
+
+      # +dos_rom+ covers $C000-$FFFF and +fdc_rom+ is the 6530's mask, each
+      # defaulting to the image in the ROM path: DOS 2.7 and the mask for
+      # MPI mechanisms. +device+ is the number the jumpers set, 8 to 15.
+      def initialize(dos_rom: nil, fdc_rom: nil, host_clock_hz: CLOCK_HZ, device: 8)
+        @device = device
+        @host_clock_hz = host_clock_hz
+        @phase = 0
+        @cycles = 0
+        build_ip(dos_rom || ROM.load("8050/dos-2.7.rom", 0xc000))
+        build_fdc(fdc_rom || ROM.read("8050/fdc-901869-01.rom"))
+        @ip_cpu = IPCPU.new(@ip_bus)
+        @fdc_cpu = FDCCPU.new(@fdc_bus)
+        init_idle(Idle::IP_LOOP, Idle::FDC_LOOP)
+        @ieee_bus.attach(self)
+      end
+
+      # Puts in the .d80 or .d82 image at +path+, write-protected with
+      # `read_only`.
+      def insert_image(path, drive: 0, read_only: false)
+        image_class = File.extname(path).casecmp?(".d82") ? Storage::D82Image : Storage::D80Image
+        insert(Disk.new(image_class.new(path, read_only:)), drive:)
+      end
+
+      private
+
+      def build_ip(rom)
+        @common = Memory.new([], length: 0x1000)
+        @ieee_bus = IEEEBus.new
+        @ieee_port = IEEEPort.new(device: @device, bus: @ieee_bus)
+        @data_riot = DataRIOT.new(peripheral: DataLines.new(@ieee_port))
+        @control_riot = ControlRIOT.new(peripheral: ControlLines.new(@ieee_port))
+        @ieee_port.data_riot = @data_riot
+        @ieee_port.control_riot = @control_riot
+        @ip_bus = IPBus.new(rom:, common: @common, data_riot: @data_riot, control_riot: @control_riot)
+      end
+
+      def build_fdc(rom)
+        @mechanism = Mechanism.new(sides:)
+        @via = ControllerVIA.new(start: 0x0040, peripheral: ReadLines.new(@mechanism))
+        @rriot = ControllerRRIOT.new(rom:, peripheral: StatusLines.new(@mechanism))
+        @fdc_bus = FDCBus.new(common: @common, via: @via, rriot: @rriot)
+        @mechanism.via = @via
+        @mechanism.rriot = @rriot
+      end
+
+      # The disk a BL-D8-DISK module holds (KeyedState).
+      def disk_from_fields(input, detached) = Disk.from_fields(input, detached:)
+
+      # One cycle of the board: the drives, then the chips, then the IP and
+      # the FDC, each in its own half of the cycle. ATN reaches UE1's PA7 as
+      # the port latched it. UE1 pulls the IP's IRQ, and the VIA and the
+      # 6530 the FDC's. Byte ready sets the FDC's V flag through SO for the
+      # next cycle's instruction step, as on the 1541.
+      def step
+        so = @mechanism.take_so
+        @mechanism.cycle!
+        @control_riot.pa7 = @ieee_port.atn_low?
+        @data_riot.cycle!
+        @control_riot.cycle!
+        @via.cycle!
+        @rriot.cycle!
+        @ip_cpu.irq = @control_riot.irq?
+        @ip_cpu.cycle!
+        @fdc_cpu.irq = @via.irq? || @rriot.irq?
+        @fdc_cpu.so! if so
+        @fdc_cpu.cycle!
+        @cycles += 1
+      end
+    end
+
+    # The 8250: the 8050's board driving double-sided mechanisms, 154 tracks
+    # a disk, with jumper E3 grounding the 6530's PB6 to say so.
+    class Model8250 < Model8050
+      def model_name = "8250"
+
+      def sides = 2
+    end
+  end
+end

data/lib/badline/drives/model9060/idle.rb

@@ -0,0 +1,149 @@
+# frozen_string_literal: true
+
+module Badline
+  module Drives
+    class Model9060
+      # Sleeping through the two processors' idle loops, exactly, as
+      # Model8050::Idle does.
+      #
+      # With nothing to do, the IP goes round DOS 3.0's idle loop from
+      # IP_LOOP, and the SASI host round its job loop from SASI_LOOP, each
+      # pass finding the job queue empty, until ATN interrupts the IP. The
+      # host has no interrupt of its own. A pass puts back what it found, so
+      # each processor comes back to its loop's start as it left it.
+      #
+      # Each time a processor comes to its loop's start, the unit compares
+      # what that processor sees with what it saw last time round: the CPU,
+      # its chips but for their counters, its RAM and the common RAM. The
+      # same, with no read of a counter or an interrupt flag between, makes
+      # the pass repeatable. Once both are, with the hard disk's controller
+      # idle and no interrupt pulled, the unit sleeps until a counter is due
+      # to pull IRQ, the IEEE-488 controller moves a line, or something
+      # outside reads or changes the unit (settle!).
+      module Idle
+        IP_LOOP = 0xc131
+        SASI_LOOP = 0xf8f1
+
+        # Whether the unit may sleep through its idle loops.
+        attr_reader :idle_skip
+
+        def idle_skip=(on)
+          settle!
+          @idle_skip = on
+        end
+
+        def asleep? = @asleep
+
+        # Brings the unit up to the present, cycle for cycle, and drops the
+        # passes it found, since whoever called may change it.
+        def settle!
+          wake! if @asleep
+          forget_passes
+        end
+
+        private
+
+        def init_idle
+          @idle_skip = true
+          @asleep = false
+          @owed = 0
+          @budget = 0
+          forget_passes
+        end
+
+        def forget_passes
+          @ip_mark = nil
+          @sasi_mark = nil
+          @ip_pass = nil
+          @sasi_pass = nil
+        end
+
+        def owe_cycle
+          @owed += 1
+          wake! if @owed >= @budget
+        end
+
+        def watch_loops
+          ip = @ip_cpu
+          @ip_pass = nil if ip.irq
+          @sasi_pass = nil if @sasi_cpu.irq
+          ip_pass_found if ip.program_counter == IP_LOOP && ip.boundary?
+          host = @sasi_cpu
+          sasi_pass_found if host.program_counter == SASI_LOOP && host.boundary?
+        end
+
+        def ip_pass_found
+          state = ip_state
+          @ip_pass = repeated(@ip_mark, state, @ip_cpu, @ip_bus.volatile)
+          @ip_mark = [state, @ip_cpu.cycles, @ip_cpu.instructions]
+          @ip_bus.volatile = false
+          fall_asleep if @ip_pass && @sasi_pass
+        end
+
+        def sasi_pass_found
+          state = sasi_state
+          @sasi_pass = repeated(@sasi_mark, state, @sasi_cpu, @sasi_bus.volatile)
+          @sasi_mark = [state, @sasi_cpu.cycles, @sasi_cpu.instructions]
+          @sasi_bus.volatile = false
+          fall_asleep if @ip_pass && @sasi_pass
+        end
+
+        def repeated(mark, state, cpu, volatile)
+          return nil if mark.nil? || volatile || mark[0] != state
+
+          [cpu.cycles - mark[1], cpu.instructions - mark[2]]
+        end
+
+        def fall_asleep
+          target = @target
+          return unless target.quiet? && !target.busy? && !@ip_cpu.irq && !@sasi_cpu.irq
+
+          budget = quiet_cycles
+          return if budget < 2
+
+          @asleep = true
+          @owed = 0
+          @budget = budget
+        end
+
+        def quiet_cycles
+          [@data_riot.quiet_cycles, @control_riot.quiet_cycles, @via.quiet_cycles].min
+        end
+
+        def wake!
+          owed = @owed
+          @asleep = false
+          @owed = 0
+          return if owed.zero?
+
+          @data_riot.fast_forward(owed)
+          @control_riot.fast_forward(owed)
+          @via.fast_forward(owed)
+          @target.fast_forward(owed)
+          skip(@ip_cpu, @ip_pass, @ip_mark, owed)
+          skip(@sasi_cpu, @sasi_pass, @sasi_mark, owed)
+          @cycles += owed
+        end
+
+        def skip(cpu, pass, mark, owed)
+          passes = owed / pass[0]
+          cpu.fast_forward(passes * pass[0], passes * pass[1])
+          mark[1] += passes * pass[0]
+          mark[2] += passes * pass[1]
+          (owed - (passes * pass[0])).times { cpu.cycle! }
+        end
+
+        def ip_state
+          [*@ip_cpu.idle_state, *@data_riot.idle_state, *@control_riot.idle_state, @ip_bus.data, common_changes]
+        end
+
+        def sasi_state
+          [*@sasi_cpu.idle_state, *@via.idle_state, *@lines.state, *@sasi_bus.ram.read(0, 0x80), @sasi_bus.data,
+           common_changes]
+        end
+
+        def common_changes = @ip_bus.common_changes + @sasi_bus.common_changes
+      end
+    end
+  end
+end

data/lib/badline/drives/model9060/keyed_state.rb

@@ -0,0 +1,123 @@
+# frozen_string_literal: true
+
+module Badline
+  module Drives
+    class Model9060
+      class SASITarget
+        # The controller's fields in a keyed snapshot module (BL-D8-SASI):
+        # the bus phase, REQ, the cycles left to the next, the command, the
+        # bytes of the phase and the place in them, the write under way,
+        # the sense bytes, the fast mode, its clock, the heads' cylinder, the
+        # geometry and the block buffer, then the image's path and how it
+        # was opened. The image itself stays in its file, which each write
+        # reached as it ended.
+        module KeyedState
+          def save_fields(out)
+            out.int("phase", @phase).bool("request", @request).int("delay", @delay)
+            out.ints("command", @command).ints("buffer", @buffer).int("index", @index)
+            out.bool("writing", @writing).ints("sense", @sense).ints("last_sense", @last_sense)
+            out.bool("fast", @fast).int("cycle", @cycle).int("cylinder", @cylinder)
+            out.int("heads", @heads).int("sectors", @sectors).ints("block_buffer", @block_buffer)
+            disk = @disk
+            out.text("path", disk.nil? ? "" : disk.path.to_s).bool("read_only", disk.nil? || disk.read_only?)
+            out.int("disk_heads", disk.nil? ? 0 : disk.heads)
+          end
+
+          # A detached reader, or a host file that is gone, leaves the drive
+          # empty.
+          def load_fields(input, detached: false)
+            load_bus_fields(input)
+            path = input.text("path", "")
+            read_only = input.bool("read_only", false)
+            heads = input.int("disk_heads", 4)
+            @disk = detached || !File.file?(path) ? nil : Storage::D90Image.new(path, read_only:, heads:)
+          end
+
+          private
+
+          def load_bus_fields(input)
+            @phase = input.int("phase", @phase)
+            @request = input.bool("request", @request)
+            @delay = input.int("delay", @delay)
+            @command = input.ints("command", @command).dup
+            @buffer = input.ints("buffer", @buffer).dup
+            @index = input.int("index", @index)
+            @writing = input.bool("writing", @writing)
+            @sense = input.ints("sense", @sense).dup
+            @last_sense = input.ints("last_sense", @last_sense).dup
+            @fast = input.bool("fast", @fast)
+            @cycle = input.int("cycle", @cycle)
+            @cylinder = input.int("cylinder", @cylinder)
+            @heads = input.int("heads", @heads)
+            @sectors = input.int("sectors", @sectors)
+            @block_buffer = input.ints("block_buffer", @block_buffer).dup
+          end
+        end
+
+        include KeyedState
+      end
+
+      # The unit's own fields in a keyed snapshot module (BL-D8): its model,
+      # its clock phase and cycle count, each bus's last byte, the
+      # controller's lines as the port latched them, under ieee.*, and the
+      # SASI lines' ACK and RST levels. A save settles the unit first, so it
+      # is awake; a load finds its passes afresh.
+      module KeyedState
+        def save_fields(out)
+          settle!
+          out.text("model", model_name).int("phase", @phase).int("cycles", @cycles)
+          out.int("ip_data", @ip_bus.data).int("sasi_data", @sasi_bus.data)
+          out.int("ieee.host", @ieee_port.host)
+          ack_high, reset_high = @lines.state
+          out.bool("sasi.ack_high", ack_high).bool("sasi.reset_high", reset_high)
+          out
+        end
+
+        def load_fields(input)
+          settle!
+          input.choice("model", [model_name], model_name)
+          @phase = input.int("phase", @phase)
+          @cycles = input.int("cycles", @cycles)
+          @ip_bus.data = input.byte("ip_data", @ip_bus.data)
+          @sasi_bus.data = input.byte("sasi_data", @sasi_bus.data)
+          @ieee_port.host = input.int("ieee.host", @ieee_port.host)
+          @lines.state = [input.bool("sasi.ack_high", true), input.bool("sasi.reset_high", false)]
+        end
+
+        # The unit as modules of its own, named from `name` (BL-D8 for
+        # device 8): its own fields, the common RAM, UC1 and UE1 with their
+        # RAM, each processor, the host's RAM and VIA, and the hard disk's
+        # controller.
+        def save_modules(sections, name)
+          sections << Snapshot::Keyed.section(name) { |out| save_fields(out) }
+          sections << Snapshot::Keyed.section("#{name}-COMMON") { |out| @common.save_fields(out, "ram") }
+          sections << Snapshot::Keyed.section("#{name}-RIOT1") { |out| @data_riot.save_fields(out) }
+          sections << Snapshot::Keyed.section("#{name}-RIOT2") { |out| @control_riot.save_fields(out) }
+          sections << Snapshot::Keyed.section("#{name}-IPCPU") { |out| @ip_cpu.save_fields(out) }
+          sections << Snapshot::Keyed.section("#{name}-SASICPU") { |out| @sasi_cpu.save_fields(out) }
+          sections << Snapshot::Keyed.section("#{name}-SASIRAM") { |out| @sasi_bus.ram.save_fields(out, "ram") }
+          sections << Snapshot::Keyed.section("#{name}-VIA") { |out| @via.save_fields(out) }
+          sections << Snapshot::Keyed.section("#{name}-SASI") { |out| @target.save_fields(out) }
+        end
+
+        # The unit from its modules, `input` being its own.
+        def load_modules(modules, input, name)
+          load_fields(input)
+          @common.load_fields(modules.required("#{name}-COMMON"), "ram")
+          @data_riot.load_fields(modules.required("#{name}-RIOT1"))
+          @control_riot.load_fields(modules.required("#{name}-RIOT2"))
+          @ip_cpu.load_fields(modules.required("#{name}-IPCPU"))
+          @sasi_cpu.load_fields(modules.required("#{name}-SASICPU"))
+          @sasi_bus.ram.load_fields(modules.required("#{name}-SASIRAM"), "ram")
+          @via.load_fields(modules.required("#{name}-VIA"))
+          @target.load_fields(modules.required("#{name}-SASI"), detached: modules.detached?)
+          @via.restored!
+          @ip_cpu.restored!
+          @sasi_cpu.restored!
+        end
+      end
+
+      include KeyedState
+    end
+  end
+end