badline 0.16.1 → 0.18.0

data/lib/badline/chips/tpi.rb

@@ -0,0 +1,233 @@
+# frozen_string_literal: true
+
+require "badline/chips/tpi/keyed_state"
+
+module Badline
+  module Chips
+    # The MOS 6525 TPI (tri-port interface): three 8-bit ports, A, B and C,
+    # each with a direction register, a 1 making the pin an output. Its
+    # three address lines repeat the eight registers every 8 bytes:
+    #
+    # 0 - PRA
+    # 1 - PRB
+    # 2 - PRC, or in mode 1 the interrupt latches (bits 0-4) and the levels
+    #     of IRQ, CA and CB (bits 5-7)
+    # 3 - DDRA
+    # 4 - DDRB
+    # 5 - DDRC, which in mode 1 is the interrupt mask, its bits 0-4 enabling
+    #     I0-I4 with a 1, and reads back all eight bits written
+    # 6 - CR: bit 0 MC, the mode, bit 1 IP, the priority, bits 2-3 IE3 and
+    #     IE4, the active edges of I3 and I4 (1 rising), bits 4-5 CA's mode
+    #     and bits 6-7 CB's
+    # 7 - AIR, the active interrupt register, in mode 1
+    #
+    # A port reads its pins: an output's level, and what the peripheral
+    # lets through of an input, which floats high (read_a, read_b and
+    # read_c pull lines low, as a VIA's peripheral does).
+    #
+    # In mode 1 PC0-PC4 are the interrupt inputs I0-I4 (#interrupt_line).
+    # A falling edge on I0-I2, or the edge IE3 and IE4 pick on I3 and I4,
+    # sets the input's latch whether or not its mask bit is set. A write of
+    # 0 to a latch's bit of PRC clears it, and a 1 does nothing. PC5 is
+    # the IRQ output, open drain, low (#irq?) while the AIR holds a bit;
+    # PC6 is CA and PC7 CB (#ca?, #cb?).
+    #
+    # Without priority (IP 0), the AIR holds every unmasked latch that is
+    # set, and a read of it clears them and it. With priority (IP 1) the
+    # inputs rank I4 > I3 > I2 > I1 > I0, and the AIR holds the one highest
+    # unmasked latch that outranks the interrupt in service, the top of a
+    # five-level stack. A read of the AIR pushes it on the stack, clears it
+    # and its latch, and lets IRQ go; a write pops the stack, letting lower
+    # interrupts through again.
+    #
+    # CA: 00 set high by I3's active edge and low by a read of PRA, 01
+    # pulsed low by a read of PRA, 10 low, 11 high. CB: 00 set low by a
+    # write of PRB and high by I4's active edge, 01 pulsed low by a write of
+    # PRB, 10 low, 11 high. A pulse is shorter than a cycle, so CA and CB
+    # read high in mode 01.
+    #
+    # The rules are the MPS 6525 datasheet's (Commodore Semiconductor
+    # Group), pages 2-81 to 2-83.
+    class TPI
+      STACK_DEPTH = 5
+
+      attr_reader :peripheral, :latches, :control, :stack
+
+      def initialize(peripheral: nil)
+        @peripheral = peripheral
+        @lines = 0x1f
+        @stack = []
+        reset!
+      end
+
+      # The RES pin clears every register: mode 0, and every pin an input.
+      def reset!
+        @pra = @prb = @prc = 0
+        @ddra = @ddrb = @ddrc = 0
+        @control = 0
+        @latches = 0
+        @air = 0
+        @stack.clear
+        @ca = @cb = false
+      end
+
+      # The interrupt mask in mode 1: DDRC's bits 0-4.
+      def mask = @ddrc & 0x1f
+
+      # Whether IRQ is pulled low.
+      def irq? = @air != 0
+
+      # The levels of CA and CB in mode 1.
+      def ca? = @ca
+
+      def cb? = @cb
+
+      # The port lines as the chip drives them, inputs floating high.
+      def port_a_output = driven(@pra, @ddra)
+
+      def port_b_output = driven(@prb, @ddrb)
+
+      def port_c_output = mode1? ? pins_c_mode1 : driven(@prc, @ddrc)
+
+      # Something outside drives interrupt input +index+, I0 to I4, +high+
+      # or low. Its active edge sets its latch in mode 1.
+      def interrupt_line(index, high)
+        bit = 1 << index
+        was_high = @lines.anybits?(bit)
+        return if was_high == high
+
+        @lines = high ? @lines | bit : @lines & ~bit
+        return unless mode1? && high == rising_active?(index)
+
+        @latches |= bit
+        @ca = true if index == 3 && ca_mode.zero?
+        @cb = true if index == 4 && cb_mode.zero?
+        update_air
+      end
+
+      def peek(addr)
+        case addr & 0x07
+        when 0 then read_pra
+        when 1 then pins(@prb, @ddrb, @peripheral ? @peripheral.read_b(port_b_output) : 0xff)
+        when 2 then mode1? ? pins_c_mode1 : read_pins_c
+        when 3 then @ddra
+        when 4 then @ddrb
+        when 5 then @ddrc
+        when 6 then @control
+        else read_air
+        end
+      end
+
+      def poke(addr, value)
+        case addr & 0x07
+        when 0 then @pra = value
+        when 1 then write_prb(value)
+        when 2 then write_prc(value)
+        when 3 then @ddra = value
+        when 4 then @ddrb = value
+        when 5 then write_ddrc(value)
+        when 6 then write_control(value)
+        else pop_air
+        end
+      end
+
+      private
+
+      def mode1? = @control.anybits?(0x01)
+
+      def priority? = @control.anybits?(0x02)
+
+      def ca_mode = (@control >> 4) & 0x03
+
+      def cb_mode = (@control >> 6) & 0x03
+
+      # I3 and I4 latch on the edge IE3 and IE4 pick, the others falling.
+      def rising_active?(index)
+        case index
+        when 3 then @control.anybits?(0x04)
+        when 4 then @control.anybits?(0x08)
+        else false
+        end
+      end
+
+      def driven(register, direction) = (register & direction) | (~direction & 0xff)
+
+      def pins(register, direction, inputs) = (register & direction) | (inputs & ~direction & 0xff)
+
+      def read_pra
+        @ca = false if mode1? && ca_mode.zero?
+        pins(@pra, @ddra, @peripheral ? @peripheral.read_a(port_a_output) : 0xff)
+      end
+
+      def read_pins_c
+        pins(@prc, @ddrc, @peripheral ? @peripheral.read_c(port_c_output) : 0xff)
+      end
+
+      # The latches, IRQ's level, CA's and CB's.
+      def pins_c_mode1
+        @latches | (irq? ? 0 : 0x20) | (@ca ? 0x40 : 0) | (@cb ? 0x80 : 0)
+      end
+
+      def write_prb(value)
+        @prb = value
+        @cb = false if mode1? && cb_mode.zero?
+      end
+
+      def write_prc(value)
+        return @prc = value unless mode1?
+
+        @latches &= value | 0xe0
+        update_air
+      end
+
+      def write_ddrc(value)
+        @ddrc = value
+        update_air
+      end
+
+      def write_control(value)
+        @control = value
+        @ca = ca_mode.anybits?(0x01) unless ca_mode.zero?
+        @cb = cb_mode.anybits?(0x01) unless cb_mode.zero?
+        update_air
+      end
+
+      def read_air
+        value = @air
+        return value unless mode1?
+
+        @latches &= ~value
+        @air = 0
+        if priority?
+          @stack.shift if @stack.length == STACK_DEPTH
+          @stack << value
+        end
+        update_air
+        value
+      end
+
+      def pop_air
+        return unless mode1?
+
+        @stack.pop
+        update_air
+      end
+
+      # The AIR's bits from the latches, the mask and, with priority, the
+      # interrupt in service.
+      def update_air
+        pending = mode1? ? @latches & mask : 0
+        return @air = pending unless priority?
+
+        highest = highest_bit(pending)
+        @air = highest > (@stack.last || 0) ? highest : 0
+      end
+
+      def highest_bit(bits)
+        bit = 0x10
+        bit >>= 1 while bit.positive? && bits.nobits?(bit)
+        bit
+      end
+    end
+  end
+end

data/lib/badline/chips/vic/bank.rb

@@ -10,6 +10,13 @@ module Badline
       # The machine's bus pushes in what the VIC sees through #connect,
       # #map_character_rom and #map whenever it changes. Until then the bank
       # has a CIA 2, RAM, colour RAM and character ROM of its own.
+      #
+      # The P500 wires the VIC another way (#map_video_bus): its phi1
+      # reads go to the character ROM while VICDOTSEL is high, and its phi2
+      # reads to the 1K static video matrix while STATVID is high, VA12
+      # high picking the matrix and VA12 low reading 0. Otherwise both go to
+      # the DRAM's 16K bank that VA14 and VA15 pick (#video_bus_lines). The
+      # colour nibbles come from the colour RAM in every phi2 read.
       class Bank
         include Addressable
 
@@ -30,6 +37,11 @@ module Badline
           map(Memory.new([], length: 2**16, start: 0))
           @lines = 0b11
           @swapped = false
+          @video_bus = false
+          @matrix = @ram
+          @statvid = false
+          @dotsel = false
+          @video_base = 0
         end
 
         # CIA 2, whose port A picks the bank, and the colour RAM, read from
@@ -57,9 +69,31 @@ module Badline
             @base = base
             @starts = BANK_STARTS.map { |start| base + start }.freeze
           end
-          @phi1_ultimax = phi1_ultimax
-          @ultimax = ultimax
           @romh = romh
+          @phi1_other = phi1_ultimax
+          @phi2_other = ultimax
+        end
+
+        # The P500's video bus: +dram+ is segment 0's 64K, +matrix+ the
+        # static video matrix, read from its start address on, and
+        # +color_ram+ the colour RAM, read from +color_base+ on. The
+        # character ROM is the one #map_character_rom gives, read from
+        # +base+ on.
+        def map_video_bus(dram, matrix, color_ram, color_base)
+          @ram = dram
+          @matrix = matrix
+          @color_ram = color_ram
+          @color_base = color_base
+          @video_bus = true
+          @phi1_other = true
+          @phi2_other = true
+        end
+
+        # STATVID, VICDOTSEL and VA14-VA15, as the P500's TPIs drive them.
+        def video_bus_lines(statvid, dotsel, bank)
+          @statvid = statvid
+          @dotsel = dotsel
+          @video_base = bank << 14
         end
 
         # On the 8565, a port A write that swaps the two bank lines, driving
@@ -74,7 +108,7 @@ module Badline
         end
 
         def peek(offset)
-          return ultimax_peek(offset) if @phi1_ultimax
+          return phi1_other(offset) if @phi1_other
 
           bits = bank_switch_register
           if (bits & @shadow_mask) == 0b01 && (offset & 0xf000) == 0x1000
@@ -88,7 +122,13 @@ module Badline
         # memory configuration the CPU does in that half. No cartridge drives
         # Ultimax mode in the first half alone, so otherwise it reads as #peek.
         def peek_phi2(offset)
-          @ultimax ? ultimax_peek(offset) : peek(offset)
+          @phi2_other ? phi2_other(offset) : peek(offset)
+        end
+
+        # A sprite's s-access in phi2: on the P500's video bus as the other
+        # phi2 reads, and otherwise as #peek.
+        def peek_sprite(offset)
+          @video_bus ? phi2_other(offset) : peek(offset)
         end
 
         def peek_color(offset)
@@ -101,7 +141,7 @@ module Badline
 
         # True if the VIC reads the character ROM at this offset.
         def character_rom?(offset)
-          !@phi1_ultimax && (bank_switch_register & @shadow_mask) == 0b01 && (offset & 0xf000) == 0x1000
+          !@phi1_other && (bank_switch_register & @shadow_mask) == 0b01 && (offset & 0xf000) == 0x1000
         end
 
         def start
@@ -110,6 +150,21 @@ module Badline
 
         private
 
+        def phi1_other(offset)
+          return ultimax_peek(offset) unless @video_bus
+          return @character_rom.peek(@character_base + (offset & 0x0fff)) if @dotsel
+
+          @ram.peek(@video_base + offset)
+        end
+
+        def phi2_other(offset)
+          return ultimax_peek(offset) unless @video_bus
+          return @ram.peek(@video_base + offset) unless @statvid
+          return 0 if offset.nobits?(0x1000)
+
+          @matrix.peek(@matrix.start + (offset & 0x03ff))
+        end
+
         # In Ultimax mode the cartridge ROMH replaces the character ROM
         # shadow, visible at $3000-$3FFF of the window. The MAX is in
         # Ultimax mode with no cartridge too.

data/lib/badline/chips/vic/sprite.rb

@@ -322,12 +322,13 @@ module Badline
         end
 
         # The three s-accesses step MC through the sprite's block, wrapping
-        # within it.
+        # within it. The first and third fall in phi2 and the second in
+        # phi1 (Bank#peek_sprite).
         def row_bits(counter)
           base = pointer * 64
-          (@bank.peek(base + counter) << 16) |
+          (@bank.peek_sprite(base + counter) << 16) |
             (@bank.peek(base + ((counter + 1) & MC_MASK)) << 8) |
-            @bank.peek(base + ((counter + 2) & MC_MASK))
+            @bank.peek_sprite(base + ((counter + 2) & MC_MASK))
         end
 
         def pointer = @bank.peek(@registers.screen_base + 0x3f8 + index)

data/lib/badline/chips/vic_i/keyed_parts.rb

@@ -86,13 +86,15 @@ module Badline
       LINE_LAYOUT = 1
 
       # The VIC-I's fields in a keyed snapshot module (Snapshot::Keyed): the
-      # registers, the beam, the text window's counters and the fetch in
-      # flight, the painter's lines under line.*, the picture, and the sound
+      # registers, the beam, the frame's length in lines and whether the
+      # next interlaced field is the long one, the text window's counters
+      # and the fetch in flight, the painter's lines under line.*, the picture, and the sound
       # under sound.* What the registers decode to, where the line's fetches
       # end and the next event are worked out on load.
       module KeyedState
         def save_fields(out)
           out.bytes("registers", @registers).int("raster", @rasterline).int("column", @column)
+          out.int("frame_lines", @frame_lines).bool("long_field", @long_field)
           out.bool("window_open", @window_open).bool("window_done", @window_done).int("row_start", @row_start)
           out.int("matrix", @matrix).int("char_line", @char_line).int("text_rows", @text_rows)
           out.int("fetch_from", @fetch_from).int("fetched", @fetched).int("code", @code)
@@ -106,6 +108,8 @@ module Badline
           input.bytes_into("registers", @registers)
           @rasterline = input.int("raster", @rasterline)
           @column = input.int("column", @column)
+          @frame_lines = input.int("frame_lines", @lines_per_frame)
+          @long_field = input.bool("long_field", true)
           @window_open = input.bool("window_open", @window_open)
           @window_done = input.bool("window_done", @window_done)
           @row_start = input.int("row_start", @row_start)
@@ -122,6 +126,7 @@ module Badline
         end
 
         def restored!
+          @frame_wrap = @frame_lines == @interlaced_lines ? @count_column : @wrap_column
           @origin_x = @registers[0] & 0x7f
           @columns = @registers[2] & 0x7f
           @origin_y = @registers[1]

data/lib/badline/chips/vic_i.rb

@@ -7,13 +7,15 @@ require "badline/chips/vic_i/keyed_parts"
 
 module Badline
   module Chips
-    # The VIC-I, the 6561 on PAL machines: its sixteen registers, the
+    # The VIC-I, the 6561 on PAL machines or the 6560 on NTSC ones: its
+    # sixteen registers, the
     # raster, the text window's fetches over the V-bus and the picture. The
     # writes to the sound's registers, $900A-$900E, go on to the Sound
     # attached as #sound.
     #
     # The registers repeat through $9000-$90FF. $9003 bit 7 and $9004 read
-    # the raster line, its bit 0 and bits 8-1. $9006 and $9007 read the
+    # the raster count, its bit 0 and bits 8-1, which on the 6561 is the
+    # raster line (see Profile for the 6560's). $9006 and $9007 read the
     # light pen, which nothing triggers yet, and $9008 and $9009 the two
     # pots, which read $FF with nothing plugged in. The other registers
     # read back what was written to them.
@@ -35,23 +37,48 @@ module Badline
     # of a text row where the row started, and the next row starts where
     # the last line of the row left it. It starts the frame at zero.
     #
-    # The picture is 4 pixels a cycle, so 284 a line. A character's 8
-    # pixels come out in the two cycles after its pattern fetch. The
-    # display's lines start 6 cycles after the raster count moves, as
-    # xvic's view of the frame does, so the character fetched 16 cycles
-    # into the line lands 48 pixels in. Lines 0-27 are blanked.
+    # The picture is 4 pixels a cycle, so 284 a line on the 6561 and 260 on
+    # the 6560. A character's 8 pixels come out in the two cycles after its
+    # pattern fetch. The display's lines start 6 cycles after the raster
+    # line moves, as xvic's view of the frame does, so the character
+    # fetched 16 cycles into the line lands 48 pixels in. Lines 0-27 are
+    # blanked.
     class VICI
       include TextWindow
 
       # What a VIC-I sets for the machine: the clock, the raster's cycles
-      # per line and lines per frame, and how many lines at the top of the
-      # frame it blanks. The 6560 of NTSC machines, with its half lines and
-      # the interlace of $9000 bit 7, would be another.
-      Profile = Data.define(:clock_hz, :cycles_per_line, :lines_per_frame, :blanked_lines)
+      # per line and lines per frame, how many lines at the top of the frame
+      # it blanks and how many it shows from there, and where in the line
+      # the raster count $9003 and $9004 read moves on, and how many lines
+      # the long field of an interlaced frame has, or 0 without interlace.
+      #
+      # The 6561's count is the raster line. The 6560's runs ahead of it: it
+      # reads the next line from +count_column+ on, and on the last line it
+      # reads one past the last line from there, then 0 from
+      # +wrap_column+ on, so the count's first and last values each last
+      # about half a line. The 6561's +count_column+ is past the end of the
+      # line, so it never moves early.
+      #
+      # With $9000 bit 7 set at the start of a frame, the 6560 interlaces:
+      # its frames alternate between the long field, +interlaced_lines+
+      # long, and the short one, a line shorter, the long one first. On the
+      # long field's last line the count wraps to 0 where it would move on,
+      # so its first and last values each last a whole line.
+      Profile = Data.define(:clock_hz, :cycles_per_line, :lines_per_frame, :blanked_lines, :shown_lines,
+                            :count_column, :wrap_column, :interlaced_lines)
 
       # The 6561: 71 cycles by 312 lines, lines 0-27 blanked (Marko
       # Mäkelä's VIC-I.txt).
-      PAL = Profile.new(clock_hz: 1_108_405, cycles_per_line: 71, lines_per_frame: 312, blanked_lines: 28)
+      PAL = Profile.new(clock_hz: 1_108_405, cycles_per_line: 71, lines_per_frame: 312, blanked_lines: 28,
+                        shown_lines: 284, count_column: 71, wrap_column: 71, interlaced_lines: 0)
+
+      # The 6560: 65 cycles by 261 lines on a 14.31818 MHz crystal divided
+      # by 14. The count's columns and the lines shown are xvic's, measured
+      # as a black box: the count moves on 28 cycles into the line, and
+      # wraps to 0 on the last line 61 cycles in. Interlaced, its fields are
+      # 263 and 262 lines.
+      NTSC = Profile.new(clock_hz: 1_022_727, cycles_per_line: 65, lines_per_frame: 261, blanked_lines: 28,
+                         shown_lines: 233, count_column: 28, wrap_column: 61, interlaced_lines: 263)
 
       PIXELS_PER_CYCLE = 4
 
@@ -71,6 +98,10 @@ module Badline
         0xb27240, 0xf2b27f, 0xc2655d, 0xbdffff, 0xf299ff, 0x8de57f, 0x806eda, 0xffffa5
       ].freeze
 
+      # The display's lines: the frame's, or the long interlaced field's
+      # where that is longer.
+      attr_reader :height
+
       attr_reader :rasterline, :column, :profile
       attr_accessor :sound
 
@@ -78,7 +109,11 @@ module Badline
         @profile = profile
         @cycles_per_line = profile.cycles_per_line
         @lines_per_frame = profile.lines_per_frame
-        @painter = Painter.new(@lines_per_frame, @cycles_per_line * PIXELS_PER_CYCLE, profile.blanked_lines)
+        @count_column = profile.count_column
+        @wrap_column = profile.wrap_column
+        @interlaced_lines = profile.interlaced_lines
+        @height = [@lines_per_frame, @interlaced_lines].max
+        @painter = Painter.new(@height, @cycles_per_line * PIXELS_PER_CYCLE, profile.blanked_lines)
         @patterns = @painter.patterns
         @colors = @painter.colors
         @counts = @painter.counts
@@ -106,11 +141,14 @@ module Badline
         @origin_x = @origin_y = @columns = @rows = 0
         @char_shift = 3
         @screen_base = @char_base = 0
+        @long_field = true
+        @frame_lines = @lines_per_frame
+        @frame_wrap = @wrap_column
         new_frame
         @fetch_from = @fetch_to = 0
         @fetched = @slot = 0
         @code = 0
-        @painter.power_on!(@lines_per_frame - 1)
+        @painter.power_on!(@frame_lines - 1)
         schedule
       end
 
@@ -131,14 +169,12 @@ module Badline
       # The sixteen registers as written.
       def register_file = @registers.dup
 
-      # The display, a palette index a pixel, 284 to a line and every line
-      # of the frame.
+      # The display, a palette index a pixel, 4 to a cycle of the line, and
+      # every line of the frame.
       def display = @painter.display
 
       def width = @painter.width
 
-      def height = @lines_per_frame
-
       # Whether each line of the display has changed since the front end
       # last cleared them.
       def dirty_lines = @painter.dirty_lines
@@ -157,8 +193,8 @@ module Badline
       def peek(addr)
         register = addr & 0x0f
         case register
-        when 0x03 then ((@rasterline & 0x01) << 7) | (@registers[3] & 0x7f)
-        when 0x04 then @rasterline >> 1
+        when 0x03 then ((raster_count & 0x01) << 7) | (@registers[3] & 0x7f)
+        when 0x04 then raster_count >> 1
         when 0x06, 0x07 then 0
         when 0x08, 0x09 then 0xff
         else @registers[register]
@@ -181,6 +217,16 @@ module Badline
         end
       end
 
+      # The raster count $9003 and $9004 read (see Profile).
+      def raster_count
+        line = @rasterline
+        column = @column
+        return line if column < @count_column
+        return 0 if line == @frame_lines - 1 && column >= @frame_wrap
+
+        line + 1
+      end
+
       private
 
       def event(column)
@@ -205,9 +251,10 @@ module Badline
 
       def start_line
         line = @rasterline + 1
-        if line == @lines_per_frame
+        if line == @frame_lines
           line = 0
           new_frame
+          next_field
         end
         @rasterline = line
         next_text_line if @window_open
@@ -215,6 +262,22 @@ module Badline
         place_fetches
       end
 
+      # How many lines the frame starting has, and where on its last line
+      # the count wraps: the field's, if $9000 bit 7 asks the 6560 to
+      # interlace, else the profile's.
+      def next_field
+        if @interlaced_lines.positive? && @registers[0] >= 0x80
+          long = @long_field
+          @frame_lines = long ? @interlaced_lines : @interlaced_lines - 1
+          @frame_wrap = long ? @count_column : @wrap_column
+          @long_field = !long
+        else
+          @frame_lines = @lines_per_frame
+          @frame_wrap = @wrap_column
+          @long_field = true
+        end
+      end
+
       def place_fetches
         line = @rasterline
         @slot = line * Painter::SLOTS

data/lib/badline/data_path.rb

@@ -24,10 +24,10 @@ module Badline
       File.join(xdg, "badline")
     end
 
-    # The quicksaves, autosaves or saves subfolder of data_path, created
-    # along with data_path if it doesn't exist yet.
+    # The quicksaves, autosaves, saves or tapes subfolder of data_path,
+    # created along with data_path if it doesn't exist yet.
     def data_folder(name)
-      raise ArgumentError, "unknown data folder: #{name}" unless %w[quicksaves autosaves saves].include?(name)
+      raise ArgumentError, "unknown data folder: #{name}" unless %w[quicksaves autosaves saves tapes].include?(name)
 
       path = File.join(data_path, name)
       FileUtils.mkdir_p(path)

data/lib/badline/drives/datasette/keyed_state.rb

@@ -10,7 +10,8 @@ module Badline
       # bytes and how far it has played. A tape that isn't in leaves tape.* out. A datasette that
       # times the read line's level adds when in the countdown the line
       # rises, and whether a recording's low half wave is on the tape. The
-      # sense and flag handlers don't fire on load.
+      # sense and flag handlers don't fire on load, and the running handler
+      # does when the load starts or stops the tape.
       module KeyedState
         def save_fields(out)
           out.bool("playing", @playing).bool("motor", @motor).int("countdown", @countdown)
@@ -33,6 +34,13 @@ module Badline
           @write_high = input.bool("write_high", @write_high)
           @rise_at = input.int("rise_at", @rise_at)
           @low_recorded = input.bool("low_recorded", @low_recorded)
+          load_tape(input)
+          update_running
+        end
+
+        private
+
+        def load_tape(input)
           bytes = input.bytes("tape.bytes", "".b).bytes
           return @tape = nil if bytes.empty?