badline 0.16.1 → 0.18.0

data/lib/badline/pet/cassettes.rb

@@ -11,7 +11,8 @@ module Badline
     # Both record from VIA PB3. The KERNAL reads each tape as the falling
     # edges its read line makes, as the C64 and VIC-20 do. The machine
     # passes the motor and write lines on after each write to the I/O
-    # chips (#lines_written).
+    # chips (#lines_written), and clocks the decks only while a tape runs
+    # (#running?).
     class Cassettes
       attr_reader :datasette1, :datasette2
 
@@ -22,6 +23,18 @@ module Badline
         @datasette2 = Drives::Datasette.new
         @datasette1.on_flag { pulse1 }
         @datasette2.on_flag { pulse2 }
+        @running = false
+        @running_handler = nil
+        @datasette1.on_running_change { update_running }
+        @datasette2.on_running_change { update_running }
+      end
+
+      # Whether either deck's tape runs.
+      def running? = @running
+
+      # Whether either deck's tape runs, each time that changes.
+      def on_running_change(&handler)
+        @running_handler = handler
       end
 
       def cycle!
@@ -48,6 +61,14 @@ module Badline
 
       private
 
+      def update_running
+        running = @datasette1.running? || @datasette2.running?
+        return if running == @running
+
+        @running = running
+        @running_handler&.call
+      end
+
       # A falling edge on a read line, and the line back up.
       def pulse1
         @pia1.ca1 = false

data/lib/badline/pet/ieee_drive.rb

@@ -1,76 +1,17 @@
 # frozen_string_literal: true
 
-require "badline/drives/model2031"
+require "badline/machine/ieee_drives"
 
 module Badline
   class PET
-    # The PET's true drive: a Drives::Model2031 on the IEEE-488 bus
-    # (IEEEPorts), clocked after the CPU each cycle and reset with it, as
-    # the PET's RES line reaches IFC. The traps on the KERNAL's primitives
-    # (IEEETraps) leave device 8 to the drive while it is device 8.
+    # The PET's true drive, a 2031, 8050 or 8250 on its IEEE-488 bus
+    # (IEEEPorts), as Machine::IEEEDrives has it, at the PET's 1 MHz.
     module IEEEDrive
-      # The 2031 on the bus, or nil.
-      attr_reader :drive2031
-
-      # Plugs in a Drives::Model2031, in place of the one there.
-      def attach_drive2031(drive)
-        detach_drive2031
-        drive.host_clock_hz = 1_000_000
-        drive.connect(@ieee.bus)
-        @drive2031 = drive
-        @ieee.lines_written
-        @ieee_trap&.device = trap_device
-        @init_threshold = [@init_threshold, Badline::Drives::Model2031::BOOT_CYCLES].max if @cycles < @init_threshold
-      end
-
-      # Unplugs the 2031, leaving it on a bus of its own.
-      def detach_drive2031
-        drive = @drive2031
-        return unless drive
-
-        drive.connect(Badline::Drives::IEEEBus.new)
-        @drive2031 = nil
-        @ieee_trap&.device = trap_device
-      end
-
-      # The true drive on the bus, or nil.
-      def true_drive = @drive2031
-
-      # Plugs in a 2031 as device 8, in place of the drive there, and
-      # returns it.
-      def plug_true_drive
-        Badline::Drives::Model2031.new.tap { |drive| attach_drive2031(drive) }
-      end
+      include Machine::IEEEDrives
 
       private
 
-      # The 2031 as keyed snapshot modules named from its device number:
-      # BL-D8, BL-D8-CPU and so on for device 8.
-      def save_drive_modules(sections)
-        drive = @drive2031
-        drive&.save_modules(sections, "BL-D#{drive.device}")
-        sections
-      end
-
-      # The 2031 a snapshot's modules hold, built afresh unless one is on
-      # the bus as the same device, or none when they hold no drive. The
-      # bus then carries the PET's lines as its chips left them.
-      def load_drive_modules(modules)
-        device = 8
-        input = modules.optional("BL-D8")
-        while input.nil? && device < 11
-          device += 1
-          input = modules.optional("BL-D#{device}")
-        end
-        if input
-          detach_drive2031 if @drive2031 && @drive2031.device != device
-          attach_drive2031(Badline::Drives::Model2031.new(device:)) unless @drive2031
-          @drive2031.load_modules(modules, input, "BL-D#{device}")
-        else
-          detach_drive2031
-        end
-        @ieee.lines_written
-      end
+      def ieee_host_clock_hz = 1_000_000
     end
   end
 end

data/lib/badline/pet/ieee_ports.rb

@@ -57,6 +57,13 @@ module Badline
         bus.host_lines = controller_lines unless bus.drives.empty?
       end
 
+      # The drives on the bus see the lines the PET pulls now.
+      def push_lines = lines_written
+
+      # Nothing to push once a cycle: the PET pushes its lines as its chips
+      # are written.
+      def cycle_lines = nil
+
       private
 
       def low_lines = @bus.low_lines(controller_lines)

data/lib/badline/pet/keyboard_ports.rb

@@ -42,8 +42,12 @@ module Badline
 
       attr_reader :keyboard
 
+      # Whether the SuperPET's board pulls the diagnostic sense low.
+      attr_accessor :diagnostic_low
+
       def initialize(keyboard)
         @keyboard = keyboard
+        @diagnostic_low = false
         @pia = nil
         @ieee = nil
         @cassettes = nil
@@ -60,8 +64,11 @@ module Badline
 
       # Port A's other lines: PA4 and PA5 read the cassette sense switches,
       # PA6 the IEEE bus's EOI, and the diagnostic sense on PA7 floats high
-      # with nothing on it.
-      def read_a(_lines) = @ieee.eoi_input & @cassettes.sense_input
+      # with nothing on it but the SuperPET's board, which can pull it low.
+      def read_a(_lines)
+        lines = @ieee.eoi_input & @cassettes.sense_input
+        @diagnostic_low ? lines & 0x7f : lines
+      end
 
       def read_b(lines)
         row = @pia.port_a_output & 0x0f

data/lib/badline/pet/keyed_state.rb

@@ -25,7 +25,9 @@ module Badline
         out.int("cycles", @cycles).bool("vertical_drive", @vertical_drive)
         pending = @pending_keys
         out.ints("host.pending_keys", pending) if pending
+        save_init_keys(out)
         out.int("host.init_pending", @cycles <= @init_threshold ? @init_handlers.length : 0)
+        save_ieee_drive_fields(out)
       end
 
       def load_machine_fields(input)
@@ -33,7 +35,9 @@ module Badline
         @vertical_drive = input.bool("vertical_drive", @vertical_drive)
         pending = input.ints("host.pending_keys", [])
         @pending_keys = pending.empty? ? nil : pending.dup
+        load_init_keys(input)
         @init_handlers_lost = [input.int("host.init_pending", 0) - @init_handlers.length, 0].max
+        load_ieee_drive_fields(input)
       end
     end
 

data/lib/badline/pet/model.rb

@@ -17,7 +17,8 @@ module Badline
     # 1K twice over and the 80-column ones with 2K. The 8296 has 128K of
     # dynamic RAM, the 32K below $8000, the 32K above it, of which the
     # screen is the start and the rest lies under the ROMs, and the 64K
-    # board (Bus::Expansion).
+    # board (Bus::Expansion). The SuperPET is an 8032 with the 901640-01
+    # character ROM, twice the 8032's size, and its own board (SuperPET).
     module Model
       Profile = Data.define(:name, :ram_kb, :basic, :editor_50hz, :editor_60hz, :kernal, :characters, :keyboard,
                             :video, :expansion) do
@@ -28,6 +29,9 @@ module Badline
         # The 8296, whose board decodes its memory in a PLA.
         def cbm8296? = name == "8296"
 
+        # The SuperPET, an 8032 with the Waterloo board (SuperPET).
+        def superpet? = name == "superpet"
+
         # The screen RAM's bytes, and on the 8296 all 32K of RAM from $8000.
         def screen_bytes
           return 0x8000 if cbm8296?
@@ -86,7 +90,12 @@ module Badline
                             kernal: "pet/kernal4.rom", characters: "pet/characters2.rom", keyboard: :business,
                             video: :crtc80, expansion: true)
 
-      ALL = [PET2001, PET3032, PET3032B, PET4032, CBM8032, CBM8096, CBM8296].freeze
+      SUPERPET = Profile.new(name: "superpet", ram_kb: 32, basic: "pet/basic4.rom",
+                             editor_50hz: "pet/editor4-80-b-50hz.rom", editor_60hz: "pet/editor4-80-b-60hz.rom",
+                             kernal: "pet/kernal4.rom", characters: "pet/characters-superpet.rom",
+                             keyboard: :business, video: :crtc80, expansion: false)
+
+      ALL = [PET2001, PET3032, PET3032B, PET4032, CBM8032, CBM8096, CBM8296, SUPERPET].freeze
 
       DEFAULT = "8032"
 

data/lib/badline/pet/rom_sets.rb

@@ -39,6 +39,7 @@ module Badline
         "4032" => { "4" => %w[4-40-n-50hz 4-40-n-60hz] },
         "8032" => { "4" => %w[4-80-b-50hz 4-80-b-50hz-0283 4-80-b-60hz] },
         "8096" => { "4" => %w[4-80-b-50hz 4-80-b-50hz-0283 4-80-b-60hz] },
+        "superpet" => { "4" => %w[4-80-b-50hz 4-80-b-50hz-0283 4-80-b-60hz] },
         "8296" => { "4" => %w[4-80-b-50hz-8296 4-80-b-50hz 4-80-b-50hz-0283 4-80-b-60hz] }
       }.freeze
 

data/lib/badline/pet/sound.rb

@@ -8,121 +8,21 @@ module Badline
     # added. CB2 carries the shift register's bits in its shift-out modes,
     # mode 4's free-running square wave under timer 2 for the bell and most
     # PET music, and the PCR's CB2 output otherwise, held high or low by
-    # hand or floating high as an input.
-    #
-    # The machine calls #cycle! once a cycle while #recording?, from #record
-    # on, so a sound nobody records costs only that check. Each sample is
-    # the share of its cycles CB2 spent high, through the output stage: a
-    # one-pole low-pass at 5 kHz and a one-pole high-pass at 100 Hz, so a
-    # line left high or low settles to silence.
+    # hand or floating high as an input. Machine::LineSound turns it into
+    # samples.
     class Sound
-      LOW_PASS_HZ = 5_000
-      HIGH_PASS_HZ = 100
-
-      # A swing from CB2 low to CB2 high, as a signed 16-bit sample.
-      SCALE = 24_000.0
+      include Machine::LineSound
 
       def initialize(via)
         @via = via
-        @recording = false
-        @high = true
-        @run = 0
-        @rate = 0
-        @clock_hz = 0
-        @remainder = 0
-        @window = 0
-        @left = 0
-        @sum = 0
-        @low = 0.0
-        @drift = 0.0
-        @low_pass = 0.0
-        @high_pass = 0.0
-        @samples = []
+        init_line_sound
       end
 
       def model = :cb2
 
-      attr_reader :recording
-      alias recording? recording
-
-      # Starts collecting the output, averaged down to `rate` samples a
-      # second at `clock_hz` cycles a second, for #drain_samples. The
-      # output stage takes CB2's level now as settled.
-      def record(rate:, clock_hz: 1_000_000)
-        @rate = rate
-        @clock_hz = clock_hz
-        @remainder = 0
-        @window = next_window
-        @left = @window
-        @sum = 0
-        @high = @via.cb2_output
-        @run = 0
-        @low = @drift = @high ? 1.0 : 0.0
-        @low_pass = 1.0 - Math.exp(-2.0 * Math::PI * LOW_PASS_HZ / rate)
-        @high_pass = 1.0 - Math.exp(-2.0 * Math::PI * HIGH_PASS_HZ / rate)
-        @samples = []
-        @recording = true
-      end
-
-      # Takes CB2's level for this cycle, while recording.
-      def cycle!
-        high = @via.cb2_output
-        if high == @high
-          @run += 1
-        else
-          hold(@high, @run)
-          @high = high
-          @run = 1
-        end
-      end
-
-      # The samples closed since the last drain.
-      def drain_samples
-        return [] unless @recording
-
-        hold(@high, @run)
-        @run = 0
-        samples = @samples
-        @samples = []
-        samples
-      end
-
       private
 
-      # Adds `cycles` cycles with CB2 high or low, closing every sample
-      # they finish.
-      def hold(high, cycles)
-        left = @left
-        while cycles >= left
-          @sum += left if high
-          cycles -= left
-          close
-          left = @left
-        end
-        @sum += cycles if high
-        @left = left - cycles
-      end
-
-      def close
-        @low += @low_pass * (@sum.fdiv(@window) - @low)
-        @drift += @high_pass * (@low - @drift)
-        sample = ((@low - @drift) * SCALE).round
-        sample = 32_767 if sample > 32_767
-        sample = -32_768 if sample < -32_768
-        @samples << sample
-        @sum = 0
-        @window = next_window
-        @left = @window
-      end
-
-      # Each window is a whole number of cycles, and they add up to the
-      # clock's cycles over a second.
-      def next_window
-        @remainder += @clock_hz
-        cycles = @remainder / @rate
-        @remainder -= cycles * @rate
-        cycles
-      end
+      def line_high? = @via.cb2_output
     end
   end
 end

data/lib/badline/pet/superpet/acia.rb

@@ -0,0 +1,12 @@
+# frozen_string_literal: true
+
+module Badline
+  class PET
+    class SuperPET < PET
+      # The board's 6551 at $EFF0, the RS-232 port's, on a 1.8432 MHz
+      # crystal, whose IRQ joins the PET's.
+      class ACIA < Chips::ACIA
+      end
+    end
+  end
+end

data/lib/badline/pet/superpet/board.rb

@@ -0,0 +1,221 @@
+# frozen_string_literal: true
+
+module Badline
+  class PET
+    class SuperPET < PET
+      # The Waterloo board, after Levak's PET-Interfaces.txt, André
+      # Fachat's SuperPET page and Commodore's 324037 schematic: 64K of
+      # RAM in 16 banks of 4K, one at a time at $9000-$9FFF, and the I/O
+      # page at $EF00 (IOPage), which both CPUs reach.
+      #
+      # The bank latch at $EFFC-$EFFD picks the bank with bits 0-3, and its
+      # bit 7 lets writes reach the system latch at $EFF8-$EFFB:
+      #
+      #   bit 0  the CPU while SW2 is at PROG: 1 the 6502, 0 the 6809
+      #   bit 1  the bank RAM while SW1 is at PROG: 1 read/write, 0 read only
+      #   bit 3  pulls the user port's diagnostic sense, PIA 1's PA7, low
+      #
+      # Bit 0 of $EFFE-$EFFF puts the board's own ROM socket at $9000 in
+      # place of the RAM, which badline leaves empty, while the 6502 runs.
+      # All three are write-only, and the RES line clears them, so the
+      # board starts at bank 0, and with SW2 at PROG with the 6809.
+      #
+      # SW1 is READ, R/W or PROG, the bank RAM's write protect, and SW2
+      # PROG, 6502 or 6809, the CPU. A write to the bank RAM while it is
+      # protected goes nowhere.
+      #
+      # While the 6809 runs, the 8032's ROMs step aside through its NO ROM
+      # line, and the Waterloo ROMs answer at $A000-$E7FF and $F000-$FFFF,
+      # the $E000 one with the CRTC table for the frame rate.
+      class Board
+        CPU_SWITCH = %w[6502 6809 prog].freeze
+
+        RAM_SWITCH = %w[rw read prog].freeze
+
+        # $EF00-$EFFF: the 6702 at $EFE0-$EFE3, the ACIA at $EFF0-$EFF3
+        # and the latches above. A read of a latch finds the last byte on
+        # the bus, and below $EFF0, where neither chip answers, $FF.
+        class IOPage
+          def initialize(board, bus, dongle, acia)
+            @board = board
+            @bus = bus
+            @dongle = dongle
+            @acia = acia
+          end
+
+          def peek(addr)
+            low = addr & 0xff
+            return @bus.data if low >= 0xf4
+            return @acia.peek(addr) if low >= 0xf0
+            return @dongle.peek(addr) if low >= 0xe0 && low < 0xe4
+
+            0xff
+          end
+
+          def poke(addr, value)
+            low = addr & 0xff
+            if low >= 0xfe
+              @board.socket = value
+            elsif low >= 0xfc
+              @board.bank_latch = value
+            elsif low >= 0xf8
+              @board.system_latch = value
+            elsif low >= 0xf0
+              @acia.poke(addr, value) if low < 0xf4
+            elsif low >= 0xe0
+              @dongle.poke(addr, value) if low < 0xe4
+            end
+          end
+        end
+
+        attr_reader :cells, :bank_latch, :system_latch, :cpu_switch, :ram_switch
+
+        # Bit 0 of $EFFE: 1 for the ROM socket at $9000.
+        attr_reader :socket
+
+        # +bus+ is the PET's, whose pages the board maps, and
+        # +keyboard_ports+ PIA 1's, whose PA7 the diagnostic sense is.
+        # +cpu_switch+ and +ram_switch+ are SW2's and SW1's positions, one
+        # of CPU_SWITCH's and RAM_SWITCH's, and +refresh_hz+ picks the
+        # Waterloo $E000 ROM, 50 or 60.
+        def initialize(bus, dongle:, acia:, keyboard_ports:, cpu_switch: "6502", ram_switch: "rw",
+                       refresh_hz: 50)
+          raise ArgumentError, "the CPU switch has no position #{cpu_switch}" unless CPU_SWITCH.include?(cpu_switch)
+          raise ArgumentError, "the RAM switch has no position #{ram_switch}" unless RAM_SWITCH.include?(ram_switch)
+
+          @bus = bus
+          @dongle = dongle
+          @keyboard_ports = keyboard_ports
+          @cpu_switch = cpu_switch
+          @ram_switch = ram_switch
+          @cells = Array.new(0x10000, 0)
+          @banks = Array.new(16) { |bank| Bus::Expansion::Window.new(@cells, bank << 12, 0x9000) }
+          @io = IOPage.new(self, bus, dongle, acia)
+          @bank_latch = 0
+          @system_latch = 0
+          @socket = 0
+          @rom_a = ROM.load("pet/superpet-a000.rom", 0xa000)
+          @rom_c = ROM.load("pet/superpet-c000.rom", 0xc000)
+          @rom_e = ROM.load(refresh_hz == 50 ? "pet/superpet-e000-50hz.rom" : "pet/superpet-e000.rom", 0xe000)
+          @m6809 = m6809_selected?
+          @select_handler = nil
+        end
+
+        # Calls the block when the CPU the switch and the system latch pick
+        # changes.
+        def on_select(&handler)
+          @select_handler = handler
+        end
+
+        # Whether the 6809 has the bus.
+        def m6809? = @m6809
+
+        def bank = @bank_latch & 0x0f
+
+        def bank_latch=(value)
+          @bank_latch = value
+          @bus.map_pages
+        end
+
+        def system_latch=(value)
+          return if @bank_latch.nobits?(0x80)
+
+          @system_latch = value
+          @keyboard_ports.diagnostic_low = value.anybits?(0x08)
+          select
+        end
+
+        def socket=(value)
+          @socket = @m6809 ? 0 : value & 0x01
+          @bus.map_pages
+        end
+
+        # Moves SW2, which picks the CPU at the next RES.
+        def cpu_switch=(position)
+          raise ArgumentError, "the CPU switch has no position #{position}" unless CPU_SWITCH.include?(position)
+
+          @cpu_switch = position
+        end
+
+        # Moves SW1, which protects the bank RAM from the next write on.
+        def ram_switch=(position)
+          raise ArgumentError, "the RAM switch has no position #{position}" unless RAM_SWITCH.include?(position)
+
+          @ram_switch = position
+          @bus.map_pages
+        end
+
+        # Whether writes to the bank RAM go nowhere.
+        def write_protected?
+          case @ram_switch
+          when "read" then true
+          when "rw" then false
+          else @system_latch.nobits?(0x02)
+          end
+        end
+
+        # Whether the CPU switch, or the system latch with it at PROG,
+        # picks the 6809.
+        def m6809_selected?
+          case @cpu_switch
+          when "6502" then false
+          when "6809" then true
+          else @system_latch.nobits?(0x01)
+          end
+        end
+
+        # The RES line clears the latches, and the 6702.
+        def reset!
+          @bank_latch = 0
+          @system_latch = 0
+          @socket = 0
+          @keyboard_ports.diagnostic_low = false
+          @dongle.reset!
+          select
+        end
+
+        def power_on!
+          @cells.fill(0)
+        end
+
+        # Lays the bank, or the empty socket, over $9000-$9FFF, the I/O
+        # page over $EF00, and the Waterloo ROMs over the 8032's while the
+        # 6809 runs.
+        def map(reads, writes)
+          if @socket.zero?
+            window = @banks[bank]
+            window.read_only = write_protected?
+            reads.fill(window, 0x90, 0x10)
+            writes.fill(window, 0x90, 0x10)
+          else
+            reads.fill(@bus.open_bus, 0x90, 0x10)
+            writes.fill(@bus.open_bus, 0x90, 0x10)
+          end
+          reads[0xef] = @io
+          writes[0xef] = @io
+          map_waterloo(reads) if @m6809
+        end
+
+        private
+
+        # Picks the CPU again, and hands the bus over if that changed it.
+        # The 6809 taking over clears the socket bit.
+        def select
+          m6809 = m6809_selected?
+          changed = m6809 != @m6809
+          @m6809 = m6809
+          @socket = 0 if m6809
+          @bus.map_pages
+          @select_handler&.call if changed
+        end
+
+        def map_waterloo(reads)
+          reads.fill(@rom_a, 0xa0, 0x20)
+          reads.fill(@rom_c, 0xc0, 0x20)
+          reads.fill(@rom_e, 0xe0, 0x08)
+          reads.fill(@rom_e, 0xf0, 0x10)
+        end
+      end
+    end
+  end
+end

data/lib/badline/pet/superpet/dongle.rb

@@ -0,0 +1,81 @@
+# frozen_string_literal: true
+
+module Badline
+  class PET
+    class SuperPET < PET
+      # The 6702 at $EFE0-$EFE3, the protection chip the Waterloo languages
+      # check for. Its behaviour comes from David Roberts' Visual 6702, a
+      # switch-level simulation of the decapped chip's netlist, driven a
+      # bus cycle at a time.
+      #
+      # Each data line has a shift register of its own, LENGTHS long, whose
+      # first stage the line reads, inverted where INVERTED has the bit
+      # set. A latch keeps the last byte written, all ones from the RES
+      # line. A write that sets D0 where the last one left it clear shifts
+      # every register one stage at the end of the next cycle, whichever
+      # cycle that is, so a read in it still finds the old byte. Each
+      # register takes in its first stage XORed with the latch's bit,
+      # inverted where FEEDBACK has the bit clear, the latch as that cycle
+      # leaves it. The RES line clears the registers.
+      class Dongle
+        LENGTHS = [6, 3, 7, 8, 1, 3, 5, 2].freeze
+
+        INVERTED = 0xd6
+
+        FEEDBACK = 0x29
+
+        # No shift waiting.
+        NONE = -1
+
+        # The registers, bit 0 of each the stage its line reads, the latch,
+        # and the cycle at whose end the registers shift, or NONE.
+        attr_reader :registers, :latch, :shift_at
+
+        # +clock+ answers #cycles, the cycle the CPU's access falls in.
+        def initialize(clock)
+          @clock = clock
+          @registers = Array.new(8, 0)
+          reset!
+        end
+
+        def reset!
+          @registers.fill(0)
+          @latch = 0xff
+          @shift_at = NONE
+        end
+
+        def peek(_addr)
+          now = @clock.cycles
+          shift if @shift_at != NONE && @shift_at < now
+          value = 0
+          8.times { |bit| value |= (@registers[bit] & 1) << bit }
+          value ^ INVERTED
+        end
+
+        def poke(_addr, value)
+          now = @clock.cycles
+          shift if @shift_at != NONE && @shift_at < now
+          raising = value.anybits?(0x01) && @latch.nobits?(0x01)
+          @latch = value
+          if @shift_at == now
+            shift
+          elsif raising
+            @shift_at = now + 1
+          end
+        end
+
+        private
+
+        def shift
+          @shift_at = NONE
+          incoming = @latch ^ FEEDBACK ^ 0xff
+          8.times do |bit|
+            register = @registers[bit]
+            stage = (register ^ (incoming >> bit)) & 1
+            @registers[bit] = (register >> 1) | (stage << (LENGTHS[bit] - 1))
+          end
+        end
+      end
+    end
+  end
+end