axi_tdl 0.2.7 → 0.2.10
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- checksums.yaml +4 -4
- data/.github/workflows/gem-push.yml +21 -48
- data/lib/axi_tdl/version.rb +1 -1
- metadata +6 -429
- data/lib/axi/xilinx_clock_reset/xilinx_preclock_block.sv +0 -49
- data/lib/axi/xilinx_clock_reset/xilinx_reset_sync.v +0 -91
- data/lib/axi/xilinx_clock_reset/xilinx_reset_sync_A1.sv +0 -112
- data/lib/axi/xilinx_clock_reset/xilinx_share_reset.sv +0 -123
- data/lib/axi/xilinx_clock_reset/xilinx_sync_block.v +0 -90
- data/lib/tdl/auto_script/tmp/MAC_FCS_sdl.rb +0 -13
- data/lib/tdl/auto_script/tmp/TPU_reprogram_wrapper_verb_sdl.rb +0 -16
- data/lib/tdl/auto_script/tmp/adc_1015_tpu_array_B1_sdl.rb +0 -20
- data/lib/tdl/auto_script/tmp/adc_1015_tpu_array_gray_sdl.rb +0 -19
- data/lib/tdl/auto_script/tmp/adc_1015_tpu_array_sdl.rb +0 -19
- data/lib/tdl/auto_script/tmp/adc_1015_tpu_array_verb_sdl.rb +0 -19
- data/lib/tdl/auto_script/tmp/adc_1015_tpu_array_verc_diffr_pca9557_sdl.rb +0 -18
- data/lib/tdl/auto_script/tmp/adc_1015_tpu_array_verc_diffr_sdl.rb +0 -19
- data/lib/tdl/auto_script/tmp/adc_1015_tpu_array_verc_sdl.rb +0 -19
- data/lib/tdl/auto_script/tmp/adc_1015_tpu_array_x7_gray_sdl.rb +0 -19
- data/lib/tdl/auto_script/tmp/adc_1015_tpu_wrapper_sdl.rb +0 -20
- data/lib/tdl/auto_script/tmp/aec_alarm_check_A1_sdl.rb +0 -14
- data/lib/tdl/auto_script/tmp/aec_alarm_check_A2_sdl.rb +0 -14
- data/lib/tdl/auto_script/tmp/aec_alarm_check_A3_sdl.rb +0 -14
- data/lib/tdl/auto_script/tmp/aec_alarm_check_A4_sdl.rb +0 -14
- data/lib/tdl/auto_script/tmp/aec_alarm_check_A5_sdl.rb +0 -14
- data/lib/tdl/auto_script/tmp/aec_alarm_check_A6_sdl.rb +0 -14
- data/lib/tdl/auto_script/tmp/arp_tpu_wrapper_sdl.rb +0 -16
- data/lib/tdl/auto_script/tmp/axi4_combin_wr_rd_batch_sdl.rb +0 -11
- data/lib/tdl/auto_script/tmp/axi4_data_convert_verb_sdl.rb +0 -12
- data/lib/tdl/auto_script/tmp/axi4_direct_A1_sdl.rb +0 -15
- data/lib/tdl/auto_script/tmp/axi4_direct_B1_sdl.rb +0 -10
- data/lib/tdl/auto_script/tmp/axi4_direct_algin_addr_step_sdl.rb +0 -20
- data/lib/tdl/auto_script/tmp/axi4_direct_verc_sdl.rb +0 -17
- data/lib/tdl/auto_script/tmp/axi4_long_to_axi4_wide_B1_sdl.rb +0 -16
- data/lib/tdl/auto_script/tmp/axi4_packet_fifo_B1_sdl.rb +0 -16
- data/lib/tdl/auto_script/tmp/axi4_partition_OD_sdl.rb +0 -13
- data/lib/tdl/auto_script/tmp/axi4_partition_wr_OD_sdl.rb +0 -12
- data/lib/tdl/auto_script/tmp/axi4_ps_convert_sdl.rb +0 -12
- data/lib/tdl/auto_script/tmp/axi4_rd_mix_interconnect_M2S_A1_sdl.rb +0 -11
- data/lib/tdl/auto_script/tmp/axi4_rd_mix_interconnect_M2S_A2_sdl.rb +0 -12
- data/lib/tdl/auto_script/tmp/axi4_to_native_for_ddr_ip_C1_sdl.rb +0 -24
- data/lib/tdl/auto_script/tmp/axi4_wr_auxiliary_gen_sdl.rb +0 -11
- data/lib/tdl/auto_script/tmp/axi4_wr_auxiliary_gen_without_resp_sdl.rb +0 -11
- data/lib/tdl/auto_script/tmp/axi4_wr_interconnect_M2S_A1_sdl.rb +0 -11
- data/lib/tdl/auto_script/tmp/axi4_wr_pipe_sdl.rb +0 -10
- data/lib/tdl/auto_script/tmp/axi_stream_cache_35bit_sdl.rb +0 -10
- data/lib/tdl/auto_script/tmp/axi_stream_cache_36_71bit_sdl.rb +0 -10
- data/lib/tdl/auto_script/tmp/axi_stream_cache_A1_sdl.rb +0 -11
- data/lib/tdl/auto_script/tmp/axi_stream_cache_compact_verb_sdl.rb +0 -10
- data/lib/tdl/auto_script/tmp/axi_stream_cache_sdl.rb +0 -10
- data/lib/tdl/auto_script/tmp/axi_stream_cache_verb_sdl.rb +0 -10
- data/lib/tdl/auto_script/tmp/axi_stream_interconnect_M2S_A1_sdl.rb +0 -12
- data/lib/tdl/auto_script/tmp/axi_stream_interconnect_S2M_auto_sdl.rb +0 -12
- data/lib/tdl/auto_script/tmp/axi_stream_interconnect_S2M_sdl.rb +0 -13
- data/lib/tdl/auto_script/tmp/axi_stream_long_cache_sdl.rb +0 -11
- data/lib/tdl/auto_script/tmp/axi_stream_long_fifo_sdl.rb +0 -12
- data/lib/tdl/auto_script/tmp/axi_stream_long_fifo_verb_sdl.rb +0 -12
- data/lib/tdl/auto_script/tmp/axi_stream_packet_fifo_sdl.rb +0 -11
- data/lib/tdl/auto_script/tmp/axi_stream_packet_fifo_with_info_sdl.rb +0 -14
- data/lib/tdl/auto_script/tmp/axi_stream_packet_long_fifo_A1_sdl.rb +0 -14
- data/lib/tdl/auto_script/tmp/axi_stream_packet_long_fifo_sdl.rb +0 -13
- data/lib/tdl/auto_script/tmp/axi_stream_planer_sdl.rb +0 -15
- data/lib/tdl/auto_script/tmp/axi_stream_to_axi4_wr_sdl.rb +0 -10
- data/lib/tdl/auto_script/tmp/axi_stream_wide_fifo_sdl.rb +0 -11
- data/lib/tdl/auto_script/tmp/axi_streams_combin_A1_sdl.rb +0 -16
- data/lib/tdl/auto_script/tmp/axi_streams_scaler_A1_sdl.rb +0 -15
- data/lib/tdl/auto_script/tmp/axis_append_A1_sdl.rb +0 -19
- data/lib/tdl/auto_script/tmp/axis_connect_pipe_right_shift_sdl.rb +0 -11
- data/lib/tdl/auto_script/tmp/axis_connect_pipe_right_shift_verb_sdl.rb +0 -13
- data/lib/tdl/auto_script/tmp/axis_connect_pipe_sdl.rb +0 -10
- data/lib/tdl/auto_script/tmp/axis_connect_pipe_with_info_sdl.rb +0 -13
- data/lib/tdl/auto_script/tmp/axis_direct_A1_sdl.rb +0 -12
- data/lib/tdl/auto_script/tmp/axis_direct_sdl.rb +0 -10
- data/lib/tdl/auto_script/tmp/axis_ex_status_sdl.rb +0 -13
- data/lib/tdl/auto_script/tmp/axis_head_cut_sdl.rb +0 -11
- data/lib/tdl/auto_script/tmp/axis_head_cut_verb_sdl.rb +0 -11
- data/lib/tdl/auto_script/tmp/axis_intc_S2M_with_addr_inf_sdl.rb +0 -13
- data/lib/tdl/auto_script/tmp/axis_length_cut_sdl.rb +0 -11
- data/lib/tdl/auto_script/tmp/axis_length_fill_sdl.rb +0 -11
- data/lib/tdl/auto_script/tmp/axis_length_fill_verb_sdl.rb +0 -13
- data/lib/tdl/auto_script/tmp/axis_length_split_sdl.rb +0 -11
- data/lib/tdl/auto_script/tmp/axis_length_split_with_addr_sdl.rb +0 -14
- data/lib/tdl/auto_script/tmp/axis_length_split_with_user_sdl.rb +0 -11
- data/lib/tdl/auto_script/tmp/axis_master_empty_sdl.rb +0 -9
- data/lib/tdl/auto_script/tmp/axis_mirror_to_master_sdl.rb +0 -11
- data/lib/tdl/auto_script/tmp/axis_pkt_fifo_filter_keep_A1_sdl.rb +0 -11
- data/lib/tdl/auto_script/tmp/axis_pkt_fifo_filter_keep_sdl.rb +0 -11
- data/lib/tdl/auto_script/tmp/axis_slaver_empty_sdl.rb +0 -9
- data/lib/tdl/auto_script/tmp/axis_slaver_pipe_A1_sdl.rb +0 -11
- data/lib/tdl/auto_script/tmp/axis_slaver_pipe_sdl.rb +0 -10
- data/lib/tdl/auto_script/tmp/axis_uncompress_A1_sdl.rb +0 -13
- data/lib/tdl/auto_script/tmp/axis_uncompress_verb_sdl.rb +0 -13
- data/lib/tdl/auto_script/tmp/axis_valve_sdl.rb +0 -11
- data/lib/tdl/auto_script/tmp/axis_valve_with_pipe_sdl.rb +0 -12
- data/lib/tdl/auto_script/tmp/axis_width_convert_sdl.rb +0 -10
- data/lib/tdl/auto_script/tmp/axis_width_convert_verb_sdl.rb +0 -12
- data/lib/tdl/auto_script/tmp/axis_width_destruct_sdl.rb +0 -10
- data/lib/tdl/auto_script/tmp/board_cs_ctrl_gray_sdl.rb +0 -14
- data/lib/tdl/auto_script/tmp/board_cs_ctrl_gray_x7_sdl.rb +0 -14
- data/lib/tdl/auto_script/tmp/broaden_and_cross_clk_sdl.rb +0 -17
- data/lib/tdl/auto_script/tmp/cbct_chip_reg_dport_wrapper_sdl.rb +0 -20
- data/lib/tdl/auto_script/tmp/cbct_chip_reg_wrapper_sdl.rb +0 -19
- data/lib/tdl/auto_script/tmp/cbct_iic_bus_tri_wrapper_sdl.rb +0 -18
- data/lib/tdl/auto_script/tmp/cbct_iic_bus_wrapper_sdl.rb +0 -14
- data/lib/tdl/auto_script/tmp/cbct_lock_lvds_data_sdl.rb +0 -16
- data/lib/tdl/auto_script/tmp/cbct_sensor_driver_array_sdl.rb +0 -12
- data/lib/tdl/auto_script/tmp/cbct_sensor_driver_clock_A1_sdl.rb +0 -13
- data/lib/tdl/auto_script/tmp/cbct_sensor_driver_clock_sdl.rb +0 -12
- data/lib/tdl/auto_script/tmp/cbct_single_sensor_lvds_dir_sdl.rb +0 -14
- data/lib/tdl/auto_script/tmp/chip_reg_tpu_phase_upgrade_sdl.rb +0 -25
- data/lib/tdl/auto_script/tmp/chip_reg_tpu_wrapper_gray_sdl.rb +0 -24
- data/lib/tdl/auto_script/tmp/chip_reg_tpu_wrapper_sdl.rb +0 -25
- data/lib/tdl/auto_script/tmp/chip_reg_tpu_wrapper_slot_gray_sdl.rb +0 -24
- data/lib/tdl/auto_script/tmp/chip_reg_tpu_wrapper_speci_gray_sdl.rb +0 -24
- data/lib/tdl/auto_script/tmp/chip_reg_tpu_wrapper_verb_sdl.rb +0 -24
- data/lib/tdl/auto_script/tmp/chip_reg_tpu_wrapper_x7_gray_sdl.rb +0 -24
- data/lib/tdl/auto_script/tmp/chip_spi_model_sdl.rb +0 -12
- data/lib/tdl/auto_script/tmp/clock_lvds_bitslip_sdl.rb +0 -13
- data/lib/tdl/auto_script/tmp/clock_manager_A2_sdl.rb +0 -25
- data/lib/tdl/auto_script/tmp/clock_manager_B2_sdl.rb +0 -26
- data/lib/tdl/auto_script/tmp/clock_manager_powerlow_sdl.rb +0 -22
- data/lib/tdl/auto_script/tmp/clock_manager_sdl.rb +0 -16
- data/lib/tdl/auto_script/tmp/clock_rst_verb_sdl.rb +0 -14
- data/lib/tdl/auto_script/tmp/clock_rst_verc_sdl.rb +0 -15
- data/lib/tdl/auto_script/tmp/cmos_redx_1xN_inner_clock_sdl.rb +0 -33
- data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0004.coe +0 -18
- data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0014.coe +0 -18
- data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0017.coe +0 -18
- data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0019.coe +0 -18
- data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0023.coe +0 -18
- data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0024.coe +0 -18
- data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0025.coe +0 -18
- data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0027.coe +0 -18
- data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0030.coe +0 -18
- data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0037.coe +0 -18
- data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0038.coe +0 -18
- data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0040.coe +0 -18
- data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0041.coe +0 -18
- data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0042.coe +0 -18
- data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0043.coe +0 -18
- data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0049.coe +0 -18
- data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0052.coe +0 -18
- data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0054.coe +0 -18
- data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0055.coe +0 -18
- data/lib/tdl/auto_script/tmp/coe_origin_mac_inf_x_0_R0000.coe +0 -9825
- data/lib/tdl/auto_script/tmp/coe_origin_mac_inf_x_1_R0001.coe +0 -9720
- data/lib/tdl/auto_script/tmp/coe_origin_mac_inf_x_2_R0002.coe +0 -9825
- data/lib/tdl/auto_script/tmp/coe_origin_mac_inf_x_3_R0003.coe +0 -9825
- data/lib/tdl/auto_script/tmp/coe_origin_mac_inf_x_R0000.coe +0 -26
- data/lib/tdl/auto_script/tmp/coe_uart_tx_inf_R0000.coe +0 -5025
- data/lib/tdl/auto_script/tmp/common_axli_flow_sdl.rb +0 -12
- data/lib/tdl/auto_script/tmp/common_fifo_sdl.rb +0 -22
- data/lib/tdl/auto_script/tmp/common_redx_1xN_ddr_simple_sdl.rb +0 -32
- data/lib/tdl/auto_script/tmp/common_redx_1xN_sdr_serdes_simple_sdl.rb +0 -31
- data/lib/tdl/auto_script/tmp/common_redx_1xN_sdr_simple_sdl.rb +0 -32
- data/lib/tdl/auto_script/tmp/cross_clk_sync_sdl.rb +0 -14
- data/lib/tdl/auto_script/tmp/custom_serdes_router_sdl.rb +0 -17
- data/lib/tdl/auto_script/tmp/data_c_cache_sdl.rb +0 -10
- data/lib/tdl/auto_script/tmp/data_c_direct_sdl.rb +0 -10
- data/lib/tdl/auto_script/tmp/data_c_pipe_force_vld_bind_data_sdl.rb +0 -14
- data/lib/tdl/auto_script/tmp/data_c_pipe_force_vld_sdl.rb +0 -10
- data/lib/tdl/auto_script/tmp/data_c_pipe_inf_sdl.rb +0 -10
- data/lib/tdl/auto_script/tmp/data_c_pipe_intc_M2S_best_robin_sdl.rb +0 -12
- data/lib/tdl/auto_script/tmp/data_c_pipe_sync_sdl.rb +0 -13
- data/lib/tdl/auto_script/tmp/data_c_sim_master_model_sdl.rb +0 -15
- data/lib/tdl/auto_script/tmp/data_inf_c_intc_S2M_sdl.rb +0 -13
- data/lib/tdl/auto_script/tmp/data_inf_c_planer_A1_sdl.rb +0 -15
- data/lib/tdl/auto_script/tmp/data_lvds_bitslip_sdl.rb +0 -12
- data/lib/tdl/auto_script/tmp/data_lvds_simple_bitslip_sdl.rb +0 -12
- data/lib/tdl/auto_script/tmp/data_mirrors_sdl.rb +0 -15
- data/lib/tdl/auto_script/tmp/datainf_c_slaver_empty_sdl.rb +0 -9
- data/lib/tdl/auto_script/tmp/ddr3_ip_wrapper_sdl.rb +0 -28
- data/lib/tdl/auto_script/tmp/ddr_axi4_to_axis_sdl.rb +0 -11
- data/lib/tdl/auto_script/tmp/det_moto_findex_sdl.rb +0 -13
- data/lib/tdl/auto_script/tmp/det_start_block_sdl.rb +0 -17
- data/lib/tdl/auto_script/tmp/det_start_filter_sdl.rb +0 -15
- data/lib/tdl/auto_script/tmp/det_with_pre_A3_sdl.rb +0 -28
- data/lib/tdl/auto_script/tmp/det_with_pre_A4_sdl.rb +0 -28
- data/lib/tdl/auto_script/tmp/det_with_pre_B1_sdl.rb +0 -29
- data/lib/tdl/auto_script/tmp/det_with_pre_findex_sdl.rb +0 -18
- data/lib/tdl/auto_script/tmp/det_with_pre_verb_sdl.rb +0 -29
- data/lib/tdl/auto_script/tmp/diffr_multi_phase_sample_sdl.rb +0 -17
- data/lib/tdl/auto_script/tmp/diffr_reg_tpu_v3_wrapper_sdl.rb +0 -17
- data/lib/tdl/auto_script/tmp/diffr_reg_tpu_wrapper_sdl.rb +0 -16
- data/lib/tdl/auto_script/tmp/diffr_reg_tpu_wrapper_v2_sdl.rb +0 -16
- data/lib/tdl/auto_script/tmp/dire_accese_flash_sdl.rb +0 -17
- data/lib/tdl/auto_script/tmp/dyn_edge_clock_sdl.rb +0 -15
- data/lib/tdl/auto_script/tmp/edge_generator_sdl.rb +0 -14
- data/lib/tdl/auto_script/tmp/eth4_chip_reg_wrapper_sdl.rb +0 -20
- data/lib/tdl/auto_script/tmp/eth4_lvds_tb_block_sdl.rb +0 -16
- data/lib/tdl/auto_script/tmp/eth4_sensor_driver_array_sdl.rb +0 -17
- data/lib/tdl/auto_script/tmp/eth4_single_chip_Red2S_lvds_dir_sdl.rb +0 -16
- data/lib/tdl/auto_script/tmp/eth_2g5_wrapper_sdl.rb +0 -25
- data/lib/tdl/auto_script/tmp/eth_outShare_wrapper_sdl.rb +0 -28
- data/lib/tdl/auto_script/tmp/eth_to_ddr_with_ack_sdl.rb +0 -13
- data/lib/tdl/auto_script/tmp/eth_to_spi_verb_sdl.rb +0 -20
- data/lib/tdl/auto_script/tmp/eth_to_standard_spi_with_ack_sdl.rb +0 -17
- data/lib/tdl/auto_script/tmp/eth_to_standard_uart_with_ack_sdl.rb +0 -16
- data/lib/tdl/auto_script/tmp/eth_xilinx_ip_sdl.rb +0 -22
- data/lib/tdl/auto_script/tmp/ethernet_wrapper_2d5G_sdl.rb +0 -28
- data/lib/tdl/auto_script/tmp/ethernet_wrapper_sdl.rb +0 -28
- data/lib/tdl/auto_script/tmp/ethernet_wrapper_track_sdl.rb +0 -28
- data/lib/tdl/auto_script/tmp/ext_sync_filter_sdl.rb +0 -14
- data/lib/tdl/auto_script/tmp/fifo_36kb_long_sdl.rb +0 -20
- data/lib/tdl/auto_script/tmp/fifo_73_96bit_sdl.rb +0 -19
- data/lib/tdl/auto_script/tmp/four_chips_Red5_lvds_dir_sdl.rb +0 -15
- data/lib/tdl/auto_script/tmp/four_chips_Red5_lvds_pins_delay_sdl.rb +0 -20
- data/lib/tdl/auto_script/tmp/full_axi4_to_axis_partition_wr_rd_sdl.rb +0 -12
- data/lib/tdl/auto_script/tmp/full_axi4_to_axis_sdl.rb +0 -11
- data/lib/tdl/auto_script/tmp/gen_big_field_table_sdl.rb +0 -15
- data/lib/tdl/auto_script/tmp/gen_common_frame_table_sdl.rb +0 -61
- data/lib/tdl/auto_script/tmp/gen_origin_axis_A2_sdl.rb +0 -14
- data/lib/tdl/auto_script/tmp/gen_origin_axis_A3_sdl.rb +0 -15
- data/lib/tdl/auto_script/tmp/gen_origin_axis_sdl.rb +0 -13
- data/lib/tdl/auto_script/tmp/general_tap_ack_A2_sdl.rb +0 -17
- data/lib/tdl/auto_script/tmp/general_tap_ack_A3_sdl.rb +0 -18
- data/lib/tdl/auto_script/tmp/general_tap_ack_A4_sdl.rb +0 -19
- data/lib/tdl/auto_script/tmp/general_tap_ack_sdl.rb +0 -16
- data/lib/tdl/auto_script/tmp/general_tap_no_ack_sdl.rb +0 -15
- data/lib/tdl/auto_script/tmp/general_tap_send_sdl.rb +0 -19
- data/lib/tdl/auto_script/tmp/gmii_from_mac_sdl.rb +0 -12
- data/lib/tdl/auto_script/tmp/gmii_to_mac_sdl.rb +0 -14
- data/lib/tdl/auto_script/tmp/gt_transceivers_axis_verb_sdl.rb +0 -22
- data/lib/tdl/auto_script/tmp/gt_tx_pack_proto_sdl.rb +0 -12
- data/lib/tdl/auto_script/tmp/gvi_k7_clock_manager_sdl.rb +0 -19
- data/lib/tdl/auto_script/tmp/gvi_k7_ddr3_ip_wrapper_sdl.rb +0 -29
- data/lib/tdl/auto_script/tmp/hardware_date_core_sdl.rb +0 -14
- data/lib/tdl/auto_script/tmp/hdl_test_sdl.rb +0 -13
- data/lib/tdl/auto_script/tmp/iic_gpio_pca9557_array_sdl.rb +0 -14
- data/lib/tdl/auto_script/tmp/independent_clock_fifo_a1_sdl.rb +0 -22
- data/lib/tdl/auto_script/tmp/independent_clock_fifo_sdl.rb +0 -21
- data/lib/tdl/auto_script/tmp/inf_time_delay_ctrl_sdl.rb +0 -10
- data/lib/tdl/auto_script/tmp/inf_time_delay_ctrl_verb_sdl.rb +0 -13
- data/lib/tdl/auto_script/tmp/init_10G_sdl.rb +0 -11
- data/lib/tdl/auto_script/tmp/init_mac_sdl.rb +0 -14
- data/lib/tdl/auto_script/tmp/init_trigger_cfg_10g_sdl.rb +0 -11
- data/lib/tdl/auto_script/tmp/inner_clock_to_sensor_sdl.rb +0 -13
- data/lib/tdl/auto_script/tmp/ip_check_sum_sdl.rb +0 -22
- data/lib/tdl/auto_script/tmp/k7_ethernet_10g_wrapper_B2_sdl.rb +0 -24
- data/lib/tdl/auto_script/tmp/k7_ethernet_multi_10g_wrapper_sdl.rb +0 -23
- data/lib/tdl/auto_script/tmp/keys_filter_sdl.rb +0 -14
- data/lib/tdl/auto_script/tmp/latency_dynamic_sdl.rb +0 -14
- data/lib/tdl/auto_script/tmp/latency_sdl.rb +0 -14
- data/lib/tdl/auto_script/tmp/lock_lvds_data_sdl.rb +0 -19
- data/lib/tdl/auto_script/tmp/lvds2cmos_sdl.rb +0 -11
- data/lib/tdl/auto_script/tmp/lvds_ibufds_array_NOBUFF_sdl.rb +0 -15
- data/lib/tdl/auto_script/tmp/lvds_ibufds_array_r8_1x6_NOBUFF_sdl.rb +0 -16
- data/lib/tdl/auto_script/tmp/lvds_ibufds_array_r8_1x6_OB_sdl.rb +0 -19
- data/lib/tdl/auto_script/tmp/lvds_ibufds_array_sdl.rb +0 -15
- data/lib/tdl/auto_script/tmp/lvds_tb_block_A1_sdl.rb +0 -16
- data/lib/tdl/auto_script/tmp/mac_to_file_sdl.rb +0 -11
- data/lib/tdl/auto_script/tmp/manchester_router_sdl.rb +0 -13
- data/lib/tdl/auto_script/tmp/mdio_model_sdl.rb +0 -11
- data/lib/tdl/auto_script/tmp/mdio_proto_sdl.rb +0 -24
- data/lib/tdl/auto_script/tmp/mirror_mac_arp_iic_sdl.rb +0 -10
- data/lib/tdl/auto_script/tmp/modified_eth_2G5_top_sdl.rb +0 -16
- data/lib/tdl/auto_script/tmp/multiple_steps_676_sdl.rb +0 -15
- data/lib/tdl/auto_script/tmp/multiple_steps_A2_sdl.rb +0 -15
- data/lib/tdl/auto_script/tmp/odata_pool_axi4_A2_sdl.rb +0 -11
- data/lib/tdl/auto_script/tmp/odata_pool_axi4_A3_sdl.rb +0 -14
- data/lib/tdl/auto_script/tmp/outSt_combin_spi_core_sdl.rb +0 -22
- data/lib/tdl/auto_script/tmp/outSt_eth_to_ct_databoard_sdl.rb +0 -13
- data/lib/tdl/auto_script/tmp/outSt_eth_to_multi_spi_with_ack_sdl.rb +0 -19
- data/lib/tdl/auto_script/tmp/outSt_eth_to_spi_sdl.rb +0 -20
- data/lib/tdl/auto_script/tmp/outSt_eth_to_spi_verb_sdl.rb +0 -17
- data/lib/tdl/auto_script/tmp/outSt_eth_to_spi_with_ack_sdl.rb +0 -17
- data/lib/tdl/auto_script/tmp/outSt_spi_core_B1_sdl.rb +0 -21
- data/lib/tdl/auto_script/tmp/pack_ip_mac_B1_sdl.rb +0 -15
- data/lib/tdl/auto_script/tmp/pack_ip_mac_verb_sdl.rb +0 -15
- data/lib/tdl/auto_script/tmp/parse_big_field_table_A2_sdl.rb +0 -19
- data/lib/tdl/auto_script/tmp/parse_big_field_table_main_sdl.rb +0 -15
- data/lib/tdl/auto_script/tmp/parse_big_field_table_mirror_sdl.rb +0 -14
- data/lib/tdl/auto_script/tmp/parse_big_field_table_sdl.rb +0 -18
- data/lib/tdl/auto_script/tmp/parse_big_field_table_slaver_sdl.rb +0 -17
- data/lib/tdl/auto_script/tmp/parse_big_field_table_verb_sdl.rb +0 -17
- data/lib/tdl/auto_script/tmp/parse_common_frame_table_A1_sdl.rb +0 -64
- data/lib/tdl/auto_script/tmp/parse_tap_stream_sdl.rb +0 -10
- data/lib/tdl/auto_script/tmp/phase_red8_sensor_lvds_block_red8_sdl.rb +0 -22
- data/lib/tdl/auto_script/tmp/phase_sensor_sync_ctrl_sdl.rb +0 -17
- data/lib/tdl/auto_script/tmp/platform_shift_ctrl_verb_sdl.rb +0 -22
- data/lib/tdl/auto_script/tmp/poll_udp_tpu_upgrade_sdl.rb +0 -30
- data/lib/tdl/auto_script/tmp/poll_udp_tpu_verb_upgrade_sdl.rb +0 -34
- data/lib/tdl/auto_script/tmp/prim_serdes_filter_decode_sdl.rb +0 -14
- data/lib/tdl/auto_script/tmp/red2s_lock_lvds_data_verc_sdl.rb +0 -20
- data/lib/tdl/auto_script/tmp/red3_lock_lvds_data_verc_sdl.rb +0 -18
- data/lib/tdl/auto_script/tmp/red3_lvds_tb_block_A1_sdl.rb +0 -16
- data/lib/tdl/auto_script/tmp/red5_chip_reg_wrapper_A1_sdl.rb +0 -20
- data/lib/tdl/auto_script/tmp/red5_chip_reg_wrapper_A2_sdl.rb +0 -21
- data/lib/tdl/auto_script/tmp/red5_chip_reg_wrapper_sdl.rb +0 -19
- data/lib/tdl/auto_script/tmp/red5_lock_lvds_data_raw_A1_sdl.rb +0 -20
- data/lib/tdl/auto_script/tmp/red5_lock_lvds_data_sdl.rb +0 -18
- data/lib/tdl/auto_script/tmp/red5_lock_lvds_data_verb_sdl.rb +0 -18
- data/lib/tdl/auto_script/tmp/red5_lock_lvds_data_verc_sdl.rb +0 -22
- data/lib/tdl/auto_script/tmp/red5_lvds_clock_mmcm_sdl.rb +0 -12
- data/lib/tdl/auto_script/tmp/red8_1x6_oneBoard_sdl.rb +0 -30
- data/lib/tdl/auto_script/tmp/red8_chip_reg_wrapper_A2_sdl.rb +0 -21
- data/lib/tdl/auto_script/tmp/redx_1xN_ddr_inner_clock_sdl.rb +0 -36
- data/lib/tdl/auto_script/tmp/redx_1xN_ddr_inner_clock_verb_sdl.rb +0 -38
- data/lib/tdl/auto_script/tmp/redx_1xN_ddr_serdes_manual_A1_sdl.rb +0 -38
- data/lib/tdl/auto_script/tmp/redx_1xN_ddr_serdes_manual_A2_sdl.rb +0 -39
- data/lib/tdl/auto_script/tmp/redx_1xN_ddr_serdes_manual_sdl.rb +0 -35
- data/lib/tdl/auto_script/tmp/redx_1xN_inner_clock_sdl.rb +0 -36
- data/lib/tdl/auto_script/tmp/redx_1xN_sdr_serdes_manual_A1_sdl.rb +0 -36
- data/lib/tdl/auto_script/tmp/redx_lock_lvds_data_2B_sdl.rb +0 -25
- data/lib/tdl/auto_script/tmp/redx_lock_lvds_data_4B_bitslip_sdl.rb +0 -26
- data/lib/tdl/auto_script/tmp/redx_lock_lvds_data_4B_sdl.rb +0 -25
- data/lib/tdl/auto_script/tmp/redx_lock_lvds_data_4B_verb_sdl.rb +0 -25
- data/lib/tdl/auto_script/tmp/redx_lock_lvds_data_dyn_compact_sdl.rb +0 -26
- data/lib/tdl/auto_script/tmp/redx_lock_lvds_data_dyn_sdl.rb +0 -26
- data/lib/tdl/auto_script/tmp/redx_lock_lvds_data_raw_sdl.rb +0 -21
- data/lib/tdl/auto_script/tmp/redx_lock_lvds_data_raw_verb_sdl.rb +0 -22
- data/lib/tdl/auto_script/tmp/redx_lock_lvds_data_sdl.rb +0 -22
- data/lib/tdl/auto_script/tmp/redx_lock_lvds_data_verb_sdl.rb +0 -23
- data/lib/tdl/auto_script/tmp/redx_lvds_dir_to_4B_sdl.rb +0 -21
- data/lib/tdl/auto_script/tmp/redx_lvds_dir_to_4B_var_delay_multi_phase_DDR_sdl.rb +0 -29
- data/lib/tdl/auto_script/tmp/redx_lvds_dir_to_4B_var_delay_multi_phase_sdl.rb +0 -28
- data/lib/tdl/auto_script/tmp/redx_lvds_dir_to_4B_var_delay_sdl.rb +0 -23
- data/lib/tdl/auto_script/tmp/rgmii_to_gmii_wrapper_sdl.rb +0 -17
- data/lib/tdl/auto_script/tmp/riffa_trans_axis_sdl.rb +0 -22
- data/lib/tdl/auto_script/tmp/sct_ddr3_16bit_ip_wrapper_sdl.rb +0 -28
- data/lib/tdl/auto_script/tmp/sct_ddr3_ip_wrapper_sdl.rb +0 -29
- data/lib/tdl/auto_script/tmp/sel_system_ip_mac_sdl.rb +0 -15
- data/lib/tdl/auto_script/tmp/senser_lvds_parse_16bit_diffr_sdl.rb +0 -16
- data/lib/tdl/auto_script/tmp/senser_lvds_parse_24bit_diffr_A1_sdl.rb +0 -16
- data/lib/tdl/auto_script/tmp/senser_lvds_parse_24bit_diffr_sdl.rb +0 -15
- data/lib/tdl/auto_script/tmp/sensor_block_unit_C2_sdl.rb +0 -29
- data/lib/tdl/auto_script/tmp/sensor_block_unit_C2_track_crc8_sdl.rb +0 -29
- data/lib/tdl/auto_script/tmp/sensor_clock_recv_check_sdl.rb +0 -11
- data/lib/tdl/auto_script/tmp/sensor_ctrl_676_28lvds_sdl.rb +0 -18
- data/lib/tdl/auto_script/tmp/sensor_ctrl_676_sdl.rb +0 -17
- data/lib/tdl/auto_script/tmp/sensor_drive_lvds_clk_SP_sdl.rb +0 -15
- data/lib/tdl/auto_script/tmp/sensor_drive_lvds_clk_sdl.rb +0 -17
- data/lib/tdl/auto_script/tmp/sensor_drive_lvds_clk_verb_sdl.rb +0 -18
- data/lib/tdl/auto_script/tmp/sensor_driver_clock_set_A2_sdl.rb +0 -13
- data/lib/tdl/auto_script/tmp/sensor_lvds_block_unit_28lvds_findex_SP_sdl.rb +0 -23
- data/lib/tdl/auto_script/tmp/sensor_lvds_block_unit_28lvds_findex_edge_sync_sdl.rb +0 -23
- data/lib/tdl/auto_script/tmp/sensor_lvds_block_unit_28lvds_findex_sdl.rb +0 -23
- data/lib/tdl/auto_script/tmp/sensor_lvds_block_unit_28lvds_findex_verb_sdl.rb +0 -23
- data/lib/tdl/auto_script/tmp/sensor_lvds_block_unit_28lvds_sdl.rb +0 -21
- data/lib/tdl/auto_script/tmp/sensor_lvds_block_unit_findex_sdl.rb +0 -23
- data/lib/tdl/auto_script/tmp/sensor_lvds_block_unit_findex_verb_A1_sdl.rb +0 -23
- data/lib/tdl/auto_script/tmp/sensor_lvds_block_unit_findex_verb_red450_sdl.rb +0 -22
- data/lib/tdl/auto_script/tmp/sensor_lvds_block_unit_findex_verb_sdl.rb +0 -23
- data/lib/tdl/auto_script/tmp/sensor_lvds_block_unit_findex_verc_red450_sdl.rb +0 -22
- data/lib/tdl/auto_script/tmp/sensor_lvds_block_unit_findex_verc_sdl.rb +0 -22
- data/lib/tdl/auto_script/tmp/sensor_lvds_block_unit_sdl.rb +0 -21
- data/lib/tdl/auto_script/tmp/serdes_parl_lock_sdl.rb +0 -18
- data/lib/tdl/auto_script/tmp/serdes_to_data_array_sdl.rb +0 -19
- data/lib/tdl/auto_script/tmp/sim_arp_tpu_sdl.rb +0 -17
- data/lib/tdl/auto_script/tmp/sim_auto_wireshark_send_sdl.rb +0 -14
- data/lib/tdl/auto_script/tmp/sim_tpu_update_file_sdl.rb +0 -13
- data/lib/tdl/auto_script/tmp/simple_cbct_lock_lvds_data_sdl.rb +0 -16
- data/lib/tdl/auto_script/tmp/simple_hardware_log_track_sdl.rb +0 -14
- data/lib/tdl/auto_script/tmp/simple_hw_test_top_sdl.rb +0 -19
- data/lib/tdl/auto_script/tmp/simple_test_eth_2g5_subs_sdl.rb +0 -18
- data/lib/tdl/auto_script/tmp/single_chip_Red2S_lvds_dir_sdl.rb +0 -15
- data/lib/tdl/auto_script/tmp/single_chip_Red3_lvds_pins_delay_sdl.rb +0 -17
- data/lib/tdl/auto_script/tmp/single_chip_iic_bus_verb_wrapper_sdl.rb +0 -14
- data/lib/tdl/auto_script/tmp/single_chip_iic_bus_verc_wrapper_sdl.rb +0 -15
- data/lib/tdl/auto_script/tmp/single_chip_iic_bus_verd_wrapper_sdl.rb +0 -15
- data/lib/tdl/auto_script/tmp/single_chip_iic_bus_wrapper_sdl.rb +0 -14
- data/lib/tdl/auto_script/tmp/single_chip_lvds_ddr_dir_sdl.rb +0 -18
- data/lib/tdl/auto_script/tmp/single_chip_lvds_dir_delay_sdl.rb +0 -19
- data/lib/tdl/auto_script/tmp/single_chip_lvds_dir_inner_sdl.rb +0 -17
- data/lib/tdl/auto_script/tmp/single_chip_sensor_lvds_dir_sdl.rb +0 -15
- data/lib/tdl/auto_script/tmp/sketch_to_origin_stream_sdl.rb +0 -13
- data/lib/tdl/auto_script/tmp/slow_lvds_data_d2s_sdl.rb +0 -13
- data/lib/tdl/auto_script/tmp/slow_sensor_inner_clock_sdl.rb +0 -18
- data/lib/tdl/auto_script/tmp/split_ddr3_ip_wrapper_sdl.rb +0 -45
- data/lib/tdl/auto_script/tmp/tcp_aux_tpu_upgrade_sdl.rb +0 -50
- data/lib/tdl/auto_script/tmp/tcp_check_sum_sdl.rb +0 -15
- data/lib/tdl/auto_script/tmp/tcp_ctrl_set_sdl.rb +0 -13
- data/lib/tdl/auto_script/tmp/tcp_option_split_B1_sdl.rb +0 -10
- data/lib/tdl/auto_script/tmp/test_red5dl_lvds_sdl.rb +0 -9
- data/lib/tdl/auto_script/tmp/time_delay_ctrl_sdl.rb +0 -13
- data/lib/tdl/auto_script/tmp/time_enable_scaler_sdl.rb +0 -12
- data/lib/tdl/auto_script/tmp/time_step_module_A1_sdl.rb +0 -14
- data/lib/tdl/auto_script/tmp/time_step_module_sdl.rb +0 -13
- data/lib/tdl/auto_script/tmp/tpu_bypass_iic_upgrade_sdl.rb +0 -29
- data/lib/tdl/auto_script/tmp/tpu_common_iic_upgrade_sdl.rb +0 -25
- data/lib/tdl/auto_script/tmp/tpu_custom_iic_bus_C1_wrapper_gray_sdl.rb +0 -19
- data/lib/tdl/auto_script/tmp/tpu_custom_iic_bus_C1_wrapper_sdl.rb +0 -20
- data/lib/tdl/auto_script/tmp/tpu_custom_iic_bus_C1_wrapper_verb_sdl.rb +0 -19
- data/lib/tdl/auto_script/tmp/tpu_custom_iic_bus_C1_wrapper_x7_gray_sdl.rb +0 -19
- data/lib/tdl/auto_script/tmp/tpu_custom_iic_bus_verc_v2_array_sdl.rb +0 -15
- data/lib/tdl/auto_script/tmp/tpu_custom_iic_bus_verc_v3_wrapper_sdl.rb +0 -17
- data/lib/tdl/auto_script/tmp/tpu_custom_iic_bus_verc_v4_wrapper_sdl.rb +0 -19
- data/lib/tdl/auto_script/tmp/tpu_custom_iic_bus_verc_v5_wrapper_sdl.rb +0 -20
- data/lib/tdl/auto_script/tmp/tpu_custom_iic_bus_verc_wrapper_sdl.rb +0 -20
- data/lib/tdl/auto_script/tmp/tpu_eth4_iic_bus_wrapper_sdl.rb +0 -15
- data/lib/tdl/auto_script/tmp/tpu_mgm_inf_sdl.rb +0 -28
- data/lib/tdl/auto_script/tmp/tpu_simple_boot_sdl.rb +0 -12
- data/lib/tdl/auto_script/tmp/trigger_data_inf_c_A1_sdl.rb +0 -12
- data/lib/tdl/auto_script/tmp/trigger_data_inf_c_sdl.rb +0 -12
- data/lib/tdl/auto_script/tmp/uart_hp_ddr3_tft800x480_hdmi_ext_sdl.rb +0 -43
- data/lib/tdl/auto_script/tmp/uart_hp_ddr3_tft800x480_hdmi_ext_sim_sdl.rb +0 -43
- data/lib/tdl/auto_script/tmp/uart_rx_core_dma_verb_sdl.rb +0 -13
- data/lib/tdl/auto_script/tmp/uart_top_bypass_sdl.rb +0 -21
- data/lib/tdl/auto_script/tmp/uart_top_sdl.rb +0 -21
- data/lib/tdl/auto_script/tmp/udp_check_sum_sdl.rb +0 -15
- data/lib/tdl/auto_script/tmp/udp_ctrl_set_A1_sdl.rb +0 -18
- data/lib/tdl/auto_script/tmp/udp_fpga_ports_route_sdl.rb +0 -12
- data/lib/tdl/auto_script/tmp/udp_socket_ddr_pump_64b_sdl.rb +0 -16
- data/lib/tdl/auto_script/tmp/udp_socket_ddr_pump_A3_sdl.rb +0 -14
- data/lib/tdl/auto_script/tmp/udp_socket_ddr_pump_B1_sdl.rb +0 -14
- data/lib/tdl/auto_script/tmp/udp_socket_ddr_pump_verb_sdl.rb +0 -14
- data/lib/tdl/auto_script/tmp/unpack_mac_ip_udp_D1_sdl.rb +0 -16
- data/lib/tdl/auto_script/tmp/unpack_mac_ip_udp_tcp_sdl.rb +0 -15
- data/lib/tdl/auto_script/tmp/unpack_mac_ip_udp_verd_sdl.rb +0 -13
- data/lib/tdl/auto_script/tmp/vio_wrapper_sdl.rb +0 -11
- data/lib/tdl/auto_script/tmp/wide_axis_to_axi4_wr_sdl.rb +0 -12
- data/lib/tdl/auto_script/tmp/wide_fifo_sdl.rb +0 -19
- data/lib/tdl/auto_script/tmp/width_combin_sdl.rb +0 -21
- data/lib/tdl/auto_script/tmp/width_convert_sdl.rb +0 -21
- data/lib/tdl/auto_script/tmp/xilinx_dna_capture_sdl.rb +0 -12
- data/lib/tdl/auto_script/tmp/xilinx_eth_clock_sdl.rb +0 -13
- data/lib/tdl/auto_script/tmp/xilinx_eth_reset_sdl.rb +0 -15
- data/lib/tdl/auto_script/tmp/xilinx_fifo_A1_sdl.rb +0 -22
- data/lib/tdl/auto_script/tmp/xilinx_fifo_sdl.rb +0 -20
- data/lib/tdl/auto_script/tmp/xilinx_fifo_verb_sdl.rb +0 -23
- data/lib/tdl/auto_script/tmp/xilinx_fifo_verc_sdl.rb +0 -21
- data/lib/tdl/auto_script/tmp/xilinx_hdl_dpram_sdl.rb +0 -29
- data/lib/tdl/auto_script/tmp/xilinx_hdl_dpram_sim_sdl.rb +0 -31
- data/lib/tdl/auto_script/tmp/xilinx_jtag_axil_wrapper_sdl.rb +0 -9
- data/lib/tdl/auto_script/tmp/xilinx_recfg_clock_multi_phase_ddr_wrapper_sdl.rb +0 -17
- data/lib/tdl/auto_script/tmp/xilinx_recfg_clock_multi_phase_wrapper_sdl.rb +0 -17
- data/lib/tdl/auto_script/tmp/xilinx_recfg_clock_phase_wrapper_sdl.rb +0 -17
- data/lib/tdl/auto_script/tmp/xilinx_recfg_clock_wrapper_sdl.rb +0 -13
- data/lib/tdl/auto_script/tmp/zynq_pl_common_dr_sensor_clk_sdl.rb +0 -13
- data/lib/tdl/auto_script/tmp/zynq_pl_common_lvds_sdl.rb +0 -18
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