axi_tdl 0.2.7 → 0.2.10

This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
Files changed (430) hide show
  1. checksums.yaml +4 -4
  2. data/.github/workflows/gem-push.yml +21 -48
  3. data/lib/axi_tdl/version.rb +1 -1
  4. metadata +6 -429
  5. data/lib/axi/xilinx_clock_reset/xilinx_preclock_block.sv +0 -49
  6. data/lib/axi/xilinx_clock_reset/xilinx_reset_sync.v +0 -91
  7. data/lib/axi/xilinx_clock_reset/xilinx_reset_sync_A1.sv +0 -112
  8. data/lib/axi/xilinx_clock_reset/xilinx_share_reset.sv +0 -123
  9. data/lib/axi/xilinx_clock_reset/xilinx_sync_block.v +0 -90
  10. data/lib/tdl/auto_script/tmp/MAC_FCS_sdl.rb +0 -13
  11. data/lib/tdl/auto_script/tmp/TPU_reprogram_wrapper_verb_sdl.rb +0 -16
  12. data/lib/tdl/auto_script/tmp/adc_1015_tpu_array_B1_sdl.rb +0 -20
  13. data/lib/tdl/auto_script/tmp/adc_1015_tpu_array_gray_sdl.rb +0 -19
  14. data/lib/tdl/auto_script/tmp/adc_1015_tpu_array_sdl.rb +0 -19
  15. data/lib/tdl/auto_script/tmp/adc_1015_tpu_array_verb_sdl.rb +0 -19
  16. data/lib/tdl/auto_script/tmp/adc_1015_tpu_array_verc_diffr_pca9557_sdl.rb +0 -18
  17. data/lib/tdl/auto_script/tmp/adc_1015_tpu_array_verc_diffr_sdl.rb +0 -19
  18. data/lib/tdl/auto_script/tmp/adc_1015_tpu_array_verc_sdl.rb +0 -19
  19. data/lib/tdl/auto_script/tmp/adc_1015_tpu_array_x7_gray_sdl.rb +0 -19
  20. data/lib/tdl/auto_script/tmp/adc_1015_tpu_wrapper_sdl.rb +0 -20
  21. data/lib/tdl/auto_script/tmp/aec_alarm_check_A1_sdl.rb +0 -14
  22. data/lib/tdl/auto_script/tmp/aec_alarm_check_A2_sdl.rb +0 -14
  23. data/lib/tdl/auto_script/tmp/aec_alarm_check_A3_sdl.rb +0 -14
  24. data/lib/tdl/auto_script/tmp/aec_alarm_check_A4_sdl.rb +0 -14
  25. data/lib/tdl/auto_script/tmp/aec_alarm_check_A5_sdl.rb +0 -14
  26. data/lib/tdl/auto_script/tmp/aec_alarm_check_A6_sdl.rb +0 -14
  27. data/lib/tdl/auto_script/tmp/arp_tpu_wrapper_sdl.rb +0 -16
  28. data/lib/tdl/auto_script/tmp/axi4_combin_wr_rd_batch_sdl.rb +0 -11
  29. data/lib/tdl/auto_script/tmp/axi4_data_convert_verb_sdl.rb +0 -12
  30. data/lib/tdl/auto_script/tmp/axi4_direct_A1_sdl.rb +0 -15
  31. data/lib/tdl/auto_script/tmp/axi4_direct_B1_sdl.rb +0 -10
  32. data/lib/tdl/auto_script/tmp/axi4_direct_algin_addr_step_sdl.rb +0 -20
  33. data/lib/tdl/auto_script/tmp/axi4_direct_verc_sdl.rb +0 -17
  34. data/lib/tdl/auto_script/tmp/axi4_long_to_axi4_wide_B1_sdl.rb +0 -16
  35. data/lib/tdl/auto_script/tmp/axi4_packet_fifo_B1_sdl.rb +0 -16
  36. data/lib/tdl/auto_script/tmp/axi4_partition_OD_sdl.rb +0 -13
  37. data/lib/tdl/auto_script/tmp/axi4_partition_wr_OD_sdl.rb +0 -12
  38. data/lib/tdl/auto_script/tmp/axi4_ps_convert_sdl.rb +0 -12
  39. data/lib/tdl/auto_script/tmp/axi4_rd_mix_interconnect_M2S_A1_sdl.rb +0 -11
  40. data/lib/tdl/auto_script/tmp/axi4_rd_mix_interconnect_M2S_A2_sdl.rb +0 -12
  41. data/lib/tdl/auto_script/tmp/axi4_to_native_for_ddr_ip_C1_sdl.rb +0 -24
  42. data/lib/tdl/auto_script/tmp/axi4_wr_auxiliary_gen_sdl.rb +0 -11
  43. data/lib/tdl/auto_script/tmp/axi4_wr_auxiliary_gen_without_resp_sdl.rb +0 -11
  44. data/lib/tdl/auto_script/tmp/axi4_wr_interconnect_M2S_A1_sdl.rb +0 -11
  45. data/lib/tdl/auto_script/tmp/axi4_wr_pipe_sdl.rb +0 -10
  46. data/lib/tdl/auto_script/tmp/axi_stream_cache_35bit_sdl.rb +0 -10
  47. data/lib/tdl/auto_script/tmp/axi_stream_cache_36_71bit_sdl.rb +0 -10
  48. data/lib/tdl/auto_script/tmp/axi_stream_cache_A1_sdl.rb +0 -11
  49. data/lib/tdl/auto_script/tmp/axi_stream_cache_compact_verb_sdl.rb +0 -10
  50. data/lib/tdl/auto_script/tmp/axi_stream_cache_sdl.rb +0 -10
  51. data/lib/tdl/auto_script/tmp/axi_stream_cache_verb_sdl.rb +0 -10
  52. data/lib/tdl/auto_script/tmp/axi_stream_interconnect_M2S_A1_sdl.rb +0 -12
  53. data/lib/tdl/auto_script/tmp/axi_stream_interconnect_S2M_auto_sdl.rb +0 -12
  54. data/lib/tdl/auto_script/tmp/axi_stream_interconnect_S2M_sdl.rb +0 -13
  55. data/lib/tdl/auto_script/tmp/axi_stream_long_cache_sdl.rb +0 -11
  56. data/lib/tdl/auto_script/tmp/axi_stream_long_fifo_sdl.rb +0 -12
  57. data/lib/tdl/auto_script/tmp/axi_stream_long_fifo_verb_sdl.rb +0 -12
  58. data/lib/tdl/auto_script/tmp/axi_stream_packet_fifo_sdl.rb +0 -11
  59. data/lib/tdl/auto_script/tmp/axi_stream_packet_fifo_with_info_sdl.rb +0 -14
  60. data/lib/tdl/auto_script/tmp/axi_stream_packet_long_fifo_A1_sdl.rb +0 -14
  61. data/lib/tdl/auto_script/tmp/axi_stream_packet_long_fifo_sdl.rb +0 -13
  62. data/lib/tdl/auto_script/tmp/axi_stream_planer_sdl.rb +0 -15
  63. data/lib/tdl/auto_script/tmp/axi_stream_to_axi4_wr_sdl.rb +0 -10
  64. data/lib/tdl/auto_script/tmp/axi_stream_wide_fifo_sdl.rb +0 -11
  65. data/lib/tdl/auto_script/tmp/axi_streams_combin_A1_sdl.rb +0 -16
  66. data/lib/tdl/auto_script/tmp/axi_streams_scaler_A1_sdl.rb +0 -15
  67. data/lib/tdl/auto_script/tmp/axis_append_A1_sdl.rb +0 -19
  68. data/lib/tdl/auto_script/tmp/axis_connect_pipe_right_shift_sdl.rb +0 -11
  69. data/lib/tdl/auto_script/tmp/axis_connect_pipe_right_shift_verb_sdl.rb +0 -13
  70. data/lib/tdl/auto_script/tmp/axis_connect_pipe_sdl.rb +0 -10
  71. data/lib/tdl/auto_script/tmp/axis_connect_pipe_with_info_sdl.rb +0 -13
  72. data/lib/tdl/auto_script/tmp/axis_direct_A1_sdl.rb +0 -12
  73. data/lib/tdl/auto_script/tmp/axis_direct_sdl.rb +0 -10
  74. data/lib/tdl/auto_script/tmp/axis_ex_status_sdl.rb +0 -13
  75. data/lib/tdl/auto_script/tmp/axis_head_cut_sdl.rb +0 -11
  76. data/lib/tdl/auto_script/tmp/axis_head_cut_verb_sdl.rb +0 -11
  77. data/lib/tdl/auto_script/tmp/axis_intc_S2M_with_addr_inf_sdl.rb +0 -13
  78. data/lib/tdl/auto_script/tmp/axis_length_cut_sdl.rb +0 -11
  79. data/lib/tdl/auto_script/tmp/axis_length_fill_sdl.rb +0 -11
  80. data/lib/tdl/auto_script/tmp/axis_length_fill_verb_sdl.rb +0 -13
  81. data/lib/tdl/auto_script/tmp/axis_length_split_sdl.rb +0 -11
  82. data/lib/tdl/auto_script/tmp/axis_length_split_with_addr_sdl.rb +0 -14
  83. data/lib/tdl/auto_script/tmp/axis_length_split_with_user_sdl.rb +0 -11
  84. data/lib/tdl/auto_script/tmp/axis_master_empty_sdl.rb +0 -9
  85. data/lib/tdl/auto_script/tmp/axis_mirror_to_master_sdl.rb +0 -11
  86. data/lib/tdl/auto_script/tmp/axis_pkt_fifo_filter_keep_A1_sdl.rb +0 -11
  87. data/lib/tdl/auto_script/tmp/axis_pkt_fifo_filter_keep_sdl.rb +0 -11
  88. data/lib/tdl/auto_script/tmp/axis_slaver_empty_sdl.rb +0 -9
  89. data/lib/tdl/auto_script/tmp/axis_slaver_pipe_A1_sdl.rb +0 -11
  90. data/lib/tdl/auto_script/tmp/axis_slaver_pipe_sdl.rb +0 -10
  91. data/lib/tdl/auto_script/tmp/axis_uncompress_A1_sdl.rb +0 -13
  92. data/lib/tdl/auto_script/tmp/axis_uncompress_verb_sdl.rb +0 -13
  93. data/lib/tdl/auto_script/tmp/axis_valve_sdl.rb +0 -11
  94. data/lib/tdl/auto_script/tmp/axis_valve_with_pipe_sdl.rb +0 -12
  95. data/lib/tdl/auto_script/tmp/axis_width_convert_sdl.rb +0 -10
  96. data/lib/tdl/auto_script/tmp/axis_width_convert_verb_sdl.rb +0 -12
  97. data/lib/tdl/auto_script/tmp/axis_width_destruct_sdl.rb +0 -10
  98. data/lib/tdl/auto_script/tmp/board_cs_ctrl_gray_sdl.rb +0 -14
  99. data/lib/tdl/auto_script/tmp/board_cs_ctrl_gray_x7_sdl.rb +0 -14
  100. data/lib/tdl/auto_script/tmp/broaden_and_cross_clk_sdl.rb +0 -17
  101. data/lib/tdl/auto_script/tmp/cbct_chip_reg_dport_wrapper_sdl.rb +0 -20
  102. data/lib/tdl/auto_script/tmp/cbct_chip_reg_wrapper_sdl.rb +0 -19
  103. data/lib/tdl/auto_script/tmp/cbct_iic_bus_tri_wrapper_sdl.rb +0 -18
  104. data/lib/tdl/auto_script/tmp/cbct_iic_bus_wrapper_sdl.rb +0 -14
  105. data/lib/tdl/auto_script/tmp/cbct_lock_lvds_data_sdl.rb +0 -16
  106. data/lib/tdl/auto_script/tmp/cbct_sensor_driver_array_sdl.rb +0 -12
  107. data/lib/tdl/auto_script/tmp/cbct_sensor_driver_clock_A1_sdl.rb +0 -13
  108. data/lib/tdl/auto_script/tmp/cbct_sensor_driver_clock_sdl.rb +0 -12
  109. data/lib/tdl/auto_script/tmp/cbct_single_sensor_lvds_dir_sdl.rb +0 -14
  110. data/lib/tdl/auto_script/tmp/chip_reg_tpu_phase_upgrade_sdl.rb +0 -25
  111. data/lib/tdl/auto_script/tmp/chip_reg_tpu_wrapper_gray_sdl.rb +0 -24
  112. data/lib/tdl/auto_script/tmp/chip_reg_tpu_wrapper_sdl.rb +0 -25
  113. data/lib/tdl/auto_script/tmp/chip_reg_tpu_wrapper_slot_gray_sdl.rb +0 -24
  114. data/lib/tdl/auto_script/tmp/chip_reg_tpu_wrapper_speci_gray_sdl.rb +0 -24
  115. data/lib/tdl/auto_script/tmp/chip_reg_tpu_wrapper_verb_sdl.rb +0 -24
  116. data/lib/tdl/auto_script/tmp/chip_reg_tpu_wrapper_x7_gray_sdl.rb +0 -24
  117. data/lib/tdl/auto_script/tmp/chip_spi_model_sdl.rb +0 -12
  118. data/lib/tdl/auto_script/tmp/clock_lvds_bitslip_sdl.rb +0 -13
  119. data/lib/tdl/auto_script/tmp/clock_manager_A2_sdl.rb +0 -25
  120. data/lib/tdl/auto_script/tmp/clock_manager_B2_sdl.rb +0 -26
  121. data/lib/tdl/auto_script/tmp/clock_manager_powerlow_sdl.rb +0 -22
  122. data/lib/tdl/auto_script/tmp/clock_manager_sdl.rb +0 -16
  123. data/lib/tdl/auto_script/tmp/clock_rst_verb_sdl.rb +0 -14
  124. data/lib/tdl/auto_script/tmp/clock_rst_verc_sdl.rb +0 -15
  125. data/lib/tdl/auto_script/tmp/cmos_redx_1xN_inner_clock_sdl.rb +0 -33
  126. data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0004.coe +0 -18
  127. data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0014.coe +0 -18
  128. data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0017.coe +0 -18
  129. data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0019.coe +0 -18
  130. data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0023.coe +0 -18
  131. data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0024.coe +0 -18
  132. data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0025.coe +0 -18
  133. data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0027.coe +0 -18
  134. data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0030.coe +0 -18
  135. data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0037.coe +0 -18
  136. data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0038.coe +0 -18
  137. data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0040.coe +0 -18
  138. data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0041.coe +0 -18
  139. data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0042.coe +0 -18
  140. data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0043.coe +0 -18
  141. data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0049.coe +0 -18
  142. data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0052.coe +0 -18
  143. data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0054.coe +0 -18
  144. data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0055.coe +0 -18
  145. data/lib/tdl/auto_script/tmp/coe_origin_mac_inf_x_0_R0000.coe +0 -9825
  146. data/lib/tdl/auto_script/tmp/coe_origin_mac_inf_x_1_R0001.coe +0 -9720
  147. data/lib/tdl/auto_script/tmp/coe_origin_mac_inf_x_2_R0002.coe +0 -9825
  148. data/lib/tdl/auto_script/tmp/coe_origin_mac_inf_x_3_R0003.coe +0 -9825
  149. data/lib/tdl/auto_script/tmp/coe_origin_mac_inf_x_R0000.coe +0 -26
  150. data/lib/tdl/auto_script/tmp/coe_uart_tx_inf_R0000.coe +0 -5025
  151. data/lib/tdl/auto_script/tmp/common_axli_flow_sdl.rb +0 -12
  152. data/lib/tdl/auto_script/tmp/common_fifo_sdl.rb +0 -22
  153. data/lib/tdl/auto_script/tmp/common_redx_1xN_ddr_simple_sdl.rb +0 -32
  154. data/lib/tdl/auto_script/tmp/common_redx_1xN_sdr_serdes_simple_sdl.rb +0 -31
  155. data/lib/tdl/auto_script/tmp/common_redx_1xN_sdr_simple_sdl.rb +0 -32
  156. data/lib/tdl/auto_script/tmp/cross_clk_sync_sdl.rb +0 -14
  157. data/lib/tdl/auto_script/tmp/custom_serdes_router_sdl.rb +0 -17
  158. data/lib/tdl/auto_script/tmp/data_c_cache_sdl.rb +0 -10
  159. data/lib/tdl/auto_script/tmp/data_c_direct_sdl.rb +0 -10
  160. data/lib/tdl/auto_script/tmp/data_c_pipe_force_vld_bind_data_sdl.rb +0 -14
  161. data/lib/tdl/auto_script/tmp/data_c_pipe_force_vld_sdl.rb +0 -10
  162. data/lib/tdl/auto_script/tmp/data_c_pipe_inf_sdl.rb +0 -10
  163. data/lib/tdl/auto_script/tmp/data_c_pipe_intc_M2S_best_robin_sdl.rb +0 -12
  164. data/lib/tdl/auto_script/tmp/data_c_pipe_sync_sdl.rb +0 -13
  165. data/lib/tdl/auto_script/tmp/data_c_sim_master_model_sdl.rb +0 -15
  166. data/lib/tdl/auto_script/tmp/data_inf_c_intc_S2M_sdl.rb +0 -13
  167. data/lib/tdl/auto_script/tmp/data_inf_c_planer_A1_sdl.rb +0 -15
  168. data/lib/tdl/auto_script/tmp/data_lvds_bitslip_sdl.rb +0 -12
  169. data/lib/tdl/auto_script/tmp/data_lvds_simple_bitslip_sdl.rb +0 -12
  170. data/lib/tdl/auto_script/tmp/data_mirrors_sdl.rb +0 -15
  171. data/lib/tdl/auto_script/tmp/datainf_c_slaver_empty_sdl.rb +0 -9
  172. data/lib/tdl/auto_script/tmp/ddr3_ip_wrapper_sdl.rb +0 -28
  173. data/lib/tdl/auto_script/tmp/ddr_axi4_to_axis_sdl.rb +0 -11
  174. data/lib/tdl/auto_script/tmp/det_moto_findex_sdl.rb +0 -13
  175. data/lib/tdl/auto_script/tmp/det_start_block_sdl.rb +0 -17
  176. data/lib/tdl/auto_script/tmp/det_start_filter_sdl.rb +0 -15
  177. data/lib/tdl/auto_script/tmp/det_with_pre_A3_sdl.rb +0 -28
  178. data/lib/tdl/auto_script/tmp/det_with_pre_A4_sdl.rb +0 -28
  179. data/lib/tdl/auto_script/tmp/det_with_pre_B1_sdl.rb +0 -29
  180. data/lib/tdl/auto_script/tmp/det_with_pre_findex_sdl.rb +0 -18
  181. data/lib/tdl/auto_script/tmp/det_with_pre_verb_sdl.rb +0 -29
  182. data/lib/tdl/auto_script/tmp/diffr_multi_phase_sample_sdl.rb +0 -17
  183. data/lib/tdl/auto_script/tmp/diffr_reg_tpu_v3_wrapper_sdl.rb +0 -17
  184. data/lib/tdl/auto_script/tmp/diffr_reg_tpu_wrapper_sdl.rb +0 -16
  185. data/lib/tdl/auto_script/tmp/diffr_reg_tpu_wrapper_v2_sdl.rb +0 -16
  186. data/lib/tdl/auto_script/tmp/dire_accese_flash_sdl.rb +0 -17
  187. data/lib/tdl/auto_script/tmp/dyn_edge_clock_sdl.rb +0 -15
  188. data/lib/tdl/auto_script/tmp/edge_generator_sdl.rb +0 -14
  189. data/lib/tdl/auto_script/tmp/eth4_chip_reg_wrapper_sdl.rb +0 -20
  190. data/lib/tdl/auto_script/tmp/eth4_lvds_tb_block_sdl.rb +0 -16
  191. data/lib/tdl/auto_script/tmp/eth4_sensor_driver_array_sdl.rb +0 -17
  192. data/lib/tdl/auto_script/tmp/eth4_single_chip_Red2S_lvds_dir_sdl.rb +0 -16
  193. data/lib/tdl/auto_script/tmp/eth_2g5_wrapper_sdl.rb +0 -25
  194. data/lib/tdl/auto_script/tmp/eth_outShare_wrapper_sdl.rb +0 -28
  195. data/lib/tdl/auto_script/tmp/eth_to_ddr_with_ack_sdl.rb +0 -13
  196. data/lib/tdl/auto_script/tmp/eth_to_spi_verb_sdl.rb +0 -20
  197. data/lib/tdl/auto_script/tmp/eth_to_standard_spi_with_ack_sdl.rb +0 -17
  198. data/lib/tdl/auto_script/tmp/eth_to_standard_uart_with_ack_sdl.rb +0 -16
  199. data/lib/tdl/auto_script/tmp/eth_xilinx_ip_sdl.rb +0 -22
  200. data/lib/tdl/auto_script/tmp/ethernet_wrapper_2d5G_sdl.rb +0 -28
  201. data/lib/tdl/auto_script/tmp/ethernet_wrapper_sdl.rb +0 -28
  202. data/lib/tdl/auto_script/tmp/ethernet_wrapper_track_sdl.rb +0 -28
  203. data/lib/tdl/auto_script/tmp/ext_sync_filter_sdl.rb +0 -14
  204. data/lib/tdl/auto_script/tmp/fifo_36kb_long_sdl.rb +0 -20
  205. data/lib/tdl/auto_script/tmp/fifo_73_96bit_sdl.rb +0 -19
  206. data/lib/tdl/auto_script/tmp/four_chips_Red5_lvds_dir_sdl.rb +0 -15
  207. data/lib/tdl/auto_script/tmp/four_chips_Red5_lvds_pins_delay_sdl.rb +0 -20
  208. data/lib/tdl/auto_script/tmp/full_axi4_to_axis_partition_wr_rd_sdl.rb +0 -12
  209. data/lib/tdl/auto_script/tmp/full_axi4_to_axis_sdl.rb +0 -11
  210. data/lib/tdl/auto_script/tmp/gen_big_field_table_sdl.rb +0 -15
  211. data/lib/tdl/auto_script/tmp/gen_common_frame_table_sdl.rb +0 -61
  212. data/lib/tdl/auto_script/tmp/gen_origin_axis_A2_sdl.rb +0 -14
  213. data/lib/tdl/auto_script/tmp/gen_origin_axis_A3_sdl.rb +0 -15
  214. data/lib/tdl/auto_script/tmp/gen_origin_axis_sdl.rb +0 -13
  215. data/lib/tdl/auto_script/tmp/general_tap_ack_A2_sdl.rb +0 -17
  216. data/lib/tdl/auto_script/tmp/general_tap_ack_A3_sdl.rb +0 -18
  217. data/lib/tdl/auto_script/tmp/general_tap_ack_A4_sdl.rb +0 -19
  218. data/lib/tdl/auto_script/tmp/general_tap_ack_sdl.rb +0 -16
  219. data/lib/tdl/auto_script/tmp/general_tap_no_ack_sdl.rb +0 -15
  220. data/lib/tdl/auto_script/tmp/general_tap_send_sdl.rb +0 -19
  221. data/lib/tdl/auto_script/tmp/gmii_from_mac_sdl.rb +0 -12
  222. data/lib/tdl/auto_script/tmp/gmii_to_mac_sdl.rb +0 -14
  223. data/lib/tdl/auto_script/tmp/gt_transceivers_axis_verb_sdl.rb +0 -22
  224. data/lib/tdl/auto_script/tmp/gt_tx_pack_proto_sdl.rb +0 -12
  225. data/lib/tdl/auto_script/tmp/gvi_k7_clock_manager_sdl.rb +0 -19
  226. data/lib/tdl/auto_script/tmp/gvi_k7_ddr3_ip_wrapper_sdl.rb +0 -29
  227. data/lib/tdl/auto_script/tmp/hardware_date_core_sdl.rb +0 -14
  228. data/lib/tdl/auto_script/tmp/hdl_test_sdl.rb +0 -13
  229. data/lib/tdl/auto_script/tmp/iic_gpio_pca9557_array_sdl.rb +0 -14
  230. data/lib/tdl/auto_script/tmp/independent_clock_fifo_a1_sdl.rb +0 -22
  231. data/lib/tdl/auto_script/tmp/independent_clock_fifo_sdl.rb +0 -21
  232. data/lib/tdl/auto_script/tmp/inf_time_delay_ctrl_sdl.rb +0 -10
  233. data/lib/tdl/auto_script/tmp/inf_time_delay_ctrl_verb_sdl.rb +0 -13
  234. data/lib/tdl/auto_script/tmp/init_10G_sdl.rb +0 -11
  235. data/lib/tdl/auto_script/tmp/init_mac_sdl.rb +0 -14
  236. data/lib/tdl/auto_script/tmp/init_trigger_cfg_10g_sdl.rb +0 -11
  237. data/lib/tdl/auto_script/tmp/inner_clock_to_sensor_sdl.rb +0 -13
  238. data/lib/tdl/auto_script/tmp/ip_check_sum_sdl.rb +0 -22
  239. data/lib/tdl/auto_script/tmp/k7_ethernet_10g_wrapper_B2_sdl.rb +0 -24
  240. data/lib/tdl/auto_script/tmp/k7_ethernet_multi_10g_wrapper_sdl.rb +0 -23
  241. data/lib/tdl/auto_script/tmp/keys_filter_sdl.rb +0 -14
  242. data/lib/tdl/auto_script/tmp/latency_dynamic_sdl.rb +0 -14
  243. data/lib/tdl/auto_script/tmp/latency_sdl.rb +0 -14
  244. data/lib/tdl/auto_script/tmp/lock_lvds_data_sdl.rb +0 -19
  245. data/lib/tdl/auto_script/tmp/lvds2cmos_sdl.rb +0 -11
  246. data/lib/tdl/auto_script/tmp/lvds_ibufds_array_NOBUFF_sdl.rb +0 -15
  247. data/lib/tdl/auto_script/tmp/lvds_ibufds_array_r8_1x6_NOBUFF_sdl.rb +0 -16
  248. data/lib/tdl/auto_script/tmp/lvds_ibufds_array_r8_1x6_OB_sdl.rb +0 -19
  249. data/lib/tdl/auto_script/tmp/lvds_ibufds_array_sdl.rb +0 -15
  250. data/lib/tdl/auto_script/tmp/lvds_tb_block_A1_sdl.rb +0 -16
  251. data/lib/tdl/auto_script/tmp/mac_to_file_sdl.rb +0 -11
  252. data/lib/tdl/auto_script/tmp/manchester_router_sdl.rb +0 -13
  253. data/lib/tdl/auto_script/tmp/mdio_model_sdl.rb +0 -11
  254. data/lib/tdl/auto_script/tmp/mdio_proto_sdl.rb +0 -24
  255. data/lib/tdl/auto_script/tmp/mirror_mac_arp_iic_sdl.rb +0 -10
  256. data/lib/tdl/auto_script/tmp/modified_eth_2G5_top_sdl.rb +0 -16
  257. data/lib/tdl/auto_script/tmp/multiple_steps_676_sdl.rb +0 -15
  258. data/lib/tdl/auto_script/tmp/multiple_steps_A2_sdl.rb +0 -15
  259. data/lib/tdl/auto_script/tmp/odata_pool_axi4_A2_sdl.rb +0 -11
  260. data/lib/tdl/auto_script/tmp/odata_pool_axi4_A3_sdl.rb +0 -14
  261. data/lib/tdl/auto_script/tmp/outSt_combin_spi_core_sdl.rb +0 -22
  262. data/lib/tdl/auto_script/tmp/outSt_eth_to_ct_databoard_sdl.rb +0 -13
  263. data/lib/tdl/auto_script/tmp/outSt_eth_to_multi_spi_with_ack_sdl.rb +0 -19
  264. data/lib/tdl/auto_script/tmp/outSt_eth_to_spi_sdl.rb +0 -20
  265. data/lib/tdl/auto_script/tmp/outSt_eth_to_spi_verb_sdl.rb +0 -17
  266. data/lib/tdl/auto_script/tmp/outSt_eth_to_spi_with_ack_sdl.rb +0 -17
  267. data/lib/tdl/auto_script/tmp/outSt_spi_core_B1_sdl.rb +0 -21
  268. data/lib/tdl/auto_script/tmp/pack_ip_mac_B1_sdl.rb +0 -15
  269. data/lib/tdl/auto_script/tmp/pack_ip_mac_verb_sdl.rb +0 -15
  270. data/lib/tdl/auto_script/tmp/parse_big_field_table_A2_sdl.rb +0 -19
  271. data/lib/tdl/auto_script/tmp/parse_big_field_table_main_sdl.rb +0 -15
  272. data/lib/tdl/auto_script/tmp/parse_big_field_table_mirror_sdl.rb +0 -14
  273. data/lib/tdl/auto_script/tmp/parse_big_field_table_sdl.rb +0 -18
  274. data/lib/tdl/auto_script/tmp/parse_big_field_table_slaver_sdl.rb +0 -17
  275. data/lib/tdl/auto_script/tmp/parse_big_field_table_verb_sdl.rb +0 -17
  276. data/lib/tdl/auto_script/tmp/parse_common_frame_table_A1_sdl.rb +0 -64
  277. data/lib/tdl/auto_script/tmp/parse_tap_stream_sdl.rb +0 -10
  278. data/lib/tdl/auto_script/tmp/phase_red8_sensor_lvds_block_red8_sdl.rb +0 -22
  279. data/lib/tdl/auto_script/tmp/phase_sensor_sync_ctrl_sdl.rb +0 -17
  280. data/lib/tdl/auto_script/tmp/platform_shift_ctrl_verb_sdl.rb +0 -22
  281. data/lib/tdl/auto_script/tmp/poll_udp_tpu_upgrade_sdl.rb +0 -30
  282. data/lib/tdl/auto_script/tmp/poll_udp_tpu_verb_upgrade_sdl.rb +0 -34
  283. data/lib/tdl/auto_script/tmp/prim_serdes_filter_decode_sdl.rb +0 -14
  284. data/lib/tdl/auto_script/tmp/red2s_lock_lvds_data_verc_sdl.rb +0 -20
  285. data/lib/tdl/auto_script/tmp/red3_lock_lvds_data_verc_sdl.rb +0 -18
  286. data/lib/tdl/auto_script/tmp/red3_lvds_tb_block_A1_sdl.rb +0 -16
  287. data/lib/tdl/auto_script/tmp/red5_chip_reg_wrapper_A1_sdl.rb +0 -20
  288. data/lib/tdl/auto_script/tmp/red5_chip_reg_wrapper_A2_sdl.rb +0 -21
  289. data/lib/tdl/auto_script/tmp/red5_chip_reg_wrapper_sdl.rb +0 -19
  290. data/lib/tdl/auto_script/tmp/red5_lock_lvds_data_raw_A1_sdl.rb +0 -20
  291. data/lib/tdl/auto_script/tmp/red5_lock_lvds_data_sdl.rb +0 -18
  292. data/lib/tdl/auto_script/tmp/red5_lock_lvds_data_verb_sdl.rb +0 -18
  293. data/lib/tdl/auto_script/tmp/red5_lock_lvds_data_verc_sdl.rb +0 -22
  294. data/lib/tdl/auto_script/tmp/red5_lvds_clock_mmcm_sdl.rb +0 -12
  295. data/lib/tdl/auto_script/tmp/red8_1x6_oneBoard_sdl.rb +0 -30
  296. data/lib/tdl/auto_script/tmp/red8_chip_reg_wrapper_A2_sdl.rb +0 -21
  297. data/lib/tdl/auto_script/tmp/redx_1xN_ddr_inner_clock_sdl.rb +0 -36
  298. data/lib/tdl/auto_script/tmp/redx_1xN_ddr_inner_clock_verb_sdl.rb +0 -38
  299. data/lib/tdl/auto_script/tmp/redx_1xN_ddr_serdes_manual_A1_sdl.rb +0 -38
  300. data/lib/tdl/auto_script/tmp/redx_1xN_ddr_serdes_manual_A2_sdl.rb +0 -39
  301. data/lib/tdl/auto_script/tmp/redx_1xN_ddr_serdes_manual_sdl.rb +0 -35
  302. data/lib/tdl/auto_script/tmp/redx_1xN_inner_clock_sdl.rb +0 -36
  303. data/lib/tdl/auto_script/tmp/redx_1xN_sdr_serdes_manual_A1_sdl.rb +0 -36
  304. data/lib/tdl/auto_script/tmp/redx_lock_lvds_data_2B_sdl.rb +0 -25
  305. data/lib/tdl/auto_script/tmp/redx_lock_lvds_data_4B_bitslip_sdl.rb +0 -26
  306. data/lib/tdl/auto_script/tmp/redx_lock_lvds_data_4B_sdl.rb +0 -25
  307. data/lib/tdl/auto_script/tmp/redx_lock_lvds_data_4B_verb_sdl.rb +0 -25
  308. data/lib/tdl/auto_script/tmp/redx_lock_lvds_data_dyn_compact_sdl.rb +0 -26
  309. data/lib/tdl/auto_script/tmp/redx_lock_lvds_data_dyn_sdl.rb +0 -26
  310. data/lib/tdl/auto_script/tmp/redx_lock_lvds_data_raw_sdl.rb +0 -21
  311. data/lib/tdl/auto_script/tmp/redx_lock_lvds_data_raw_verb_sdl.rb +0 -22
  312. data/lib/tdl/auto_script/tmp/redx_lock_lvds_data_sdl.rb +0 -22
  313. data/lib/tdl/auto_script/tmp/redx_lock_lvds_data_verb_sdl.rb +0 -23
  314. data/lib/tdl/auto_script/tmp/redx_lvds_dir_to_4B_sdl.rb +0 -21
  315. data/lib/tdl/auto_script/tmp/redx_lvds_dir_to_4B_var_delay_multi_phase_DDR_sdl.rb +0 -29
  316. data/lib/tdl/auto_script/tmp/redx_lvds_dir_to_4B_var_delay_multi_phase_sdl.rb +0 -28
  317. data/lib/tdl/auto_script/tmp/redx_lvds_dir_to_4B_var_delay_sdl.rb +0 -23
  318. data/lib/tdl/auto_script/tmp/rgmii_to_gmii_wrapper_sdl.rb +0 -17
  319. data/lib/tdl/auto_script/tmp/riffa_trans_axis_sdl.rb +0 -22
  320. data/lib/tdl/auto_script/tmp/sct_ddr3_16bit_ip_wrapper_sdl.rb +0 -28
  321. data/lib/tdl/auto_script/tmp/sct_ddr3_ip_wrapper_sdl.rb +0 -29
  322. data/lib/tdl/auto_script/tmp/sel_system_ip_mac_sdl.rb +0 -15
  323. data/lib/tdl/auto_script/tmp/senser_lvds_parse_16bit_diffr_sdl.rb +0 -16
  324. data/lib/tdl/auto_script/tmp/senser_lvds_parse_24bit_diffr_A1_sdl.rb +0 -16
  325. data/lib/tdl/auto_script/tmp/senser_lvds_parse_24bit_diffr_sdl.rb +0 -15
  326. data/lib/tdl/auto_script/tmp/sensor_block_unit_C2_sdl.rb +0 -29
  327. data/lib/tdl/auto_script/tmp/sensor_block_unit_C2_track_crc8_sdl.rb +0 -29
  328. data/lib/tdl/auto_script/tmp/sensor_clock_recv_check_sdl.rb +0 -11
  329. data/lib/tdl/auto_script/tmp/sensor_ctrl_676_28lvds_sdl.rb +0 -18
  330. data/lib/tdl/auto_script/tmp/sensor_ctrl_676_sdl.rb +0 -17
  331. data/lib/tdl/auto_script/tmp/sensor_drive_lvds_clk_SP_sdl.rb +0 -15
  332. data/lib/tdl/auto_script/tmp/sensor_drive_lvds_clk_sdl.rb +0 -17
  333. data/lib/tdl/auto_script/tmp/sensor_drive_lvds_clk_verb_sdl.rb +0 -18
  334. data/lib/tdl/auto_script/tmp/sensor_driver_clock_set_A2_sdl.rb +0 -13
  335. data/lib/tdl/auto_script/tmp/sensor_lvds_block_unit_28lvds_findex_SP_sdl.rb +0 -23
  336. data/lib/tdl/auto_script/tmp/sensor_lvds_block_unit_28lvds_findex_edge_sync_sdl.rb +0 -23
  337. data/lib/tdl/auto_script/tmp/sensor_lvds_block_unit_28lvds_findex_sdl.rb +0 -23
  338. data/lib/tdl/auto_script/tmp/sensor_lvds_block_unit_28lvds_findex_verb_sdl.rb +0 -23
  339. data/lib/tdl/auto_script/tmp/sensor_lvds_block_unit_28lvds_sdl.rb +0 -21
  340. data/lib/tdl/auto_script/tmp/sensor_lvds_block_unit_findex_sdl.rb +0 -23
  341. data/lib/tdl/auto_script/tmp/sensor_lvds_block_unit_findex_verb_A1_sdl.rb +0 -23
  342. data/lib/tdl/auto_script/tmp/sensor_lvds_block_unit_findex_verb_red450_sdl.rb +0 -22
  343. data/lib/tdl/auto_script/tmp/sensor_lvds_block_unit_findex_verb_sdl.rb +0 -23
  344. data/lib/tdl/auto_script/tmp/sensor_lvds_block_unit_findex_verc_red450_sdl.rb +0 -22
  345. data/lib/tdl/auto_script/tmp/sensor_lvds_block_unit_findex_verc_sdl.rb +0 -22
  346. data/lib/tdl/auto_script/tmp/sensor_lvds_block_unit_sdl.rb +0 -21
  347. data/lib/tdl/auto_script/tmp/serdes_parl_lock_sdl.rb +0 -18
  348. data/lib/tdl/auto_script/tmp/serdes_to_data_array_sdl.rb +0 -19
  349. data/lib/tdl/auto_script/tmp/sim_arp_tpu_sdl.rb +0 -17
  350. data/lib/tdl/auto_script/tmp/sim_auto_wireshark_send_sdl.rb +0 -14
  351. data/lib/tdl/auto_script/tmp/sim_tpu_update_file_sdl.rb +0 -13
  352. data/lib/tdl/auto_script/tmp/simple_cbct_lock_lvds_data_sdl.rb +0 -16
  353. data/lib/tdl/auto_script/tmp/simple_hardware_log_track_sdl.rb +0 -14
  354. data/lib/tdl/auto_script/tmp/simple_hw_test_top_sdl.rb +0 -19
  355. data/lib/tdl/auto_script/tmp/simple_test_eth_2g5_subs_sdl.rb +0 -18
  356. data/lib/tdl/auto_script/tmp/single_chip_Red2S_lvds_dir_sdl.rb +0 -15
  357. data/lib/tdl/auto_script/tmp/single_chip_Red3_lvds_pins_delay_sdl.rb +0 -17
  358. data/lib/tdl/auto_script/tmp/single_chip_iic_bus_verb_wrapper_sdl.rb +0 -14
  359. data/lib/tdl/auto_script/tmp/single_chip_iic_bus_verc_wrapper_sdl.rb +0 -15
  360. data/lib/tdl/auto_script/tmp/single_chip_iic_bus_verd_wrapper_sdl.rb +0 -15
  361. data/lib/tdl/auto_script/tmp/single_chip_iic_bus_wrapper_sdl.rb +0 -14
  362. data/lib/tdl/auto_script/tmp/single_chip_lvds_ddr_dir_sdl.rb +0 -18
  363. data/lib/tdl/auto_script/tmp/single_chip_lvds_dir_delay_sdl.rb +0 -19
  364. data/lib/tdl/auto_script/tmp/single_chip_lvds_dir_inner_sdl.rb +0 -17
  365. data/lib/tdl/auto_script/tmp/single_chip_sensor_lvds_dir_sdl.rb +0 -15
  366. data/lib/tdl/auto_script/tmp/sketch_to_origin_stream_sdl.rb +0 -13
  367. data/lib/tdl/auto_script/tmp/slow_lvds_data_d2s_sdl.rb +0 -13
  368. data/lib/tdl/auto_script/tmp/slow_sensor_inner_clock_sdl.rb +0 -18
  369. data/lib/tdl/auto_script/tmp/split_ddr3_ip_wrapper_sdl.rb +0 -45
  370. data/lib/tdl/auto_script/tmp/tcp_aux_tpu_upgrade_sdl.rb +0 -50
  371. data/lib/tdl/auto_script/tmp/tcp_check_sum_sdl.rb +0 -15
  372. data/lib/tdl/auto_script/tmp/tcp_ctrl_set_sdl.rb +0 -13
  373. data/lib/tdl/auto_script/tmp/tcp_option_split_B1_sdl.rb +0 -10
  374. data/lib/tdl/auto_script/tmp/test_red5dl_lvds_sdl.rb +0 -9
  375. data/lib/tdl/auto_script/tmp/time_delay_ctrl_sdl.rb +0 -13
  376. data/lib/tdl/auto_script/tmp/time_enable_scaler_sdl.rb +0 -12
  377. data/lib/tdl/auto_script/tmp/time_step_module_A1_sdl.rb +0 -14
  378. data/lib/tdl/auto_script/tmp/time_step_module_sdl.rb +0 -13
  379. data/lib/tdl/auto_script/tmp/tpu_bypass_iic_upgrade_sdl.rb +0 -29
  380. data/lib/tdl/auto_script/tmp/tpu_common_iic_upgrade_sdl.rb +0 -25
  381. data/lib/tdl/auto_script/tmp/tpu_custom_iic_bus_C1_wrapper_gray_sdl.rb +0 -19
  382. data/lib/tdl/auto_script/tmp/tpu_custom_iic_bus_C1_wrapper_sdl.rb +0 -20
  383. data/lib/tdl/auto_script/tmp/tpu_custom_iic_bus_C1_wrapper_verb_sdl.rb +0 -19
  384. data/lib/tdl/auto_script/tmp/tpu_custom_iic_bus_C1_wrapper_x7_gray_sdl.rb +0 -19
  385. data/lib/tdl/auto_script/tmp/tpu_custom_iic_bus_verc_v2_array_sdl.rb +0 -15
  386. data/lib/tdl/auto_script/tmp/tpu_custom_iic_bus_verc_v3_wrapper_sdl.rb +0 -17
  387. data/lib/tdl/auto_script/tmp/tpu_custom_iic_bus_verc_v4_wrapper_sdl.rb +0 -19
  388. data/lib/tdl/auto_script/tmp/tpu_custom_iic_bus_verc_v5_wrapper_sdl.rb +0 -20
  389. data/lib/tdl/auto_script/tmp/tpu_custom_iic_bus_verc_wrapper_sdl.rb +0 -20
  390. data/lib/tdl/auto_script/tmp/tpu_eth4_iic_bus_wrapper_sdl.rb +0 -15
  391. data/lib/tdl/auto_script/tmp/tpu_mgm_inf_sdl.rb +0 -28
  392. data/lib/tdl/auto_script/tmp/tpu_simple_boot_sdl.rb +0 -12
  393. data/lib/tdl/auto_script/tmp/trigger_data_inf_c_A1_sdl.rb +0 -12
  394. data/lib/tdl/auto_script/tmp/trigger_data_inf_c_sdl.rb +0 -12
  395. data/lib/tdl/auto_script/tmp/uart_hp_ddr3_tft800x480_hdmi_ext_sdl.rb +0 -43
  396. data/lib/tdl/auto_script/tmp/uart_hp_ddr3_tft800x480_hdmi_ext_sim_sdl.rb +0 -43
  397. data/lib/tdl/auto_script/tmp/uart_rx_core_dma_verb_sdl.rb +0 -13
  398. data/lib/tdl/auto_script/tmp/uart_top_bypass_sdl.rb +0 -21
  399. data/lib/tdl/auto_script/tmp/uart_top_sdl.rb +0 -21
  400. data/lib/tdl/auto_script/tmp/udp_check_sum_sdl.rb +0 -15
  401. data/lib/tdl/auto_script/tmp/udp_ctrl_set_A1_sdl.rb +0 -18
  402. data/lib/tdl/auto_script/tmp/udp_fpga_ports_route_sdl.rb +0 -12
  403. data/lib/tdl/auto_script/tmp/udp_socket_ddr_pump_64b_sdl.rb +0 -16
  404. data/lib/tdl/auto_script/tmp/udp_socket_ddr_pump_A3_sdl.rb +0 -14
  405. data/lib/tdl/auto_script/tmp/udp_socket_ddr_pump_B1_sdl.rb +0 -14
  406. data/lib/tdl/auto_script/tmp/udp_socket_ddr_pump_verb_sdl.rb +0 -14
  407. data/lib/tdl/auto_script/tmp/unpack_mac_ip_udp_D1_sdl.rb +0 -16
  408. data/lib/tdl/auto_script/tmp/unpack_mac_ip_udp_tcp_sdl.rb +0 -15
  409. data/lib/tdl/auto_script/tmp/unpack_mac_ip_udp_verd_sdl.rb +0 -13
  410. data/lib/tdl/auto_script/tmp/vio_wrapper_sdl.rb +0 -11
  411. data/lib/tdl/auto_script/tmp/wide_axis_to_axi4_wr_sdl.rb +0 -12
  412. data/lib/tdl/auto_script/tmp/wide_fifo_sdl.rb +0 -19
  413. data/lib/tdl/auto_script/tmp/width_combin_sdl.rb +0 -21
  414. data/lib/tdl/auto_script/tmp/width_convert_sdl.rb +0 -21
  415. data/lib/tdl/auto_script/tmp/xilinx_dna_capture_sdl.rb +0 -12
  416. data/lib/tdl/auto_script/tmp/xilinx_eth_clock_sdl.rb +0 -13
  417. data/lib/tdl/auto_script/tmp/xilinx_eth_reset_sdl.rb +0 -15
  418. data/lib/tdl/auto_script/tmp/xilinx_fifo_A1_sdl.rb +0 -22
  419. data/lib/tdl/auto_script/tmp/xilinx_fifo_sdl.rb +0 -20
  420. data/lib/tdl/auto_script/tmp/xilinx_fifo_verb_sdl.rb +0 -23
  421. data/lib/tdl/auto_script/tmp/xilinx_fifo_verc_sdl.rb +0 -21
  422. data/lib/tdl/auto_script/tmp/xilinx_hdl_dpram_sdl.rb +0 -29
  423. data/lib/tdl/auto_script/tmp/xilinx_hdl_dpram_sim_sdl.rb +0 -31
  424. data/lib/tdl/auto_script/tmp/xilinx_jtag_axil_wrapper_sdl.rb +0 -9
  425. data/lib/tdl/auto_script/tmp/xilinx_recfg_clock_multi_phase_ddr_wrapper_sdl.rb +0 -17
  426. data/lib/tdl/auto_script/tmp/xilinx_recfg_clock_multi_phase_wrapper_sdl.rb +0 -17
  427. data/lib/tdl/auto_script/tmp/xilinx_recfg_clock_phase_wrapper_sdl.rb +0 -17
  428. data/lib/tdl/auto_script/tmp/xilinx_recfg_clock_wrapper_sdl.rb +0 -13
  429. data/lib/tdl/auto_script/tmp/zynq_pl_common_dr_sensor_clk_sdl.rb +0 -13
  430. data/lib/tdl/auto_script/tmp/zynq_pl_common_lvds_sdl.rb +0 -18
data/lib/tdl/auto_script/tmp/common_axli_flow_sdl.rb DELETED
@@ -1,12 +0,0 @@
1
-
2
- # add_to_all_file_paths('common_axli_flow','/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/hand_2G5/common_axli_flow.sv')
3
- # real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/hand_2G5/common_axli_flow.sv'
4
- TdlBuild.common_axli_flow do
5
- self.real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/hand_2G5/common_axli_flow.sv'
6
- self.path = File.expand_path(__FILE__)
7
- parameter.LEN 10
8
- input - 'enable'
9
- input[ param.LEN][(63+8+1-0)] - 'flow_data'
10
- port.axi_lite_inf.master - 'ali'
11
- end
12
-
data/lib/tdl/auto_script/tmp/common_fifo_sdl.rb DELETED
@@ -1,22 +0,0 @@
1
-
2
- # add_to_all_file_paths('common_fifo','/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/common_fifo/common_fifo.sv')
3
- # real_sv_path = '/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/common_fifo/common_fifo.sv'
4
- TdlBuild.common_fifo do
5
- self.real_sv_path = '/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/common_fifo/common_fifo.sv'
6
- self.path = File.expand_path(__FILE__)
7
- parameter.DEPTH 4
8
- parameter.DSIZE 8
9
- parameter.DEFAULT_VALUES 0
10
- parameter.PSIZE NqString.new('$clog2(DEPTH)')
11
- parameter.CSIZE NqString.new('$clog2(DEPTH+1)')
12
- input - 'clock'
13
- input - 'rst_n'
14
- input[ param.DSIZE] - 'wdata'
15
- input - 'wr_en'
16
- output[ param.DSIZE] - 'rdata'
17
- input - 'rd_en'
18
- output[ param.CSIZE] - 'count'
19
- output - 'empty'
20
- output - 'full'
21
- end
22
-
data/lib/tdl/auto_script/tmp/common_redx_1xN_ddr_simple_sdl.rb DELETED
@@ -1,32 +0,0 @@
1
-
2
- # add_to_all_file_paths('common_redx_1xN_ddr_simple','/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/sensor_prim_lvds/inner_module/common_redx_1xN_ddr_simple.sv')
3
- # real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/sensor_prim_lvds/inner_module/common_redx_1xN_ddr_simple.sv'
4
- TdlBuild.common_redx_1xN_ddr_simple do
5
- self.real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/sensor_prim_lvds/inner_module/common_redx_1xN_ddr_simple.sv'
6
- self.path = File.expand_path(__FILE__)
7
- parameter.DIFF_TERM "TRUE"
8
- parameter.SENSOR_LVDS_IN_CLK "ON"
9
- parameter.NUM 6
10
- parameter.DR_SENSOR_CLK 2
11
- parameter.TARGET_FREQM 50
12
- parameter.SOURCE_FREQM 100
13
- parameter.MMCM_FREQM 1400
14
- parameter.HDIV 2
15
- parameter.LDIV 14
16
- parameter.NSIZE 14
17
- input - 'cpu_glbl_rstn'
18
- input - 'root_lvds_clock'
19
- input[ param.NUM] - 'lvds_data_p'
20
- input[ param.NUM] - 'lvds_data_n'
21
- input[ param.DR_SENSOR_CLK] - 'lvds_clock_p'
22
- input[ param.DR_SENSOR_CLK] - 'lvds_clock_n'
23
- output[ param.DR_SENSOR_CLK] - 'dr_sensor_clock_p'
24
- output[ param.DR_SENSOR_CLK] - 'dr_sensor_clock_n'
25
- output - 'lvds_logic_clock'
26
- input - 'sync'
27
- input - 'sample_win'
28
- output[ param.NUM*2] - 'lvds_data'
29
- output[ param.NUM*2] - 'lvds_data_vld'
30
- input - 'cross_lvds_clk'
31
- end
32
-
data/lib/tdl/auto_script/tmp/common_redx_1xN_sdr_serdes_simple_sdl.rb DELETED
@@ -1,31 +0,0 @@
1
-
2
- # add_to_all_file_paths('common_redx_1xN_sdr_serdes_simple','/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/sensor_prim_lvds/inner_module/common_redx_1xN_sdr_serdes_simple.sv')
3
- # real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/sensor_prim_lvds/inner_module/common_redx_1xN_sdr_serdes_simple.sv'
4
- TdlBuild.common_redx_1xN_sdr_serdes_simple do
5
- self.real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/sensor_prim_lvds/inner_module/common_redx_1xN_sdr_serdes_simple.sv'
6
- self.path = File.expand_path(__FILE__)
7
- parameter.DIFF_TERM "TRUE"
8
- parameter.SENSOR_LVDS_IN_CLK "ON"
9
- parameter.DR_SENSOR_CLK_EN "ON"
10
- parameter.NUM 6
11
- parameter.DR_SENSOR_CLK 2
12
- parameter.TARGET_FREQM 50
13
- parameter.SOURCE_FREQM 100
14
- parameter.MMCM_FREQM 1400
15
- parameter.HDIV 2
16
- parameter.LDIV 14
17
- parameter.NSIZE 14
18
- input - 'cpu_glbl_rstn'
19
- input - 'root_lvds_clock'
20
- input[ param.NUM] - 'lvds_data_p'
21
- input[ param.NUM] - 'lvds_data_n'
22
- input[ param.DR_SENSOR_CLK] - 'lvds_clock_p'
23
- input[ param.DR_SENSOR_CLK] - 'lvds_clock_n'
24
- input[ param.DR_SENSOR_CLK] - 'lvds_clock_inver_edge'
25
- output[ param.DR_SENSOR_CLK] - 'dr_sensor_clock_p'
26
- output[ param.DR_SENSOR_CLK] - 'dr_sensor_clock_n'
27
- output - 'lvds_logic_clock'
28
- output[ param.NUM] - 'lvds_data'
29
- output[ param.NUM] - 'lvds_data_vld'
30
- end
31
-
data/lib/tdl/auto_script/tmp/common_redx_1xN_sdr_simple_sdl.rb DELETED
@@ -1,32 +0,0 @@
1
-
2
- # add_to_all_file_paths('common_redx_1xN_sdr_simple','/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/sensor_prim_lvds/inner_module/common_redx_1xN_sdr_simple.sv')
3
- # real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/sensor_prim_lvds/inner_module/common_redx_1xN_sdr_simple.sv'
4
- TdlBuild.common_redx_1xN_sdr_simple do
5
- self.real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/sensor_prim_lvds/inner_module/common_redx_1xN_sdr_simple.sv'
6
- self.path = File.expand_path(__FILE__)
7
- parameter.DIFF_TERM "TRUE"
8
- parameter.SENSOR_LVDS_IN_CLK "ON"
9
- parameter.NUM 6
10
- parameter.DR_SENSOR_CLK 2
11
- parameter.TARGET_FREQM 50
12
- parameter.SOURCE_FREQM 100
13
- parameter.MMCM_FREQM 1400
14
- parameter.HDIV 2
15
- parameter.LDIV 14
16
- parameter.NSIZE 14
17
- input - 'cpu_glbl_rstn'
18
- input - 'root_lvds_clock'
19
- input[ param.NUM] - 'lvds_data_p'
20
- input[ param.NUM] - 'lvds_data_n'
21
- input[ param.DR_SENSOR_CLK] - 'lvds_clock_p'
22
- input[ param.DR_SENSOR_CLK] - 'lvds_clock_n'
23
- output[ param.DR_SENSOR_CLK] - 'dr_sensor_clock_p'
24
- output[ param.DR_SENSOR_CLK] - 'dr_sensor_clock_n'
25
- output - 'lvds_logic_clock'
26
- input - 'sync'
27
- input - 'sample_win'
28
- output[ param.NUM] - 'lvds_data'
29
- output[ param.NUM] - 'lvds_data_vld'
30
- input - 'cross_lvds_clk'
31
- end
32
-
data/lib/tdl/auto_script/tmp/cross_clk_sync_sdl.rb DELETED
@@ -1,14 +0,0 @@
1
-
2
- # add_to_all_file_paths('cross_clk_sync','/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/public_atom_module/cross_clk_sync.v')
3
- # real_sv_path = '/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/public_atom_module/cross_clk_sync.v'
4
- TdlBuild.cross_clk_sync do
5
- self.real_sv_path = '/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/public_atom_module/cross_clk_sync.v'
6
- self.path = File.expand_path(__FILE__)
7
- parameter.LAT 2
8
- parameter.DSIZE 1
9
- input - 'clk'
10
- input - 'rst_n'
11
- input[ param.DSIZE] - 'd'
12
- output[ param.DSIZE] - 'q'
13
- end
14
-
data/lib/tdl/auto_script/tmp/custom_serdes_router_sdl.rb DELETED
@@ -1,17 +0,0 @@
1
-
2
- # add_to_all_file_paths('custom_serdes_router','/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/hardware/manchester/custom_serdes_router.sv')
3
- # real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/hardware/manchester/custom_serdes_router.sv'
4
- TdlBuild.custom_serdes_router do
5
- self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/hardware/manchester/custom_serdes_router.sv'
6
- self.path = File.expand_path(__FILE__)
7
- parameter.NUM 32
8
- input - 'clock'
9
- input - 'sample_clk'
10
- input - 'sample_4clk'
11
- input - 'clk200M_ref'
12
- output[ param.NUM] - 'mch_dataout'
13
- input[ param.NUM] - 'mch_datain'
14
- port.axi_stream_inf.slaver - 'to_ct_databoard_inf'
15
- port.axi_stream_inf.master - 'from_ct_databoard_inf'
16
- end
17
-
data/lib/tdl/auto_script/tmp/data_c_cache_sdl.rb DELETED
@@ -1,10 +0,0 @@
1
-
2
- # add_to_all_file_paths('data_c_cache','/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/data_interface/data_inf_c/data_c_cache.sv')
3
- # real_sv_path = '/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/data_interface/data_inf_c/data_c_cache.sv'
4
- TdlBuild.data_c_cache do
5
- self.real_sv_path = '/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/data_interface/data_inf_c/data_c_cache.sv'
6
- self.path = File.expand_path(__FILE__)
7
- port.data_inf_c.slaver - 'data_in'
8
- port.data_inf_c.master - 'data_out'
9
- end
10
-
data/lib/tdl/auto_script/tmp/data_c_direct_sdl.rb DELETED
@@ -1,10 +0,0 @@
1
-
2
- # add_to_all_file_paths('data_c_direct','/var/lib/gems/2.7.0/gems/axi_tdl-0.2.4/lib/axi/data_interface/data_inf_c/data_c_direct.sv')
3
- # real_sv_path = '/var/lib/gems/2.7.0/gems/axi_tdl-0.2.4/lib/axi/data_interface/data_inf_c/data_c_direct.sv'
4
- TdlBuild.data_c_direct do
5
- self.real_sv_path = '/var/lib/gems/2.7.0/gems/axi_tdl-0.2.4/lib/axi/data_interface/data_inf_c/data_c_direct.sv'
6
- self.path = File.expand_path(__FILE__)
7
- port.data_inf_c.slaver - 'slaver'
8
- port.data_inf_c.master - 'master'
9
- end
10
-
data/lib/tdl/auto_script/tmp/data_c_pipe_force_vld_bind_data_sdl.rb DELETED
@@ -1,14 +0,0 @@
1
-
2
- # add_to_all_file_paths('data_c_pipe_force_vld_bind_data','/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/data_interface/data_inf_c/data_c_pipe_force_vld_bind_data.sv')
3
- # real_sv_path = '/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/data_interface/data_inf_c/data_c_pipe_force_vld_bind_data.sv'
4
- TdlBuild.data_c_pipe_force_vld_bind_data do
5
- self.real_sv_path = '/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/data_interface/data_inf_c/data_c_pipe_force_vld_bind_data.sv'
6
- self.path = File.expand_path(__FILE__)
7
- parameter.DSIZE 32
8
- parameter.HEAD_MODE "ON"
9
- parameter.SYNC "master"
10
- input[ param.DSIZE] - 'data'
11
- port.data_inf_c.slaver - 'slaver'
12
- port.data_inf_c.master - 'master'
13
- end
14
-
data/lib/tdl/auto_script/tmp/data_c_pipe_force_vld_sdl.rb DELETED
@@ -1,10 +0,0 @@
1
-
2
- # add_to_all_file_paths('data_c_pipe_force_vld','/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/data_interface/data_inf_c/data_c_pipe_force_vld.sv')
3
- # real_sv_path = '/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/data_interface/data_inf_c/data_c_pipe_force_vld.sv'
4
- TdlBuild.data_c_pipe_force_vld do
5
- self.real_sv_path = '/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/data_interface/data_inf_c/data_c_pipe_force_vld.sv'
6
- self.path = File.expand_path(__FILE__)
7
- port.data_inf_c.slaver - 'slaver'
8
- port.data_inf_c.master - 'master'
9
- end
10
-
data/lib/tdl/auto_script/tmp/data_c_pipe_inf_sdl.rb DELETED
@@ -1,10 +0,0 @@
1
-
2
- # add_to_all_file_paths('data_c_pipe_inf','/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/data_interface/data_inf_c/data_c_pipe_inf.sv')
3
- # real_sv_path = '/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/data_interface/data_inf_c/data_c_pipe_inf.sv'
4
- TdlBuild.data_c_pipe_inf do
5
- self.real_sv_path = '/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/data_interface/data_inf_c/data_c_pipe_inf.sv'
6
- self.path = File.expand_path(__FILE__)
7
- port.data_inf_c.slaver - 'slaver'
8
- port.data_inf_c.master - 'master'
9
- end
10
-
data/lib/tdl/auto_script/tmp/data_c_pipe_intc_M2S_best_robin_sdl.rb DELETED
@@ -1,12 +0,0 @@
1
-
2
- # add_to_all_file_paths('data_c_pipe_intc_M2S_best_robin','/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_best_robin.sv')
3
- # real_sv_path = '/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_best_robin.sv'
4
- TdlBuild.data_c_pipe_intc_M2S_best_robin do
5
- self.real_sv_path = '/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_best_robin.sv'
6
- self.path = File.expand_path(__FILE__)
7
- parameter.NUM 8
8
- parameter.NSIZE NqString.new('$clog2(NUM)')
9
- port.data_inf_c.slaver[ param.NUM] - 's00'
10
- port.data_inf_c.master - 'm00'
11
- end
12
-
data/lib/tdl/auto_script/tmp/data_c_pipe_sync_sdl.rb DELETED
@@ -1,13 +0,0 @@
1
-
2
- # add_to_all_file_paths('data_c_pipe_sync','/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/data_interface/data_inf_c/data_c_pipe_sync.sv')
3
- # real_sv_path = '/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/data_interface/data_inf_c/data_c_pipe_sync.sv'
4
- TdlBuild.data_c_pipe_sync do
5
- self.real_sv_path = '/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/data_interface/data_inf_c/data_c_pipe_sync.sv'
6
- self.path = File.expand_path(__FILE__)
7
- parameter.DSIZE 32
8
- input[ param.DSIZE] - 'in_data'
9
- output[ param.DSIZE] - 'out_data'
10
- port.data_inf_c.slaver - 'in_inf'
11
- port.data_inf_c.master - 'out_inf'
12
- end
13
-
data/lib/tdl/auto_script/tmp/data_c_sim_master_model_sdl.rb DELETED
@@ -1,15 +0,0 @@
1
-
2
- # add_to_all_file_paths('data_c_sim_master_model','/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/data_interface/data_inf_c/data_c_sim_master_model.sv')
3
- # real_sv_path = '/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/data_interface/data_inf_c/data_c_sim_master_model.sv'
4
- TdlBuild.data_c_sim_master_model do
5
- self.real_sv_path = '/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/data_interface/data_inf_c/data_c_sim_master_model.sv'
6
- self.path = File.expand_path(__FILE__)
7
- parameter.LOOP "TRUE"
8
- parameter.RAM_DEPTH 10000
9
- input - 'enable'
10
- input - 'load_trigger'
11
- input[32] - 'total_length'
12
- input[512*8] - 'mem_file'
13
- port.data_inf_c.master - 'out_inf'
14
- end
15
-
data/lib/tdl/auto_script/tmp/data_inf_c_intc_S2M_sdl.rb DELETED
@@ -1,13 +0,0 @@
1
-
2
- # add_to_all_file_paths('data_inf_c_intc_S2M','/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/data_interface/data_inf_c/data_inf_c_intc_S2M.sv')
3
- # real_sv_path = '/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/data_interface/data_inf_c/data_inf_c_intc_S2M.sv'
4
- TdlBuild.data_inf_c_intc_S2M do
5
- self.real_sv_path = '/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/data_interface/data_inf_c/data_inf_c_intc_S2M.sv'
6
- self.path = File.expand_path(__FILE__)
7
- parameter.NUM 8
8
- parameter.NSIZE NqString.new('$clog2(NUM)')
9
- input[ param.NSIZE] - 'addr'
10
- port.data_inf_c.master[ param.NUM] - 'm00'
11
- port.data_inf_c.slaver - 's00'
12
- end
13
-
data/lib/tdl/auto_script/tmp/data_inf_c_planer_A1_sdl.rb DELETED
@@ -1,15 +0,0 @@
1
-
2
- # add_to_all_file_paths('data_inf_c_planer_A1','/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/data_interface/data_inf_c/data_inf_c_planer_A1.sv')
3
- # real_sv_path = '/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/data_interface/data_inf_c/data_inf_c_planer_A1.sv'
4
- TdlBuild.data_inf_c_planer_A1 do
5
- self.real_sv_path = '/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/data_interface/data_inf_c/data_inf_c_planer_A1.sv'
6
- self.path = File.expand_path(__FILE__)
7
- parameter.LAT 3
8
- parameter.DSIZE 8
9
- parameter.HEAD "FALSE"
10
- input - 'reset'
11
- input[ param.DSIZE] - 'pack_data'
12
- port.data_inf_c.slaver - 'slaver'
13
- port.data_inf_c.master - 'master'
14
- end
15
-
data/lib/tdl/auto_script/tmp/data_lvds_bitslip_sdl.rb DELETED
@@ -1,12 +0,0 @@
1
-
2
- # add_to_all_file_paths('data_lvds_bitslip','/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/hardware/dyn_lvds_bitslip/data_lvds_bitslip.sv')
3
- # real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/hardware/dyn_lvds_bitslip/data_lvds_bitslip.sv'
4
- TdlBuild.data_lvds_bitslip do
5
- self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/hardware/dyn_lvds_bitslip/data_lvds_bitslip.sv'
6
- self.path = File.expand_path(__FILE__)
7
- input - 'reset'
8
- input - 'sample_clock'
9
- input - 'lvds_data_in'
10
- output - 'sample_data'
11
- end
12
-
data/lib/tdl/auto_script/tmp/data_lvds_simple_bitslip_sdl.rb DELETED
@@ -1,12 +0,0 @@
1
-
2
- # add_to_all_file_paths('data_lvds_simple_bitslip','/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/hardware/dyn_lvds_bitslip/data_lvds_simple_bitslip.sv')
3
- # real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/hardware/dyn_lvds_bitslip/data_lvds_simple_bitslip.sv'
4
- TdlBuild.data_lvds_simple_bitslip do
5
- self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/hardware/dyn_lvds_bitslip/data_lvds_simple_bitslip.sv'
6
- self.path = File.expand_path(__FILE__)
7
- input - 'reset'
8
- input - 'sample_clock'
9
- input - 'lvds_data_in'
10
- output - 'sample_data'
11
- end
12
-
data/lib/tdl/auto_script/tmp/data_mirrors_sdl.rb DELETED
@@ -1,15 +0,0 @@
1
-
2
- # add_to_all_file_paths('data_mirrors','/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/data_interface/data_inf_c/data_mirrors.sv')
3
- # real_sv_path = '/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/data_interface/data_inf_c/data_mirrors.sv'
4
- TdlBuild.data_mirrors do
5
- self.real_sv_path = '/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/data_interface/data_inf_c/data_mirrors.sv'
6
- self.path = File.expand_path(__FILE__)
7
- parameter.H 0
8
- parameter.L 0
9
- parameter.NUM 8
10
- parameter.MODE "CDS_MODE"
11
- input[( param.H+1- param.L)] - 'condition_data'
12
- port.data_inf_c.slaver - 'data_in'
13
- port.data_inf_c.master[ param.NUM] - 'data_mirror'
14
- end
15
-
data/lib/tdl/auto_script/tmp/datainf_c_slaver_empty_sdl.rb DELETED
@@ -1,9 +0,0 @@
1
-
2
- # add_to_all_file_paths('datainf_c_slaver_empty','/var/lib/gems/2.7.0/gems/axi_tdl-0.2.4/lib/axi/data_interface/datainf_c_slaver_empty.sv')
3
- # real_sv_path = '/var/lib/gems/2.7.0/gems/axi_tdl-0.2.4/lib/axi/data_interface/datainf_c_slaver_empty.sv'
4
- TdlBuild.datainf_c_slaver_empty do
5
- self.real_sv_path = '/var/lib/gems/2.7.0/gems/axi_tdl-0.2.4/lib/axi/data_interface/datainf_c_slaver_empty.sv'
6
- self.path = File.expand_path(__FILE__)
7
- port.data_inf_c.slaver - 'slaver'
8
- end
9
-
data/lib/tdl/auto_script/tmp/ddr3_ip_wrapper_sdl.rb DELETED
@@ -1,28 +0,0 @@
1
-
2
- # add_to_all_file_paths('ddr3_ip_wrapper','/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/hardware/mamo676_clk_ddr/ddr3/ddr3_ip_wrapper.sv')
3
- # real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/hardware/mamo676_clk_ddr/ddr3/ddr3_ip_wrapper.sv'
4
- TdlBuild.ddr3_ip_wrapper do
5
- self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/hardware/mamo676_clk_ddr/ddr3/ddr3_ip_wrapper.sv'
6
- self.path = File.expand_path(__FILE__)
7
- parameter.MARK_X "OFF"
8
- input - 'ddr_ref_200M'
9
- input - 'ddr_rst'
10
- output - 'driver_axi4_clk'
11
- output - 'driver_axi4_rst'
12
- inout[16] - 'ddr3_dq'
13
- inout[2] - 'ddr3_dqs_n'
14
- inout[2] - 'ddr3_dqs_p'
15
- output[15] - 'ddr3_addr'
16
- output[3] - 'ddr3_ba'
17
- output - 'ddr3_ras_n'
18
- output - 'ddr3_cas_n'
19
- output - 'ddr3_we_n'
20
- output - 'ddr3_reset_n'
21
- output[1] - 'ddr3_ck_p'
22
- output[1] - 'ddr3_ck_n'
23
- output[1] - 'ddr3_cke'
24
- output[2] - 'ddr3_dm'
25
- output[1] - 'ddr3_odt'
26
- port.axi_inf.slaver - 'caxi_inf'
27
- end
28
-
data/lib/tdl/auto_script/tmp/ddr_axi4_to_axis_sdl.rb DELETED
@@ -1,11 +0,0 @@
1
-
2
- # add_to_all_file_paths('ddr_axi4_to_axis','/var/lib/gems/2.7.0/gems/axi_tdl-0.2.4/lib/axi/axi4_to_xilinx_ddr_native/ddr_axi4_to_axis.sv')
3
- # real_sv_path = '/var/lib/gems/2.7.0/gems/axi_tdl-0.2.4/lib/axi/axi4_to_xilinx_ddr_native/ddr_axi4_to_axis.sv'
4
- TdlBuild.ddr_axi4_to_axis do
5
- self.real_sv_path = '/var/lib/gems/2.7.0/gems/axi_tdl-0.2.4/lib/axi/axi4_to_xilinx_ddr_native/ddr_axi4_to_axis.sv'
6
- self.path = File.expand_path(__FILE__)
7
- port.axi_stream_inf.master - 'axis_inf'
8
- port.axi_stream_inf.slaver - 'axis_rd_inf'
9
- port.axi_inf.slaver - 'axi4_inf'
10
- end
11
-
data/lib/tdl/auto_script/tmp/det_moto_findex_sdl.rb DELETED
@@ -1,13 +0,0 @@
1
-
2
- # add_to_all_file_paths('det_moto_findex','/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/hardware/itgt_det/det_moto_findex.sv')
3
- # real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/hardware/itgt_det/det_moto_findex.sv'
4
- TdlBuild.det_moto_findex do
5
- self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/hardware/itgt_det/det_moto_findex.sv'
6
- self.path = File.expand_path(__FILE__)
7
- input - 'reset_findex'
8
- input - 'exp_start_stable_falling'
9
- input[8][32] - 'moto_dist_array'
10
- input[32] - 'moto_dist_tail'
11
- port.data_inf_c.master - 'det_move_inf'
12
- end
13
-
data/lib/tdl/auto_script/tmp/det_start_block_sdl.rb DELETED
@@ -1,17 +0,0 @@
1
-
2
- # add_to_all_file_paths('det_start_block','/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/hardware/itgt_det/det_start_block.sv')
3
- # real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/hardware/itgt_det/det_start_block.sv'
4
- TdlBuild.det_start_block do
5
- self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/hardware/itgt_det/det_start_block.sv'
6
- self.path = File.expand_path(__FILE__)
7
- parameter.SYS_CLK_FREQ 100
8
- input - 'clock'
9
- input - 'rst_n'
10
- input - 'exp_start'
11
- output - 'exp_start_stable'
12
- output - 'exp_start_stable_raising'
13
- output - 'exp_start_stable_falling'
14
- port.data_inf_c.master - 'req_frame_inf'
15
- port.data_inf_c.master - 'power_up_or_down_inf'
16
- end
17
-
data/lib/tdl/auto_script/tmp/det_start_filter_sdl.rb DELETED
@@ -1,15 +0,0 @@
1
-
2
- # add_to_all_file_paths('det_start_filter','/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/hardware/itgt_det/det_start_filter.sv')
3
- # real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/hardware/itgt_det/det_start_filter.sv'
4
- TdlBuild.det_start_filter do
5
- self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/hardware/itgt_det/det_start_filter.sv'
6
- self.path = File.expand_path(__FILE__)
7
- parameter.SYS_CLK_FREQ 100
8
- input - 'clock'
9
- input - 'rst_n'
10
- input - 'exp_start'
11
- output - 'exp_start_stable'
12
- output - 'exp_start_stable_raising'
13
- output - 'exp_start_stable_falling'
14
- end
15
-
data/lib/tdl/auto_script/tmp/det_with_pre_A3_sdl.rb DELETED
@@ -1,28 +0,0 @@
1
-
2
- # add_to_all_file_paths('det_with_pre_A3','/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/hardware/itgt_det/det_with_pre_A3.sv')
3
- # real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/hardware/itgt_det/det_with_pre_A3.sv'
4
- TdlBuild.det_with_pre_A3 do
5
- self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/hardware/itgt_det/det_with_pre_A3.sv'
6
- self.path = File.expand_path(__FILE__)
7
- output - 'exp_ready'
8
- input - 'exp_start'
9
- output - 'det_data'
10
- output - 'det_pos0'
11
- output - 'det_pos1'
12
- output - 'sensor_sync'
13
- input[8] - 'moto_curr_status'
14
- output[2] - 'sensor_xlocal'
15
- output - 'sensor_xlocal_valid'
16
- port.axi_stream_inf.mirror - 'ctrl_tap_inf'
17
- port.axi_stream_inf.master - 'to_ctrl_tap_in_inf'
18
- port.axi_stream_inf.master - 'msg_axis_inf'
19
- port.data_inf_c.master - 'det_move_inf'
20
- port.data_inf_c.mirror - 'move_done_inf'
21
- port.data_inf_c.master - 'req_frame_inf'
22
- port.data_inf_c.mirror - 'req_frame_done_inf'
23
- port.data_inf_c.mirror - 'sync_done_trigger_inf'
24
- port.data_inf_c.master - 'power_up_or_down_inf'
25
- port.data_inf_c.master - 'hight_voltage_ctrl_inf'
26
- port.data_inf_c.master - 'avdd_1v2_en_ctrl_inf'
27
- end
28
-
data/lib/tdl/auto_script/tmp/det_with_pre_A4_sdl.rb DELETED
@@ -1,28 +0,0 @@
1
-
2
- # add_to_all_file_paths('det_with_pre_A4','/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/hardware/itgt_det/det_with_pre_A4.sv')
3
- # real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/hardware/itgt_det/det_with_pre_A4.sv'
4
- TdlBuild.det_with_pre_A4 do
5
- self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/hardware/itgt_det/det_with_pre_A4.sv'
6
- self.path = File.expand_path(__FILE__)
7
- output - 'exp_ready'
8
- input - 'exp_start'
9
- output - 'det_data'
10
- output - 'det_pos0'
11
- output - 'det_pos1'
12
- output - 'sensor_sync'
13
- input[8] - 'moto_curr_status'
14
- output[2] - 'sensor_xlocal'
15
- output - 'sensor_xlocal_valid'
16
- port.axi_stream_inf.mirror - 'ctrl_tap_inf'
17
- port.axi_stream_inf.master - 'to_ctrl_tap_in_inf'
18
- port.axi_stream_inf.master - 'msg_axis_inf'
19
- port.data_inf_c.master - 'det_move_inf'
20
- port.data_inf_c.mirror - 'move_done_inf'
21
- port.data_inf_c.master - 'req_frame_inf'
22
- port.data_inf_c.mirror - 'req_frame_done_inf'
23
- port.data_inf_c.mirror - 'sync_done_trigger_inf'
24
- port.data_inf_c.master - 'power_up_or_down_inf'
25
- port.data_inf_c.master - 'hight_voltage_ctrl_inf'
26
- port.data_inf_c.master - 'avdd_1v2_en_ctrl_inf'
27
- end
28
-
data/lib/tdl/auto_script/tmp/det_with_pre_B1_sdl.rb DELETED
@@ -1,29 +0,0 @@
1
-
2
- # add_to_all_file_paths('det_with_pre_B1','/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/hardware/itgt_det/det_with_pre_B1.sv')
3
- # real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/hardware/itgt_det/det_with_pre_B1.sv'
4
- TdlBuild.det_with_pre_B1 do
5
- self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/hardware/itgt_det/det_with_pre_B1.sv'
6
- self.path = File.expand_path(__FILE__)
7
- output - 'exp_ready'
8
- input - 'exp_start'
9
- input - 'soft_start'
10
- output - 'det_data'
11
- output - 'det_pos0'
12
- output - 'det_pos1'
13
- output - 'sensor_sync'
14
- input[8] - 'moto_curr_status'
15
- output[2] - 'sensor_xlocal'
16
- output - 'sensor_xlocal_valid'
17
- port.axi_stream_inf.mirror - 'ctrl_tap_inf'
18
- port.axi_stream_inf.master - 'to_ctrl_tap_in_inf'
19
- port.axi_stream_inf.master - 'msg_axis_inf'
20
- port.data_inf_c.master - 'det_move_inf'
21
- port.data_inf_c.mirror - 'move_done_inf'
22
- port.data_inf_c.master - 'req_frame_inf'
23
- port.data_inf_c.mirror - 'req_frame_done_inf'
24
- port.data_inf_c.mirror - 'sync_done_trigger_inf'
25
- port.data_inf_c.master - 'power_up_or_down_inf'
26
- port.data_inf_c.master - 'hight_voltage_ctrl_inf'
27
- port.data_inf_c.master - 'avdd_1v2_en_ctrl_inf'
28
- end
29
-
data/lib/tdl/auto_script/tmp/det_with_pre_findex_sdl.rb DELETED
@@ -1,18 +0,0 @@
1
-
2
- # add_to_all_file_paths('det_with_pre_findex','/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/hardware/itgt_det/laux/det_with_pre_findex.sv')
3
- # real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/hardware/itgt_det/laux/det_with_pre_findex.sv'
4
- TdlBuild.det_with_pre_findex do
5
- self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/hardware/itgt_det/laux/det_with_pre_findex.sv'
6
- self.path = File.expand_path(__FILE__)
7
- input - 'reset_findex'
8
- input - 'exp_start'
9
- input - 'soft_start'
10
- output - 'sensor_sync'
11
- port.axi_stream_inf.mirror - 'ctrl_tap_inf'
12
- port.axi_stream_inf.master - 'to_ctrl_tap_in_inf'
13
- port.data_inf_c.master - 'det_move_inf'
14
- port.data_inf_c.mirror - 'move_done_inf'
15
- port.data_inf_c.master - 'req_frame_inf'
16
- port.data_inf_c.mirror - 'sync_done_trigger_inf'
17
- end
18
-
data/lib/tdl/auto_script/tmp/det_with_pre_verb_sdl.rb DELETED
@@ -1,29 +0,0 @@
1
-
2
- # add_to_all_file_paths('det_with_pre_verb','/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/hardware/itgt_det/det_with_pre_verb.sv')
3
- # real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/hardware/itgt_det/det_with_pre_verb.sv'
4
- TdlBuild.det_with_pre_verb do
5
- self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/hardware/itgt_det/det_with_pre_verb.sv'
6
- self.path = File.expand_path(__FILE__)
7
- output - 'exp_ready'
8
- input - 'exp_start'
9
- input - 'soft_start'
10
- output - 'det_data'
11
- output - 'det_pos0'
12
- output - 'det_pos1'
13
- output - 'sensor_sync'
14
- input[8] - 'moto_curr_status'
15
- output[2] - 'sensor_xlocal'
16
- output - 'sensor_xlocal_valid'
17
- port.axi_stream_inf.mirror - 'ctrl_tap_inf'
18
- port.axi_stream_inf.master - 'to_ctrl_tap_in_inf'
19
- port.axi_stream_inf.master - 'msg_axis_inf'
20
- port.data_inf_c.master - 'det_move_inf'
21
- port.data_inf_c.mirror - 'move_done_inf'
22
- port.data_inf_c.master - 'req_frame_inf'
23
- port.data_inf_c.mirror - 'req_frame_done_inf'
24
- port.data_inf_c.mirror - 'sync_done_trigger_inf'
25
- port.data_inf_c.master - 'power_up_or_down_inf'
26
- port.data_inf_c.master - 'hight_voltage_ctrl_inf'
27
- port.data_inf_c.master - 'avdd_1v2_en_ctrl_inf'
28
- end
29
-
data/lib/tdl/auto_script/tmp/diffr_multi_phase_sample_sdl.rb DELETED
@@ -1,17 +0,0 @@
1
-
2
- # add_to_all_file_paths('diffr_multi_phase_sample','/media/kali/DATA2/work/BK/work/FPGA/red8_1x6_20230925/git_repo/hardware/diffr_lvds/dyn_lvds_bitslip/diffr_multi_phase_sample.sv')
3
- # real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/red8_1x6_20230925/git_repo/hardware/diffr_lvds/dyn_lvds_bitslip/diffr_multi_phase_sample.sv'
4
- TdlBuild.diffr_multi_phase_sample do
5
- self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/red8_1x6_20230925/git_repo/hardware/diffr_lvds/dyn_lvds_bitslip/diffr_multi_phase_sample.sv'
6
- self.path = File.expand_path(__FILE__)
7
- input - 'bf_data_i'
8
- input - 'bf_data_ib'
9
- input - 'clk_100M_phs22'
10
- input - 'clk_100M_phs45'
11
- input[4] - 'sel_sample'
12
- input - 'inner_clock'
13
- input - 'inner_rstn'
14
- output - 'bf_data'
15
- output - 'bf_data_vld'
16
- end
17
-