axi_tdl 0.2.7 → 0.2.10

data/lib/tdl/auto_script/tmp/diffr_reg_tpu_v3_wrapper_sdl.rb

@@ -1,17 +0,0 @@
-
-# add_to_all_file_paths('diffr_reg_tpu_v3_wrapper','/media/kali/DATA2/work/BK/work/FPGA/red8_1x6_20230925/git_repo/tpu_app/diffr_reg_tpu/diffr_reg_tpu_v3_wrapper.sv')
-# real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/red8_1x6_20230925/git_repo/tpu_app/diffr_reg_tpu/diffr_reg_tpu_v3_wrapper.sv'
-TdlBuild.diffr_reg_tpu_v3_wrapper do 
-self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/red8_1x6_20230925/git_repo/tpu_app/diffr_reg_tpu/diffr_reg_tpu_v3_wrapper.sv'
-self.path = File.expand_path(__FILE__)
-output - 'spi_mosi' 
-input - 'spi_miso' 
-output - 'spi_sclk' 
-output - 'spi_csn' 
-port.axi_stream_inf.mirror - 'ctrl_tap_inf' 
-port.axi_stream_inf.master - 'to_ctrl_tap_in_inf' 
-port.data_inf_c.slaver - 'set_reg_inf' 
-port.data_inf_c.slaver - 'req_reg_inf' 
-port.data_inf_c.master - 'reg_data_inf' 
-end
-

data/lib/tdl/auto_script/tmp/diffr_reg_tpu_wrapper_sdl.rb

@@ -1,16 +0,0 @@
-
-# add_to_all_file_paths('diffr_reg_tpu_wrapper','/media/kali/DATA2/work/BK/work/FPGA/red8_1x6_20230925/git_repo/tpu_app/diffr_reg_tpu/diffr_reg_tpu_wrapper.sv')
-# real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/red8_1x6_20230925/git_repo/tpu_app/diffr_reg_tpu/diffr_reg_tpu_wrapper.sv'
-TdlBuild.diffr_reg_tpu_wrapper do 
-self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/red8_1x6_20230925/git_repo/tpu_app/diffr_reg_tpu/diffr_reg_tpu_wrapper.sv'
-self.path = File.expand_path(__FILE__)
-output[4] - 'cspi_mosi' 
-input[4] - 'cspi_miso' 
-output[4] - 'cspi_sclk' 
-output[4] - 'cspi_csn' 
-port.axi_stream_inf.mirror - 'ctrl_tap_inf' 
-port.axi_stream_inf.master - 'to_ctrl_tap_in_inf' 
-port.axi_stream_inf.master - 'axis_out_inf' 
-port.data_inf_c.master - 'cspi_cs_ctrl_inf' 
-end
-

data/lib/tdl/auto_script/tmp/diffr_reg_tpu_wrapper_v2_sdl.rb

@@ -1,16 +0,0 @@
-
-# add_to_all_file_paths('diffr_reg_tpu_wrapper_v2','/media/kali/DATA2/work/BK/work/FPGA/red8_1x6_20230925/git_repo/tpu_app/diffr_reg_tpu/diffr_reg_tpu_wrapper_v2.sv')
-# real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/red8_1x6_20230925/git_repo/tpu_app/diffr_reg_tpu/diffr_reg_tpu_wrapper_v2.sv'
-TdlBuild.diffr_reg_tpu_wrapper_v2 do 
-self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/red8_1x6_20230925/git_repo/tpu_app/diffr_reg_tpu/diffr_reg_tpu_wrapper_v2.sv'
-self.path = File.expand_path(__FILE__)
-output[8] - 'cspi_mosi' 
-input[8] - 'cspi_miso' 
-output[8] - 'cspi_sclk' 
-output[8] - 'cspi_csn' 
-port.axi_stream_inf.mirror - 'ctrl_tap_inf' 
-port.axi_stream_inf.master - 'to_ctrl_tap_in_inf' 
-port.axi_stream_inf.master - 'axis_out_inf' 
-port.data_inf_c.master - 'cspi_cs_ctrl_inf' 
-end
-

data/lib/tdl/auto_script/tmp/dire_accese_flash_sdl.rb

@@ -1,17 +0,0 @@
-
-# add_to_all_file_paths('dire_accese_flash','/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/fpga_dire_flash/dire_accese_flash.sv')
-# real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/fpga_dire_flash/dire_accese_flash.sv'
-TdlBuild.dire_accese_flash do 
-self.real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/fpga_dire_flash/dire_accese_flash.sv'
-self.path = File.expand_path(__FILE__)
-parameter.FLAG   "16'hAA2"
-parameter.EDIV   6
-output - 'spi_csn' 
-output - 'spi_mosi' 
-input - 'spi_miso' 
-output - 'spi_hold' 
-output - 'spi_wp' 
-port.axi_stream_inf.mirror - 'ctrl_tap_inf' 
-port.axi_stream_inf.master - 'to_ctrl_tap_in_inf' 
-end
-

data/lib/tdl/auto_script/tmp/dyn_edge_clock_sdl.rb

@@ -1,15 +0,0 @@
-
-# add_to_all_file_paths('dyn_edge_clock','/media/kali/DATA2/work/BK/work/FPGA/mamo_x7_20250512_recall/git_repo/hardware/dyn_edge_sample/dyn_edge_clock.sv')
-# real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/mamo_x7_20250512_recall/git_repo/hardware/dyn_edge_sample/dyn_edge_clock.sv'
-TdlBuild.dyn_edge_clock do 
-self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/mamo_x7_20250512_recall/git_repo/hardware/dyn_edge_sample/dyn_edge_clock.sv'
-self.path = File.expand_path(__FILE__)
-input - 'rx_clock' 
-input - 'rx_data' 
-input - 'reset' 
-input - 'sample_clock' 
-input - 'system_clk' 
-output - 'sample_data' 
-output - 'sync_sample_data' 
-end
-

data/lib/tdl/auto_script/tmp/edge_generator_sdl.rb

@@ -1,14 +0,0 @@
-
-# add_to_all_file_paths('edge_generator','/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/public_atom_module/edge_generator.v')
-# real_sv_path = '/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/public_atom_module/edge_generator.v'
-TdlBuild.edge_generator do 
-self.real_sv_path = '/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/public_atom_module/edge_generator.v'
-self.path = File.expand_path(__FILE__)
-parameter.MODE   "NORMAL"
-input - 'clk' 
-input - 'rst_n' 
-input - 'in' 
-output - 'raising' 
-output - 'falling' 
-end
-

data/lib/tdl/auto_script/tmp/eth4_chip_reg_wrapper_sdl.rb

@@ -1,20 +0,0 @@
-
-# add_to_all_file_paths('eth4_chip_reg_wrapper','/media/kali/DATA2/work/BK/work/FPGA/Red8_x4_Eth4_20240923/git_repo/tpu_app/Eth4_chip_reg/eth4_chip_reg_wrapper.sv')
-# real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/Red8_x4_Eth4_20240923/git_repo/tpu_app/Eth4_chip_reg/eth4_chip_reg_wrapper.sv'
-TdlBuild.eth4_chip_reg_wrapper do 
-self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/Red8_x4_Eth4_20240923/git_repo/tpu_app/Eth4_chip_reg/eth4_chip_reg_wrapper.sv'
-self.path = File.expand_path(__FILE__)
-output[4] - 'cspi_mosi' 
-input[4] - 'cspi_miso' 
-output[2] - 'cspi_sclk' 
-output[2] - 'cspi_csn' 
-output - 'avdd_chip_en' 
-output - 'sensor_hardware_rstn' 
-input[16] - 'pc_port' 
-port.axi_stream_inf.mirror - 'ctrl_tap_inf' 
-port.axi_stream_inf.master - 'to_ctrl_tap_in_inf' 
-port.axi_stream_inf.master - 'axis_out_inf' 
-port.data_inf_c.slaver - 'power_up_or_down_inf' 
-port.data_inf_c.slaver - 'ex_avdd_chip_en_inf' 
-end
-

data/lib/tdl/auto_script/tmp/eth4_lvds_tb_block_sdl.rb

@@ -1,16 +0,0 @@
-
-# add_to_all_file_paths('eth4_lvds_tb_block','/media/kali/DATA2/work/BK/work/FPGA/Red8_x4_Eth4_20240923/git_repo/hardware/eth4_chip_lvds/eth4_lvds_tb_block.sv')
-# real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/Red8_x4_Eth4_20240923/git_repo/hardware/eth4_chip_lvds/eth4_lvds_tb_block.sv'
-TdlBuild.eth4_lvds_tb_block do 
-self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/Red8_x4_Eth4_20240923/git_repo/hardware/eth4_chip_lvds/eth4_lvds_tb_block.sv'
-self.path = File.expand_path(__FILE__)
-parameter.HEAD   "20'b0000_0000_10100111"
-parameter.BITS   8
-parameter.LENGTH   256*256
-input - 'clock' 
-input - 'rst_n' 
-input - 'cs' 
-output - 'lvds_data_p' 
-output - 'lvds_data_n' 
-end
-

data/lib/tdl/auto_script/tmp/eth4_sensor_driver_array_sdl.rb

@@ -1,17 +0,0 @@
-
-# add_to_all_file_paths('eth4_sensor_driver_array','/media/kali/DATA2/work/BK/work/FPGA/Red8_x4_Eth4_20240923/git_repo/hardware/eth4_chip_lvds/clock/eth4_sensor_driver_array.sv')
-# real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/Red8_x4_Eth4_20240923/git_repo/hardware/eth4_chip_lvds/clock/eth4_sensor_driver_array.sv'
-TdlBuild.eth4_sensor_driver_array do 
-self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/Red8_x4_Eth4_20240923/git_repo/hardware/eth4_chip_lvds/clock/eth4_sensor_driver_array.sv'
-self.path = File.expand_path(__FILE__)
-parameter.NUM   4
-input - 'origin_clock_100M' 
-output[ param.NUM] - 'sensor_lvds_dr_clock_p' 
-output[ param.NUM] - 'sensor_lvds_dr_clock_n' 
-output - 'fabri_clk_50M' 
-output - 'fabri_rstn_50M' 
-output - 'fabri_clk_100M' 
-output - 'fabri_rstn_100M' 
-output - 'fabri_clk_200M' 
-end
-

data/lib/tdl/auto_script/tmp/eth4_single_chip_Red2S_lvds_dir_sdl.rb

@@ -1,16 +0,0 @@
-
-# add_to_all_file_paths('eth4_single_chip_Red2S_lvds_dir','/media/kali/DATA2/work/BK/work/FPGA/Red8_x4_Eth4_20240923/git_repo/hardware/eth4_chip_lvds/eth4_single_chip_Red2S_lvds_dir.sv')
-# real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/Red8_x4_Eth4_20240923/git_repo/hardware/eth4_chip_lvds/eth4_single_chip_Red2S_lvds_dir.sv'
-TdlBuild.eth4_single_chip_Red2S_lvds_dir do 
-self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/Red8_x4_Eth4_20240923/git_repo/hardware/eth4_chip_lvds/eth4_single_chip_Red2S_lvds_dir.sv'
-self.path = File.expand_path(__FILE__)
-input - 'cpu_glbl_rstn' 
-input[8] - 'sensor2fpga_lvds_data_p' 
-input[8] - 'sensor2fpga_lvds_data_n' 
-input - 'sensor2fpga_lvds_clock_p' 
-input - 'sensor2fpga_lvds_clock_n' 
-output - 'sensor_lvds_clock' 
-output - 'sensor_lvds_rstn' 
-output[16] - 'sensor_lvds_data' 
-end
-

data/lib/tdl/auto_script/tmp/eth_2g5_wrapper_sdl.rb

@@ -1,25 +0,0 @@
-
-# add_to_all_file_paths('eth_2g5_wrapper','/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/hand_2G5/simple_sub_system/eth_2g5_wrapper.sv')
-# real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/hand_2G5/simple_sub_system/eth_2g5_wrapper.sv'
-TdlBuild.eth_2g5_wrapper do 
-self.real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/hand_2G5/simple_sub_system/eth_2g5_wrapper.sv'
-self.path = File.expand_path(__FILE__)
-output - 'rx_mac_aclk' 
-output - 'rx_reset' 
-output - 'tx_mac_aclk' 
-output - 'tx_reset' 
-input - 'glbl_rstn' 
-input - 'ref_clk_200M' 
-input - 'sgmii_rxn' 
-input - 'sgmii_rxp' 
-output - 'sgmii_txn' 
-output - 'sgmii_txp' 
-input - 'mgt_clk_clk_p' 
-input - 'mgt_clk_clk_n' 
-output - 'mdc' 
-inout - 'mdio' 
-port.axi_stream_inf.master - 'rx_axis_inf' 
-port.axi_stream_inf.slaver - 'tx_axis_inf' 
-port.axi_lite_inf.slaver - 'ali' 
-end
-

data/lib/tdl/auto_script/tmp/eth_outShare_wrapper_sdl.rb

@@ -1,28 +0,0 @@
-
-# add_to_all_file_paths('eth_outShare_wrapper','/media/kali/DATA2/work/BK/work/FPGA/Red8_x4_Eth4_20240923/git_repo/hardware/multi_ethernet_1g/eth_outShare_wrapper.sv')
-# real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/Red8_x4_Eth4_20240923/git_repo/hardware/multi_ethernet_1g/eth_outShare_wrapper.sv'
-TdlBuild.eth_outShare_wrapper do 
-self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/Red8_x4_Eth4_20240923/git_repo/hardware/multi_ethernet_1g/eth_outShare_wrapper.sv'
-self.path = File.expand_path(__FILE__)
-input - 'mac_init_req' 
-input - 'mac_1G_req' 
-input - 'mac_100M_req' 
-input - 'mac_10M_req' 
-output - 'mac_config_done' 
-input - 'gtx_clk' 
-input - 'gtx_clk90' 
-input - 'axi_lite_clk' 
-input - 'glbl_rstn' 
-output[4] - 'rgmii_txd' 
-output - 'rgmii_tx_ctl' 
-output - 'rgmii_txc' 
-input[4] - 'rgmii_rxd' 
-input - 'rgmii_rx_ctl' 
-input - 'rgmii_rxc' 
-inout - 'mdio' 
-output - 'mdc' 
-input[48] - 'mac_addr' 
-port.axi_stream_inf.master - 'rx_mac_inf' 
-port.axi_stream_inf.slaver - 'tx_mac_inf' 
-end
-

data/lib/tdl/auto_script/tmp/eth_to_ddr_with_ack_sdl.rb

@@ -1,13 +0,0 @@
-
-# add_to_all_file_paths('eth_to_ddr_with_ack','/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/software/eth_to_ddr/eth_to_ddr_with_ack.sv')
-# real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/software/eth_to_ddr/eth_to_ddr_with_ack.sv'
-TdlBuild.eth_to_ddr_with_ack do 
-self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/software/eth_to_ddr/eth_to_ddr_with_ack.sv'
-self.path = File.expand_path(__FILE__)
-parameter.FLAG   "16'hD03"
-parameter.DDR_INF_DSIZE   128
-port.axi_stream_inf.mirror - 'ctrl_tap_inf' 
-port.axi_stream_inf.master - 'to_ctrl_tap_in_inf' 
-port.axi_inf.master_wr - 'wr_to_ddr_inf' 
-end
-

data/lib/tdl/auto_script/tmp/eth_to_spi_verb_sdl.rb

@@ -1,20 +0,0 @@
-
-# add_to_all_file_paths('eth_to_spi_verb','/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/hardware/fast_spi/eth_to_spi_verb.sv')
-# real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/hardware/fast_spi/eth_to_spi_verb.sv'
-TdlBuild.eth_to_spi_verb do 
-self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/hardware/fast_spi/eth_to_spi_verb.sv'
-self.path = File.expand_path(__FILE__)
-parameter.FLAG   "16'h1BF"
-parameter.DSIZE   8
-parameter.ASIZE   8
-parameter.FreQM   "100.0"
-parameter.SCK_FreQM   "50.0"
-output - 'spi_cs' 
-output - 'spi_sclk' 
-input - 'spi_miso' 
-output - 'spi_mosi' 
-port.axi_stream_inf.mirror - 'ctrl_tap_inf' 
-port.axi_stream_inf.master - 'to_ctrl_tap_in_inf' 
-port.data_inf_c.master - 'switch_tri_inf' 
-end
-

data/lib/tdl/auto_script/tmp/eth_to_standard_spi_with_ack_sdl.rb

@@ -1,17 +0,0 @@
-
-# add_to_all_file_paths('eth_to_standard_spi_with_ack','/media/kali/DATA2/work/BK/work/FPGA/A7_2x4_20240826/git_repo/hardware/fpga_spi_2x4/eth_to_standard_spi_with_ack.sv')
-# real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/A7_2x4_20240826/git_repo/hardware/fpga_spi_2x4/eth_to_standard_spi_with_ack.sv'
-TdlBuild.eth_to_standard_spi_with_ack do 
-self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/A7_2x4_20240826/git_repo/hardware/fpga_spi_2x4/eth_to_standard_spi_with_ack.sv'
-self.path = File.expand_path(__FILE__)
-parameter.FLAG   "16'h1BF"
-parameter.EDIV   4                
-output - 'spi_cs' 
-output - 'spi_sclk' 
-input - 'spi_miso' 
-output - 'spi_mosi' 
-port.axi_stream_inf.mirror - 'ctrl_tap_inf' 
-port.axi_stream_inf.master - 'to_ctrl_tap_in_inf' 
-port.data_inf_c.master - 'switch_tri_inf' 
-end
-

data/lib/tdl/auto_script/tmp/eth_to_standard_uart_with_ack_sdl.rb

@@ -1,16 +0,0 @@
-
-# add_to_all_file_paths('eth_to_standard_uart_with_ack','/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/uart_stream/eth_to_standard_uart_with_ack.sv')
-# real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/uart_stream/eth_to_standard_uart_with_ack.sv'
-TdlBuild.eth_to_standard_uart_with_ack do 
-self.real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/uart_stream/eth_to_standard_uart_with_ack.sv'
-self.path = File.expand_path(__FILE__)
-parameter.FLAG   "16'h1BF"
-parameter.CLK_FREQM   125
-parameter.BAUD_RATE   115200
-output - 'uart_tx' 
-input - 'uart_rx' 
-output - 'ctrl_rx_tx' 
-port.axi_stream_inf.mirror - 'ctrl_tap_inf' 
-port.axi_stream_inf.master - 'to_ctrl_tap_in_inf' 
-end
-

data/lib/tdl/auto_script/tmp/eth_xilinx_ip_sdl.rb

@@ -1,22 +0,0 @@
-
-# add_to_all_file_paths('eth_xilinx_ip','/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/jlw0708/eth_with_xilinx_rgmii/eth_xilinx_ip.sv')
-# real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/jlw0708/eth_with_xilinx_rgmii/eth_xilinx_ip.sv'
-TdlBuild.eth_xilinx_ip do 
-self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/jlw0708/eth_with_xilinx_rgmii/eth_xilinx_ip.sv'
-self.path = File.expand_path(__FILE__)
-input - 'sys_clk_100M' 
-input - 'axi_aclk' 
-input - 'axi_aresetn' 
-input - 'rgmii_rxc' 
-input - 'rgmii_rx_ctl' 
-input[4] - 'rgmii_rxd' 
-output - 'rgmii_txc' 
-output - 'rgmii_tx_ctl' 
-output[4] - 'rgmii_txd' 
-output - 'e_reset' 
-inout - 'mdio' 
-output - 'mdc' 
-port.axi_stream_inf.slaver - 'axis_tx' 
-port.axi_stream_inf.master - 'axis_rx' 
-end
-

data/lib/tdl/auto_script/tmp/ethernet_wrapper_2d5G_sdl.rb

@@ -1,28 +0,0 @@
-
-# add_to_all_file_paths('ethernet_wrapper_2d5G','/media/kali/DATA2/work/BK/work/FPGA/A7_2x4_20240826/git_repo/hardware/itgt_ethernet_1g/ethernet_wrapper_2d5G.sv')
-# real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/A7_2x4_20240826/git_repo/hardware/itgt_ethernet_1g/ethernet_wrapper_2d5G.sv'
-TdlBuild.ethernet_wrapper_2d5G do 
-self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/A7_2x4_20240826/git_repo/hardware/itgt_ethernet_1g/ethernet_wrapper_2d5G.sv'
-self.path = File.expand_path(__FILE__)
-input - 'mac_init_req' 
-input - 'mac_1G_req' 
-input - 'mac_100M_req' 
-input - 'mac_10M_req' 
-output - 'mac_config_done' 
-input - 'gtx_clk' 
-input - 'axi_lite_clk' 
-input - 'refclk_200M' 
-input - 'glbl_rstn' 
-input - 'sgmii_rxn' 
-input - 'sgmii_rxp' 
-output - 'sgmii_txn' 
-output - 'sgmii_txp' 
-output - 'mdio_mdc' 
-input - 'mgt_clk_clk_n' 
-input - 'mgt_clk_clk_p' 
-inout - 'mdio' 
-input[48] - 'mac_addr' 
-port.axi_stream_inf.master - 'rx_mac_inf' 
-port.axi_stream_inf.slaver - 'tx_mac_inf' 
-end
-

data/lib/tdl/auto_script/tmp/ethernet_wrapper_sdl.rb

@@ -1,28 +0,0 @@
-
-# add_to_all_file_paths('ethernet_wrapper','/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/itgt_ethernet_1g/ethernet_wrapper.sv')
-# real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/itgt_ethernet_1g/ethernet_wrapper.sv'
-TdlBuild.ethernet_wrapper do 
-self.real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/itgt_ethernet_1g/ethernet_wrapper.sv'
-self.path = File.expand_path(__FILE__)
-input - 'mac_init_req' 
-input - 'mac_1G_req' 
-input - 'mac_100M_req' 
-input - 'mac_10M_req' 
-output - 'mac_config_done' 
-input - 'gtx_clk' 
-input - 'axi_lite_clk' 
-input - 'refclk_200M' 
-input - 'glbl_rstn' 
-output[4] - 'rgmii_txd' 
-output - 'rgmii_tx_ctl' 
-output - 'rgmii_txc' 
-input[4] - 'rgmii_rxd' 
-input - 'rgmii_rx_ctl' 
-input - 'rgmii_rxc' 
-inout - 'mdio' 
-output - 'mdc' 
-input[48] - 'mac_addr' 
-port.axi_stream_inf.master - 'rx_mac_inf' 
-port.axi_stream_inf.slaver - 'tx_mac_inf' 
-end
-

data/lib/tdl/auto_script/tmp/ethernet_wrapper_track_sdl.rb

@@ -1,28 +0,0 @@
-
-# add_to_all_file_paths('ethernet_wrapper_track','/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/itgt_ethernet_1g/ethernet_wrapper_track.sv')
-# real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/itgt_ethernet_1g/ethernet_wrapper_track.sv'
-TdlBuild.ethernet_wrapper_track do 
-self.real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/itgt_ethernet_1g/ethernet_wrapper_track.sv'
-self.path = File.expand_path(__FILE__)
-input - 'mac_init_req' 
-input - 'mac_1G_req' 
-input - 'mac_100M_req' 
-input - 'mac_10M_req' 
-output - 'mac_config_done' 
-input - 'gtx_clk' 
-input - 'axi_lite_clk' 
-input - 'refclk_200M' 
-input - 'glbl_rstn' 
-output[4] - 'rgmii_txd' 
-output - 'rgmii_tx_ctl' 
-output - 'rgmii_txc' 
-input[4] - 'rgmii_rxd' 
-input - 'rgmii_rx_ctl' 
-input - 'rgmii_rxc' 
-inout - 'mdio' 
-output - 'mdc' 
-input[48] - 'mac_addr' 
-port.axi_stream_inf.master - 'rx_mac_inf' 
-port.axi_stream_inf.slaver - 'tx_mac_inf' 
-end
-

data/lib/tdl/auto_script/tmp/ext_sync_filter_sdl.rb

@@ -1,14 +0,0 @@
-
-# add_to_all_file_paths('ext_sync_filter','/media/kali/DATA2/work/BK/work/FPGA/Big8_20230619/git_repo/hardware/boneQ_share_signals/ext_sync_filter.sv')
-# real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/Big8_20230619/git_repo/hardware/boneQ_share_signals/ext_sync_filter.sv'
-TdlBuild.ext_sync_filter do 
-self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/Big8_20230619/git_repo/hardware/boneQ_share_signals/ext_sync_filter.sv'
-self.path = File.expand_path(__FILE__)
-input - 'reset_sync_cnt' 
-input - 'ext_sync' 
-output - 'ext_sync_stable' 
-output - 'ext_reset_sync_cnt' 
-port.axi_stream_inf.mirror - 'ctrl_tap_inf' 
-port.axi_stream_inf.master - 'to_ctrl_tap_in_inf' 
-end
-

data/lib/tdl/auto_script/tmp/fifo_36kb_long_sdl.rb

@@ -1,20 +0,0 @@
-
-# add_to_all_file_paths('fifo_36kb_long','/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/platform_ip/fifo_36kb_long.sv')
-# real_sv_path = '/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/platform_ip/fifo_36kb_long.sv'
-TdlBuild.fifo_36kb_long do 
-self.real_sv_path = '/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/platform_ip/fifo_36kb_long.sv'
-self.path = File.expand_path(__FILE__)
-parameter.DSIZE   32
-parameter.DEPTH   8000
-input - 'wr_clk' 
-input - 'wr_rst' 
-input - 'rd_clk' 
-input - 'rd_rst' 
-input[ param.DSIZE] - 'din' 
-input - 'wr_en' 
-input - 'rd_en' 
-output[ param.DSIZE] - 'dout' 
-output - 'full' 
-output - 'empty' 
-end
-

data/lib/tdl/auto_script/tmp/fifo_73_96bit_sdl.rb

@@ -1,19 +0,0 @@
-
-# add_to_all_file_paths('fifo_73_96bit','/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/platform_ip/fifo_73_96bit.sv')
-# real_sv_path = '/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/platform_ip/fifo_73_96bit.sv'
-TdlBuild.fifo_73_96bit do 
-self.real_sv_path = '/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/platform_ip/fifo_73_96bit.sv'
-self.path = File.expand_path(__FILE__)
-parameter.DSIZE   96
-input - 'wr_clk' 
-input - 'wr_rst' 
-input - 'rd_clk' 
-input - 'rd_rst' 
-input[ param.DSIZE] - 'din' 
-input - 'wr_en' 
-input - 'rd_en' 
-output[ param.DSIZE] - 'dout' 
-output - 'full' 
-output - 'empty' 
-end
-

data/lib/tdl/auto_script/tmp/four_chips_Red5_lvds_dir_sdl.rb

@@ -1,15 +0,0 @@
-
-# add_to_all_file_paths('four_chips_Red5_lvds_dir','/media/kali/DATA2/work/BK/work/FPGA/Big8_20230920/git_repo/hardware/four_red5_lvds/four_chips_Red5_lvds_dir.sv')
-# real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/Big8_20230920/git_repo/hardware/four_red5_lvds/four_chips_Red5_lvds_dir.sv'
-TdlBuild.four_chips_Red5_lvds_dir do 
-self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/Big8_20230920/git_repo/hardware/four_red5_lvds/four_chips_Red5_lvds_dir.sv'
-self.path = File.expand_path(__FILE__)
-parameter.LAN_NUM   16
-input[ param.LAN_NUM] - 'sensor2fpga_lvds_data_p' 
-input[ param.LAN_NUM] - 'sensor2fpga_lvds_data_n' 
-input[ param.LAN_NUM] - 'sensor2fpga_lvds_clock_p' 
-input[ param.LAN_NUM] - 'sensor2fpga_lvds_clock_n' 
-output[ param.LAN_NUM] - 'sensor_lvds_clock' 
-output[ param.LAN_NUM] - 'sensor_lvds_data' 
-end
-

data/lib/tdl/auto_script/tmp/four_chips_Red5_lvds_pins_delay_sdl.rb

@@ -1,20 +0,0 @@
-
-# add_to_all_file_paths('four_chips_Red5_lvds_pins_delay','/media/kali/DATA2/work/BK/work/FPGA/Big8_20230920/git_repo/hardware/four_red5_lvds/four_chips_Red5_lvds_pins_delay.sv')
-# real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/Big8_20230920/git_repo/hardware/four_red5_lvds/four_chips_Red5_lvds_pins_delay.sv'
-TdlBuild.four_chips_Red5_lvds_pins_delay do 
-self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/Big8_20230920/git_repo/hardware/four_red5_lvds/four_chips_Red5_lvds_pins_delay.sv'
-self.path = File.expand_path(__FILE__)
-parameter.IDLY_CTRL   "ON"
-parameter.NAME_DELAY   0
-parameter.DAT_NAME_DELAY   "16'b0000_0000"
-parameter.CLK_NAME_DELAY   "16'b0000_0000"
-parameter.LAN_NUM   4
-input - 'ref_200M' 
-input[ param.LAN_NUM] - 'sensor2fpga_lvds_data_p' 
-input[ param.LAN_NUM] - 'sensor2fpga_lvds_data_n' 
-input[ param.LAN_NUM] - 'sensor2fpga_lvds_clock_p' 
-input[ param.LAN_NUM] - 'sensor2fpga_lvds_clock_n' 
-output[ param.LAN_NUM] - 'sensor_lvds_clock' 
-output[ param.LAN_NUM] - 'sensor_lvds_data' 
-end
-

data/lib/tdl/auto_script/tmp/full_axi4_to_axis_partition_wr_rd_sdl.rb

@@ -1,12 +0,0 @@
-
-# add_to_all_file_paths('full_axi4_to_axis_partition_wr_rd','/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/AXI4/full_axi4_to_axis_partition_wr_rd.sv')
-# real_sv_path = '/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/AXI4/full_axi4_to_axis_partition_wr_rd.sv'
-TdlBuild.full_axi4_to_axis_partition_wr_rd do 
-self.real_sv_path = '/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/AXI4/full_axi4_to_axis_partition_wr_rd.sv'
-self.path = File.expand_path(__FILE__)
-port.axi_stream_inf.master - 'axis_wr_inf' 
-port.axi_stream_inf.master - 'axis_rd_inf' 
-port.axi_stream_inf.slaver - 'axis_rd_rel_inf' 
-port.axi_inf.slaver - 'xaxi4_inf' 
-end
-

data/lib/tdl/auto_script/tmp/full_axi4_to_axis_sdl.rb

@@ -1,11 +0,0 @@
-
-# add_to_all_file_paths('full_axi4_to_axis','/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/AXI4/full_axi4_to_axis.sv')
-# real_sv_path = '/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/AXI4/full_axi4_to_axis.sv'
-TdlBuild.full_axi4_to_axis do 
-self.real_sv_path = '/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/AXI4/full_axi4_to_axis.sv'
-self.path = File.expand_path(__FILE__)
-port.axi_stream_inf.master - 'axis_inf' 
-port.axi_stream_inf.slaver - 'axis_rd_inf' 
-port.axi_inf.slaver - 'xaxi4_inf' 
-end
-

data/lib/tdl/auto_script/tmp/gen_big_field_table_sdl.rb

@@ -1,15 +0,0 @@
-
-# add_to_all_file_paths('gen_big_field_table','/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/AXI_stream/gen_big_field_table.sv')
-# real_sv_path = '/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/AXI_stream/gen_big_field_table.sv'
-TdlBuild.gen_big_field_table do 
-self.real_sv_path = '/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/AXI_stream/gen_big_field_table.sv'
-self.path = File.expand_path(__FILE__)
-parameter.MASTER_MODE   "OFF"
-parameter.DSIZE   8
-parameter.FIELD_LEN   16*8
-parameter.FIELD_NAME   "Big Filed"
-input - 'enable' 
-input[ param.DSIZE* param.FIELD_LEN] - 'value' 
-port.axi_stream_inf.master - 'cm_tb' 
-end
-

data/lib/tdl/auto_script/tmp/gen_common_frame_table_sdl.rb

@@ -1,61 +0,0 @@
-
-# add_to_all_file_paths('gen_common_frame_table','/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/AXI_stream/gen_common_frame_table.sv')
-# real_sv_path = '/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/AXI_stream/gen_common_frame_table.sv'
-TdlBuild.gen_common_frame_table do 
-self.real_sv_path = '/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/AXI_stream/gen_common_frame_table.sv'
-self.path = File.expand_path(__FILE__)
-parameter.MASTER_MODE   "OFF"
-parameter.FIELD_TOTLE   11
-parameter.DSIZE   8
-parameter.F0_LEN   1
-parameter.F0_NAME   "version+head length"
-parameter.F1_LEN   1
-parameter.F1_NAME   "TOS"
-parameter.F2_LEN   2
-parameter.F2_NAME   "totle length"
-parameter.F3_LEN   2
-parameter.F3_NAME   "identify"
-parameter.F4_LEN   1
-parameter.F4_NAME   "flag + offset MSB"
-parameter.F5_LEN   1
-parameter.F5_NAME   "offset LSB"
-parameter.F6_LEN   1
-parameter.F6_NAME   "TTL"
-parameter.F7_LEN   1
-parameter.F7_NAME   "sub protocol"
-parameter.F8_LEN   2
-parameter.F8_NAME   "head CRC"
-parameter.F9_LEN   4
-parameter.F9_NAME   "source ip addr"
-parameter.F10_LEN   4
-parameter.F10_NAME   "destination ip addr"
-parameter.F11_LEN   1
-parameter.F11_NAME   "Filed 11"
-parameter.F12_LEN   1
-parameter.F12_NAME   "Filed 12"
-parameter.F13_LEN   1
-parameter.F13_NAME   "Field 13"
-parameter.F14_LEN   1
-parameter.F14_NAME   "Field 14"
-parameter.F15_LEN   1
-parameter.F15_NAME   "Field 15"
-input - 'enable' 
-input[( param.F0_LEN * param.DSIZE-1+1-0)] - 'f0_value' 
-input[( param.F1_LEN * param.DSIZE-1+1-0)] - 'f1_value' 
-input[( param.F2_LEN * param.DSIZE-1+1-0)] - 'f2_value' 
-input[( param.F3_LEN * param.DSIZE-1+1-0)] - 'f3_value' 
-input[( param.F4_LEN * param.DSIZE-1+1-0)] - 'f4_value' 
-input[( param.F5_LEN * param.DSIZE-1+1-0)] - 'f5_value' 
-input[( param.F6_LEN * param.DSIZE-1+1-0)] - 'f6_value' 
-input[( param.F7_LEN * param.DSIZE-1+1-0)] - 'f7_value' 
-input[( param.F8_LEN * param.DSIZE-1+1-0)] - 'f8_value' 
-input[( param.F9_LEN * param.DSIZE-1+1-0)] - 'f9_value' 
-input[ param.F10_LEN* param.DSIZE] - 'f10_value' 
-input[ param.F11_LEN* param.DSIZE] - 'f11_value' 
-input[ param.F12_LEN* param.DSIZE] - 'f12_value' 
-input[ param.F13_LEN* param.DSIZE] - 'f13_value' 
-input[ param.F14_LEN* param.DSIZE] - 'f14_value' 
-input[ param.F15_LEN* param.DSIZE] - 'f15_value' 
-port.axi_stream_inf.master - 'cm_tb' 
-end
-