axi_tdl 0.2.7 → 0.2.10

data/lib/tdl/auto_script/tmp/cbct_lock_lvds_data_sdl.rb

@@ -1,16 +0,0 @@
-
-# add_to_all_file_paths('cbct_lock_lvds_data','/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/single_chip_lvds/cbct_lock_lvds_data.sv')
-# real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/single_chip_lvds/cbct_lock_lvds_data.sv'
-TdlBuild.cbct_lock_lvds_data do 
-self.real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/single_chip_lvds/cbct_lock_lvds_data.sv'
-self.path = File.expand_path(__FILE__)
-parameter.HEAD_FLAG   "16'b0000_0000_1010_0111"
-parameter.DATA_LENGTH   18*288
-input - 'serial_clock' 
-input - 'serial_rstn' 
-input - 'serial_data' 
-input[2] - 'bits_sel' 
-input - 'sync' 
-port.axi_stream_inf.master - 'paralle_data_inf' 
-end
-

data/lib/tdl/auto_script/tmp/cbct_sensor_driver_array_sdl.rb

@@ -1,12 +0,0 @@
-
-# add_to_all_file_paths('cbct_sensor_driver_array','/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/single_chip_lvds/clock/cbct_sensor_driver_array.sv')
-# real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/single_chip_lvds/clock/cbct_sensor_driver_array.sv'
-TdlBuild.cbct_sensor_driver_array do 
-self.real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/single_chip_lvds/clock/cbct_sensor_driver_array.sv'
-self.path = File.expand_path(__FILE__)
-parameter.NUM   4
-input - 'origin_clock_100M' 
-output[ param.NUM] - 'sensor_lvds_dr_clock_p' 
-output[ param.NUM] - 'sensor_lvds_dr_clock_n' 
-end
-

data/lib/tdl/auto_script/tmp/cbct_sensor_driver_clock_A1_sdl.rb

@@ -1,13 +0,0 @@
-
-# add_to_all_file_paths('cbct_sensor_driver_clock_A1','/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/single_chip_lvds/clock/cbct_sensor_driver_clock_A1.sv')
-# real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/single_chip_lvds/clock/cbct_sensor_driver_clock_A1.sv'
-TdlBuild.cbct_sensor_driver_clock_A1 do 
-self.real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/single_chip_lvds/clock/cbct_sensor_driver_clock_A1.sv'
-self.path = File.expand_path(__FILE__)
-input - 'sensor_lvds_50_200M' 
-input - 'sensor_drive_clk_en' 
-input - 'data' 
-output - 'lvds_clock_p' 
-output - 'lvds_clock_n' 
-end
-

data/lib/tdl/auto_script/tmp/cbct_sensor_driver_clock_sdl.rb

@@ -1,12 +0,0 @@
-
-# add_to_all_file_paths('cbct_sensor_driver_clock','/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/single_chip_lvds/clock/cbct_sensor_driver_clock.sv')
-# real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/single_chip_lvds/clock/cbct_sensor_driver_clock.sv'
-TdlBuild.cbct_sensor_driver_clock do 
-self.real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/single_chip_lvds/clock/cbct_sensor_driver_clock.sv'
-self.path = File.expand_path(__FILE__)
-input - 'sensor_lvds_50_200M' 
-input - 'sensor_drive_clk_en' 
-output - 'lvds_clock_p' 
-output - 'lvds_clock_n' 
-end
-

data/lib/tdl/auto_script/tmp/cbct_single_sensor_lvds_dir_sdl.rb

@@ -1,14 +0,0 @@
-
-# add_to_all_file_paths('cbct_single_sensor_lvds_dir','/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/single_chip_lvds/cbct_single_sensor_lvds_dir.sv')
-# real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/single_chip_lvds/cbct_single_sensor_lvds_dir.sv'
-TdlBuild.cbct_single_sensor_lvds_dir do 
-self.real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/single_chip_lvds/cbct_single_sensor_lvds_dir.sv'
-self.path = File.expand_path(__FILE__)
-input - 'sensor2fpga_lvds_data_p' 
-input - 'sensor2fpga_lvds_data_n' 
-input - 'sensor2fpga_lvds_clock_p' 
-input - 'sensor2fpga_lvds_clock_n' 
-output - 'sensor_lvds_clock' 
-output - 'sensor_lvds_data' 
-end
-

data/lib/tdl/auto_script/tmp/chip_reg_tpu_phase_upgrade_sdl.rb

@@ -1,25 +0,0 @@
-
-# add_to_all_file_paths('chip_reg_tpu_phase_upgrade','/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/tpu_app/chip_reg_tpu/compile_out/chip_reg_tpu_phase_upgrade.sv')
-# real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/tpu_app/chip_reg_tpu/compile_out/chip_reg_tpu_phase_upgrade.sv'
-TdlBuild.chip_reg_tpu_phase_upgrade do 
-self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/tpu_app/chip_reg_tpu/compile_out/chip_reg_tpu_phase_upgrade.sv'
-self.path = File.expand_path(__FILE__)
-parameter.UPGRADE_FLAG   "16'hb3"
-output - 'cspi_mosi' 
-output[4] - 'cspi_sclk' 
-output[8] - 'cspi_csn' 
-output[1] - 'cspi_sample' 
-output[4] - 'cspi_miso_pd_addr' 
-input[16] - 'cspi_miso_pd' 
-input[1] - 'read_reg_require' 
-input[16] - 'read_reg_addr_data' 
-input[1] - 'write_reg_require' 
-input[16] - 'write_reg_addr_data' 
-input[16] - 'udp_ack_tap_flag' 
-output[1] - 'clear_read_req' 
-output[1] - 'clear_write_req' 
-port.axi_stream_inf.master - 'axis_out_inf' 
-port.axi_stream_inf.mirror - 'ctrl_tap_inf' 
-port.axi_stream_inf.master - 'to_ctrl_tap_in_inf' 
-end
-

data/lib/tdl/auto_script/tmp/chip_reg_tpu_wrapper_gray_sdl.rb

@@ -1,24 +0,0 @@
-
-# add_to_all_file_paths('chip_reg_tpu_wrapper_gray','/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/tpu_app/chip_reg_tpu/chip_reg_tpu_wrapper_gray.sv')
-# real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/tpu_app/chip_reg_tpu/chip_reg_tpu_wrapper_gray.sv'
-TdlBuild.chip_reg_tpu_wrapper_gray do 
-self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/tpu_app/chip_reg_tpu/chip_reg_tpu_wrapper_gray.sv'
-self.path = File.expand_path(__FILE__)
-input - 'hardware_rstn' 
-input[8] - 'moto_curr_status' 
-input[3] - 'curr_board_cs_code' 
-input - 'curr_sync' 
-output[6] - 'cspi_mosi' 
-input[12] - 'cspi_miso' 
-output[6] - 'cspi_sclk' 
-output[12] - 'cspi_csn' 
-output[2] - 'avdd_chip_en' 
-port.axi_stream_inf.mirror - 'ctrl_tap_inf' 
-port.axi_stream_inf.master - 'to_ctrl_tap_in_inf' 
-port.axi_stream_inf.master - 'axis_out_inf' 
-port.data_inf_c.slaver - 'power_up_or_down_inf' 
-port.data_inf_c.slaver - 'ex_avdd_chip_en_inf' 
-port.data_inf_c.master - 'cspi_cs_ctrl_inf' 
-port.data_inf_c.out_mirror - 'mirror_set_reg_status_inf' 
-end
-

data/lib/tdl/auto_script/tmp/chip_reg_tpu_wrapper_sdl.rb

@@ -1,25 +0,0 @@
-
-# add_to_all_file_paths('chip_reg_tpu_wrapper','/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/tpu_app/chip_reg_tpu/chip_reg_tpu_wrapper.sv')
-# real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/tpu_app/chip_reg_tpu/chip_reg_tpu_wrapper.sv'
-TdlBuild.chip_reg_tpu_wrapper do 
-self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/tpu_app/chip_reg_tpu/chip_reg_tpu_wrapper.sv'
-self.path = File.expand_path(__FILE__)
-input - 'hardware_rstn' 
-input[8] - 'moto_curr_status' 
-input[3] - 'curr_board_cs_code' 
-input - 'curr_sync' 
-output[6] - 'cspi_mosi' 
-input[12] - 'cspi_miso' 
-output[6] - 'cspi_sclk' 
-output[12] - 'cspi_csn' 
-output[2] - 'avdd_chip_en' 
-output[6] - 'cspi_board_cs' 
-port.axi_stream_inf.mirror - 'ctrl_tap_inf' 
-port.axi_stream_inf.master - 'to_ctrl_tap_in_inf' 
-port.axi_stream_inf.master - 'axis_out_inf' 
-port.data_inf_c.slaver - 'power_up_or_down_inf' 
-port.data_inf_c.slaver - 'ex_avdd_chip_en_inf' 
-port.data_inf_c.master - 'cspi_cs_ctrl_inf' 
-port.data_inf_c.out_mirror - 'mirror_set_reg_status_inf' 
-end
-

data/lib/tdl/auto_script/tmp/chip_reg_tpu_wrapper_slot_gray_sdl.rb

@@ -1,24 +0,0 @@
-
-# add_to_all_file_paths('chip_reg_tpu_wrapper_slot_gray','/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/tpu_app/chip_reg_tpu/chip_reg_tpu_wrapper_slot_gray.sv')
-# real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/tpu_app/chip_reg_tpu/chip_reg_tpu_wrapper_slot_gray.sv'
-TdlBuild.chip_reg_tpu_wrapper_slot_gray do 
-self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/tpu_app/chip_reg_tpu/chip_reg_tpu_wrapper_slot_gray.sv'
-self.path = File.expand_path(__FILE__)
-input - 'hardware_rstn' 
-input[8] - 'moto_curr_status' 
-input[3] - 'curr_board_cs_code' 
-input - 'curr_sync' 
-output[5] - 'cspi_mosi' 
-input[10] - 'cspi_miso' 
-output[5] - 'cspi_sclk' 
-output[5] - 'cspi_csn' 
-output[2] - 'avdd_chip_en' 
-port.axi_stream_inf.mirror - 'ctrl_tap_inf' 
-port.axi_stream_inf.master - 'to_ctrl_tap_in_inf' 
-port.axi_stream_inf.master - 'axis_out_inf' 
-port.data_inf_c.slaver - 'power_up_or_down_inf' 
-port.data_inf_c.slaver - 'ex_avdd_chip_en_inf' 
-port.data_inf_c.master - 'cspi_cs_ctrl_inf' 
-port.data_inf_c.out_mirror - 'mirror_set_reg_status_inf' 
-end
-

data/lib/tdl/auto_script/tmp/chip_reg_tpu_wrapper_speci_gray_sdl.rb

@@ -1,24 +0,0 @@
-
-# add_to_all_file_paths('chip_reg_tpu_wrapper_speci_gray','/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/tpu_app/chip_reg_tpu/chip_reg_tpu_wrapper_speci_gray.sv')
-# real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/tpu_app/chip_reg_tpu/chip_reg_tpu_wrapper_speci_gray.sv'
-TdlBuild.chip_reg_tpu_wrapper_speci_gray do 
-self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/tpu_app/chip_reg_tpu/chip_reg_tpu_wrapper_speci_gray.sv'
-self.path = File.expand_path(__FILE__)
-input - 'hardware_rstn' 
-input[8] - 'moto_curr_status' 
-input[3] - 'curr_board_cs_code' 
-input - 'curr_sync' 
-output[4] - 'cspi_mosi' 
-input[8] - 'cspi_miso' 
-output[4] - 'cspi_sclk' 
-output[4] - 'cspi_csn' 
-output[2] - 'avdd_chip_en' 
-port.axi_stream_inf.mirror - 'ctrl_tap_inf' 
-port.axi_stream_inf.master - 'to_ctrl_tap_in_inf' 
-port.axi_stream_inf.master - 'axis_out_inf' 
-port.data_inf_c.slaver - 'power_up_or_down_inf' 
-port.data_inf_c.slaver - 'ex_avdd_chip_en_inf' 
-port.data_inf_c.master - 'cspi_cs_ctrl_inf' 
-port.data_inf_c.out_mirror - 'mirror_set_reg_status_inf' 
-end
-

data/lib/tdl/auto_script/tmp/chip_reg_tpu_wrapper_verb_sdl.rb

@@ -1,24 +0,0 @@
-
-# add_to_all_file_paths('chip_reg_tpu_wrapper_verb','/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/tpu_app/chip_reg_tpu/chip_reg_tpu_wrapper_verb.sv')
-# real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/tpu_app/chip_reg_tpu/chip_reg_tpu_wrapper_verb.sv'
-TdlBuild.chip_reg_tpu_wrapper_verb do 
-self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/tpu_app/chip_reg_tpu/chip_reg_tpu_wrapper_verb.sv'
-self.path = File.expand_path(__FILE__)
-input - 'hardware_rstn' 
-input[8] - 'moto_curr_status' 
-input[3] - 'curr_board_cs_code' 
-input - 'curr_sync' 
-output[6] - 'cspi_mosi' 
-input[12] - 'cspi_miso' 
-output[6] - 'cspi_sclk' 
-output[12] - 'cspi_csn' 
-output[2] - 'avdd_chip_en' 
-port.axi_stream_inf.mirror - 'ctrl_tap_inf' 
-port.axi_stream_inf.master - 'to_ctrl_tap_in_inf' 
-port.axi_stream_inf.master - 'axis_out_inf' 
-port.data_inf_c.slaver - 'power_up_or_down_inf' 
-port.data_inf_c.slaver - 'ex_avdd_chip_en_inf' 
-port.data_inf_c.master - 'cspi_cs_ctrl_inf' 
-port.data_inf_c.out_mirror - 'mirror_set_reg_status_inf' 
-end
-

data/lib/tdl/auto_script/tmp/chip_reg_tpu_wrapper_x7_gray_sdl.rb

@@ -1,24 +0,0 @@
-
-# add_to_all_file_paths('chip_reg_tpu_wrapper_x7_gray','/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/tpu_app/chip_reg_tpu/chip_reg_tpu_wrapper_x7_gray.sv')
-# real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/tpu_app/chip_reg_tpu/chip_reg_tpu_wrapper_x7_gray.sv'
-TdlBuild.chip_reg_tpu_wrapper_x7_gray do 
-self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/tpu_app/chip_reg_tpu/chip_reg_tpu_wrapper_x7_gray.sv'
-self.path = File.expand_path(__FILE__)
-input - 'hardware_rstn' 
-input[8] - 'moto_curr_status' 
-input[3] - 'curr_board_cs_code' 
-input - 'curr_sync' 
-output[7] - 'cspi_mosi' 
-input[14] - 'cspi_miso' 
-output[7] - 'cspi_sclk' 
-output[14] - 'cspi_csn' 
-output[2] - 'avdd_chip_en' 
-port.axi_stream_inf.mirror - 'ctrl_tap_inf' 
-port.axi_stream_inf.master - 'to_ctrl_tap_in_inf' 
-port.axi_stream_inf.master - 'axis_out_inf' 
-port.data_inf_c.slaver - 'power_up_or_down_inf' 
-port.data_inf_c.slaver - 'ex_avdd_chip_en_inf' 
-port.data_inf_c.master - 'cspi_cs_ctrl_inf' 
-port.data_inf_c.out_mirror - 'mirror_set_reg_status_inf' 
-end
-

data/lib/tdl/auto_script/tmp/chip_spi_model_sdl.rb

@@ -1,12 +0,0 @@
-
-# add_to_all_file_paths('chip_spi_model','/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/fpga_dire_flash/chip_spi_model.sv')
-# real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/fpga_dire_flash/chip_spi_model.sv'
-TdlBuild.chip_spi_model do 
-self.real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/fpga_dire_flash/chip_spi_model.sv'
-self.path = File.expand_path(__FILE__)
-input - 'spi_sclk' 
-input - 'spi_csn' 
-input - 'spi_mosi' 
-output - 'spi_miso' 
-end
-

data/lib/tdl/auto_script/tmp/clock_lvds_bitslip_sdl.rb

@@ -1,13 +0,0 @@
-
-# add_to_all_file_paths('clock_lvds_bitslip','/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/hardware/dyn_lvds_bitslip/clock_lvds_bitslip.sv')
-# real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/hardware/dyn_lvds_bitslip/clock_lvds_bitslip.sv'
-TdlBuild.clock_lvds_bitslip do 
-self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/hardware/dyn_lvds_bitslip/clock_lvds_bitslip.sv'
-self.path = File.expand_path(__FILE__)
-parameter.EDGE   "POSITIVE"
-input - 'reset' 
-input - 'sample_clock' 
-input - 'lvds_clock_in' 
-output - 'sample_enable' 
-end
-

data/lib/tdl/auto_script/tmp/clock_manager_A2_sdl.rb

@@ -1,25 +0,0 @@
-
-# add_to_all_file_paths('clock_manager_A2','/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/acceRed450_clk_ddr3/itgt_clock_manager/clock_manager_A2.sv')
-# real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/acceRed450_clk_ddr3/itgt_clock_manager/clock_manager_A2.sv'
-TdlBuild.clock_manager_A2 do 
-self.real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/acceRed450_clk_ddr3/itgt_clock_manager/clock_manager_A2.sv'
-self.path = File.expand_path(__FILE__)
-parameter.SENSOR_DIV   10
-parameter.MULTI_SAMPLE   10
-parameter.CNT_DIV   "ON"
-input - 'cpu_glbl_rstn' 
-input - 'sysclk_25M' 
-input - 'force_reset_mac' 
-output - 'mac_ref_200M' 
-output - 'mac_clk_125M' 
-output - 'mac_clk_100M' 
-output - 'clk_150M' 
-output - 'mac_rst_n' 
-output - 'ddr_ref_200M' 
-output - 'ddr_rst_n' 
-output - 'sensor_lvds_25_50M_sample_clock' 
-output - 'sensor_lvds_25_50M' 
-output - 'clk_50M' 
-output - 'track_clock' 
-end
-

data/lib/tdl/auto_script/tmp/clock_manager_B2_sdl.rb

@@ -1,26 +0,0 @@
-
-# add_to_all_file_paths('clock_manager_B2','/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/acceRed450_clk_ddr3/itgt_clock_manager/clock_manager_B2.sv')
-# real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/acceRed450_clk_ddr3/itgt_clock_manager/clock_manager_B2.sv'
-TdlBuild.clock_manager_B2 do 
-self.real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/acceRed450_clk_ddr3/itgt_clock_manager/clock_manager_B2.sv'
-self.path = File.expand_path(__FILE__)
-parameter.SENSOR_DIV   10
-parameter.MULTI_SAMPLE   10
-parameter.CNT_DIV   "ON"
-input - 'cpu_glbl_rstn' 
-input - 'force_reset_mac' 
-input - 'sysclk_200M_p' 
-input - 'sysclk_200M_n' 
-output - 'mac_ref_200M' 
-output - 'mac_clk_125M' 
-output - 'mac_clk_100M' 
-output - 'origin_clk_75M' 
-output - 'mac_rst_n' 
-output - 'ddr_ref_200M' 
-output - 'ddr_rst_n' 
-output - 'sensor_lvds_25_50M_sample_clock' 
-output - 'sensor_lvds_25_50M' 
-output - 'clk_50M' 
-output - 'track_clock' 
-end
-

data/lib/tdl/auto_script/tmp/clock_manager_powerlow_sdl.rb

@@ -1,22 +0,0 @@
-
-# add_to_all_file_paths('clock_manager_powerlow','/media/kali/DATA2/work/BK/work/FPGA/mamo_xvm270_20230221/git_repo/hardware/itgt_custom_200T/itgt_clock_manager/clock_manager_powerlow.sv')
-# real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/mamo_xvm270_20230221/git_repo/hardware/itgt_custom_200T/itgt_clock_manager/clock_manager_powerlow.sv'
-TdlBuild.clock_manager_powerlow do 
-self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/mamo_xvm270_20230221/git_repo/hardware/itgt_custom_200T/itgt_clock_manager/clock_manager_powerlow.sv'
-self.path = File.expand_path(__FILE__)
-parameter.SENSOR_DIV   10
-parameter.MULTI_SAMPLE   10
-parameter.CNT_DIV   "ON"
-input - 'cpu_glbl_rstn' 
-input - 'sysclk_25M' 
-output - 'mac_ref_200M' 
-output - 'mac_clk_125M' 
-output - 'mac_clk_100M' 
-output - 'mac_rst_n' 
-input - 'powerdown' 
-output - 'ddr_ref_200M' 
-output - 'ddr_rst_n' 
-output - 'sensor_lvds_25_50M_sample_clock' 
-output - 'sensor_lvds_25_50M' 
-end
-

data/lib/tdl/auto_script/tmp/clock_manager_sdl.rb

@@ -1,16 +0,0 @@
-
-# add_to_all_file_paths('clock_manager','/media/kali/data/FPGA/newQQ/ch50_eth_base/coda_repo/xiaomeige/clock/clock_manager.sv')
-# real_sv_path = '/media/kali/data/FPGA/newQQ/ch50_eth_base/coda_repo/xiaomeige/clock/clock_manager.sv'
-TdlBuild.clock_manager do 
-self.real_sv_path = '/media/kali/data/FPGA/newQQ/ch50_eth_base/coda_repo/xiaomeige/clock/clock_manager.sv'
-self.path = File.expand_path(__FILE__)
-input - 'cpu_glbl_rstn' 
-input - 'systemclk_50M' 
-output - 'clk_33M' 
-output - 'clk_50M' 
-output - 'clk_100M' 
-output - 'clk_200M' 
-output - 'clk_125M' 
-output - 'reset_n' 
-end
-

data/lib/tdl/auto_script/tmp/clock_rst_verb_sdl.rb

@@ -1,14 +0,0 @@
-
-# add_to_all_file_paths('clock_rst_verb','/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/public_atom_module/sim/clock_rst_verb.sv')
-# real_sv_path = '/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/public_atom_module/sim/clock_rst_verb.sv'
-TdlBuild.clock_rst_verb do 
-self.real_sv_path = '/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/public_atom_module/sim/clock_rst_verb.sv'
-self.path = File.expand_path(__FILE__)
-parameter.ACTIVE   1
-parameter.PERIOD_CNT   0
-parameter.RST_HOLD   5
-parameter.FreqM   100
-output - 'clock' 
-output - 'rst_x' 
-end
-

data/lib/tdl/auto_script/tmp/clock_rst_verc_sdl.rb

@@ -1,15 +0,0 @@
-
-# add_to_all_file_paths('clock_rst_verc','/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/public_atom_module/sim/clock_rst_verc.sv')
-# real_sv_path = '/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/public_atom_module/sim/clock_rst_verc.sv'
-TdlBuild.clock_rst_verc do 
-self.real_sv_path = '/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/public_atom_module/sim/clock_rst_verc.sv'
-self.path = File.expand_path(__FILE__)
-parameter.ACTIVE   1
-parameter.PERIOD_CNT   0
-parameter.RST_HOLD   5
-parameter.FreqM   100
-input - 'reboot' 
-output - 'clock' 
-output - 'rst_x' 
-end
-

data/lib/tdl/auto_script/tmp/cmos_redx_1xN_inner_clock_sdl.rb

@@ -1,33 +0,0 @@
-
-# add_to_all_file_paths('cmos_redx_1xN_inner_clock','/media/kali/DATA2/work/BK/work/FPGA/A7_4x4_20241010/git_repo/hardware/sensor_prim_lvds/inner_module/cmos_redx_1xN_inner_clock.sv')
-# real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/A7_4x4_20241010/git_repo/hardware/sensor_prim_lvds/inner_module/cmos_redx_1xN_inner_clock.sv'
-TdlBuild.cmos_redx_1xN_inner_clock do 
-self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/A7_4x4_20241010/git_repo/hardware/sensor_prim_lvds/inner_module/cmos_redx_1xN_inner_clock.sv'
-self.path = File.expand_path(__FILE__)
-parameter.TARGET_FREQM   50
-parameter.SOURCE_FREQM   100
-parameter.MMCM_FREQM   1400
-parameter.HDIV   2
-parameter.LDIV   14
-parameter.NSIZE   14
-parameter.DR_SENSOR_CLK   8
-parameter.CH_NUM   6
-parameter.PARTTEN   "14'b10_0000_0000_0000"
-parameter.PARTTEN_LEN   2
-parameter.PARTTEN_INDEX   13         
-input - 'cpu_glbl_rstn' 
-input - 'root_lvds_clock' 
-input[ param.CH_NUM] - 'cmos_data' 
-output[ param.DR_SENSOR_CLK] - 'cmos_dr_sensor_clock' 
-output - 'lvds_logic_clock' 
-output[ param.CH_NUM] - 'lvds_data' 
-input[ param.CH_NUM] - 'sample_lock' 
-input[ param.CH_NUM][4] - 'force_sample_type' 
-input[ param.CH_NUM] - 'force_sample_type_vld' 
-input - 'enable_sample' 
-output[ param.CH_NUM][4] - 'sample_type' 
-output[ param.CH_NUM] - 'sample_type_vld' 
-output[ param.CH_NUM] - 'sample_type_dire' 
-input['$clog2(CH_NUM)-1:0'] - 'trace_index' 
-end
-

data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0004.coe

@@ -1,18 +0,0 @@
-@0000 0
-@0001 0
-@0002 0
-@0003 0
-@0004 0
-@0005 0
-@0006 0
-@0007 0
-@0008 0
-@0009 0
-@000a a00
-@000b a00
-@000c a00
-@000d a01
-@000e a0a
-@000f a0b
-@0010 a0c
-@0011 b0d

data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0014.coe

@@ -1,18 +0,0 @@
-@0000 0
-@0001 0
-@0002 0
-@0003 0
-@0004 0
-@0005 0
-@0006 0
-@0007 0
-@0008 0
-@0009 0
-@000a a00
-@000b a00
-@000c a00
-@000d a01
-@000e a0a
-@000f a0b
-@0010 a0c
-@0011 b0d

data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0017.coe

@@ -1,18 +0,0 @@
-@0000 0
-@0001 0
-@0002 0
-@0003 0
-@0004 0
-@0005 0
-@0006 0
-@0007 0
-@0008 0
-@0009 0
-@000a a00
-@000b a00
-@000c a00
-@000d a01
-@000e a0a
-@000f a0b
-@0010 a0c
-@0011 b0d

data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0019.coe

@@ -1,18 +0,0 @@
-@0000 0
-@0001 0
-@0002 0
-@0003 0
-@0004 0
-@0005 0
-@0006 0
-@0007 0
-@0008 0
-@0009 0
-@000a a00
-@000b a00
-@000c a00
-@000d a01
-@000e a0a
-@000f a0b
-@0010 a0c
-@0011 b0d

data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0023.coe

@@ -1,18 +0,0 @@
-@0000 0
-@0001 0
-@0002 0
-@0003 0
-@0004 0
-@0005 0
-@0006 0
-@0007 0
-@0008 0
-@0009 0
-@000a a00
-@000b a00
-@000c a00
-@000d a01
-@000e a0a
-@000f a0b
-@0010 a0c
-@0011 b0d

data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0024.coe

@@ -1,18 +0,0 @@
-@0000 0
-@0001 0
-@0002 0
-@0003 0
-@0004 0
-@0005 0
-@0006 0
-@0007 0
-@0008 0
-@0009 0
-@000a a00
-@000b a00
-@000c a00
-@000d a01
-@000e a0a
-@000f a0b
-@0010 a0c
-@0011 b0d

data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0025.coe

@@ -1,18 +0,0 @@
-@0000 0
-@0001 0
-@0002 0
-@0003 0
-@0004 0
-@0005 0
-@0006 0
-@0007 0
-@0008 0
-@0009 0
-@000a a00
-@000b a00
-@000c a00
-@000d a01
-@000e a0a
-@000f a0b
-@0010 a0c
-@0011 b0d

data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0027.coe

@@ -1,18 +0,0 @@
-@0000 0
-@0001 0
-@0002 0
-@0003 0
-@0004 0
-@0005 0
-@0006 0
-@0007 0
-@0008 0
-@0009 0
-@000a a00
-@000b a00
-@000c a00
-@000d a01
-@000e a0a
-@000f a0b
-@0010 a0c
-@0011 b0d

data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0030.coe

@@ -1,18 +0,0 @@
-@0000 0
-@0001 0
-@0002 0
-@0003 0
-@0004 0
-@0005 0
-@0006 0
-@0007 0
-@0008 0
-@0009 0
-@000a a00
-@000b a00
-@000c a00
-@000d a01
-@000e a0a
-@000f a0b
-@0010 a0c
-@0011 b0d

data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0037.coe

@@ -1,18 +0,0 @@
-@0000 0
-@0001 0
-@0002 0
-@0003 0
-@0004 0
-@0005 0
-@0006 0
-@0007 0
-@0008 0
-@0009 0
-@000a a00
-@000b a00
-@000c a00
-@000d a01
-@000e a0a
-@000f a0b
-@0010 a0c
-@0011 b0d