axi_tdl 0.2.7 → 0.2.10

data/lib/tdl/auto_script/tmp/single_chip_iic_bus_verc_wrapper_sdl.rb

@@ -1,15 +0,0 @@
-
-# add_to_all_file_paths('tpu_single_chip_iic_bus_verc_wrapper','/media/kali/DATA2/work/BK/work/FPGA/Red5_20230605/git_repo/tpu_app/single_chip_iic_bus/single_chip_iic_bus_verc_wrapper.sv')
-# real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/Red5_20230605/git_repo/tpu_app/single_chip_iic_bus/single_chip_iic_bus_verc_wrapper.sv'
-TdlBuild.tpu_single_chip_iic_bus_verc_wrapper do 
-self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/Red5_20230605/git_repo/tpu_app/single_chip_iic_bus/single_chip_iic_bus_verc_wrapper.sv'
-self.path = File.expand_path(__FILE__)
-output - 'scl' 
-inout - 'sda' 
-output - 'mcp4728_ldac' 
-input[8] - 'ads1015_iic_addr' 
-port.axi_stream_inf.mirror - 'ctrl_tap_inf' 
-port.axi_stream_inf.master - 'to_ctrl_tap_in_inf' 
-port.axi_stream_inf.master - 'axis_out_inf' 
-end
-

data/lib/tdl/auto_script/tmp/single_chip_iic_bus_verd_wrapper_sdl.rb

@@ -1,15 +0,0 @@
-
-# add_to_all_file_paths('tpu_single_chip_iic_bus_verd_wrapper','/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/tpu_app/single_chip_iic_bus/single_chip_iic_bus_verd_wrapper.sv')
-# real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/tpu_app/single_chip_iic_bus/single_chip_iic_bus_verd_wrapper.sv'
-TdlBuild.tpu_single_chip_iic_bus_verd_wrapper do 
-self.real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/tpu_app/single_chip_iic_bus/single_chip_iic_bus_verd_wrapper.sv'
-self.path = File.expand_path(__FILE__)
-output - 'scl' 
-inout - 'sda' 
-output - 'mcp4728_ldac' 
-input[8] - 'ads1015_iic_addr' 
-port.axi_stream_inf.mirror - 'ctrl_tap_inf' 
-port.axi_stream_inf.master - 'to_ctrl_tap_in_inf' 
-port.axi_stream_inf.master - 'axis_out_inf' 
-end
-

data/lib/tdl/auto_script/tmp/single_chip_iic_bus_wrapper_sdl.rb

@@ -1,14 +0,0 @@
-
-# add_to_all_file_paths('tpu_single_chip_iic_bus_wrapper','/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/tpu_app/single_chip_iic_bus/single_chip_iic_bus_wrapper.sv')
-# real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/tpu_app/single_chip_iic_bus/single_chip_iic_bus_wrapper.sv'
-TdlBuild.tpu_single_chip_iic_bus_wrapper do 
-self.real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/tpu_app/single_chip_iic_bus/single_chip_iic_bus_wrapper.sv'
-self.path = File.expand_path(__FILE__)
-output - 'scl' 
-inout - 'sda' 
-output - 'mcp4728_ldac' 
-port.axi_stream_inf.mirror - 'ctrl_tap_inf' 
-port.axi_stream_inf.master - 'to_ctrl_tap_in_inf' 
-port.axi_stream_inf.master - 'axis_out_inf' 
-end
-

data/lib/tdl/auto_script/tmp/single_chip_lvds_ddr_dir_sdl.rb

@@ -1,18 +0,0 @@
-
-# add_to_all_file_paths('single_chip_lvds_ddr_dir','/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/single_chip_lvds/single_chip_lvds_ddr_dir.sv')
-# real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/single_chip_lvds/single_chip_lvds_ddr_dir.sv'
-TdlBuild.single_chip_lvds_ddr_dir do 
-self.real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/single_chip_lvds/single_chip_lvds_ddr_dir.sv'
-self.path = File.expand_path(__FILE__)
-parameter.CLOCK_TYPE   "OUTER"
-input - 'cpu_glbl_rstn' 
-input[8] - 'sensor2fpga_lvds_data_p' 
-input[8] - 'sensor2fpga_lvds_data_n' 
-input - 'sensor2fpga_lvds_clock_p' 
-input - 'sensor2fpga_lvds_clock_n' 
-input - 'inner_sensor_sp_clock' 
-output - 'sensor_lvds_clock' 
-output - 'sensor_lvds_rstn' 
-output[16] - 'sensor_lvds_data' 
-end
-

data/lib/tdl/auto_script/tmp/single_chip_lvds_dir_delay_sdl.rb

@@ -1,19 +0,0 @@
-
-# add_to_all_file_paths('single_chip_lvds_dir_delay','/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/single_chip_lvds/single_chip_lvds_dir_delay.sv')
-# real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/single_chip_lvds/single_chip_lvds_dir_delay.sv'
-TdlBuild.single_chip_lvds_dir_delay do 
-self.real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/single_chip_lvds/single_chip_lvds_dir_delay.sv'
-self.path = File.expand_path(__FILE__)
-parameter.LAN_NUM   16
-parameter.INNER_SAMPLE   "OFF"
-parameter.DELAY_TAPS   0
-input - 'ref_200M' 
-input - 'sensor_inner_sp_clock' 
-input[ param.LAN_NUM] - 'sensor2fpga_lvds_data_p' 
-input[ param.LAN_NUM] - 'sensor2fpga_lvds_data_n' 
-input - 'sensor2fpga_lvds_clock_p' 
-input - 'sensor2fpga_lvds_clock_n' 
-output - 'sensor_lvds_clock' 
-output[ param.LAN_NUM] - 'sensor_lvds_data' 
-end
-

data/lib/tdl/auto_script/tmp/single_chip_lvds_dir_inner_sdl.rb

@@ -1,17 +0,0 @@
-
-# add_to_all_file_paths('single_chip_lvds_dir_inner','/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/single_chip_lvds/single_chip_lvds_dir_inner.sv')
-# real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/single_chip_lvds/single_chip_lvds_dir_inner.sv'
-TdlBuild.single_chip_lvds_dir_inner do 
-self.real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/single_chip_lvds/single_chip_lvds_dir_inner.sv'
-self.path = File.expand_path(__FILE__)
-parameter.LAN_NUM   16
-parameter.INNER_SAMPLE   "OFF"
-input - 'sensor_inner_sp_clock' 
-input[ param.LAN_NUM] - 'sensor2fpga_lvds_data_p' 
-input[ param.LAN_NUM] - 'sensor2fpga_lvds_data_n' 
-input - 'sensor2fpga_lvds_clock_p' 
-input - 'sensor2fpga_lvds_clock_n' 
-output - 'sensor_lvds_clock' 
-output[ param.LAN_NUM] - 'sensor_lvds_data' 
-end
-

data/lib/tdl/auto_script/tmp/single_chip_sensor_lvds_dir_sdl.rb

@@ -1,15 +0,0 @@
-
-# add_to_all_file_paths('single_chip_sensor_lvds_dir','/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/single_chip_lvds/single_chip_sensor_lvds_dir.sv')
-# real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/single_chip_lvds/single_chip_sensor_lvds_dir.sv'
-TdlBuild.single_chip_sensor_lvds_dir do 
-self.real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/single_chip_lvds/single_chip_sensor_lvds_dir.sv'
-self.path = File.expand_path(__FILE__)
-parameter.LAN_NUM   16
-input[ param.LAN_NUM] - 'sensor2fpga_lvds_data_p' 
-input[ param.LAN_NUM] - 'sensor2fpga_lvds_data_n' 
-input - 'sensor2fpga_lvds_clock_p' 
-input - 'sensor2fpga_lvds_clock_n' 
-output - 'sensor_lvds_clock' 
-output[ param.LAN_NUM] - 'sensor_lvds_data' 
-end
-

data/lib/tdl/auto_script/tmp/sketch_to_origin_stream_sdl.rb

@@ -1,13 +0,0 @@
-
-# add_to_all_file_paths('sketch_to_origin_stream','/media/kali/DATA2/work/BK/work/FPGA/Red8_x4_Eth4_20240923/git_repo/hardware/eth4_chip_lvds/serdes/sketch_to_origin_stream.sv')
-# real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/Red8_x4_Eth4_20240923/git_repo/hardware/eth4_chip_lvds/serdes/sketch_to_origin_stream.sv'
-TdlBuild.sketch_to_origin_stream do 
-self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/Red8_x4_Eth4_20240923/git_repo/hardware/eth4_chip_lvds/serdes/sketch_to_origin_stream.sv'
-self.path = File.expand_path(__FILE__)
-parameter.HEAD_FLAG   "12'b0000_1010_0111"
-parameter.DATA_LENGTH   288*18
-input[5] - 'point_index' 
-port.axi_stream_inf.slaver - 'sketch_inf' 
-port.axi_stream_inf.master - 'origin_inf' 
-end
-

data/lib/tdl/auto_script/tmp/slow_lvds_data_d2s_sdl.rb

@@ -1,13 +0,0 @@
-
-# add_to_all_file_paths('slow_lvds_data_d2s','/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/sensor_prim_lvds/slow_noprim/slow_lvds_data_d2s.sv')
-# real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/sensor_prim_lvds/slow_noprim/slow_lvds_data_d2s.sv'
-TdlBuild.slow_lvds_data_d2s do 
-self.real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/sensor_prim_lvds/slow_noprim/slow_lvds_data_d2s.sv'
-self.path = File.expand_path(__FILE__)
-parameter.DIFF_TERM   "FALSE"
-parameter.NUM   8                
-input[ param.NUM] - 'lvds_data_p' 
-input[ param.NUM] - 'lvds_data_n' 
-output[ param.NUM] - 'lvds_data' 
-end
-

data/lib/tdl/auto_script/tmp/slow_sensor_inner_clock_sdl.rb

@@ -1,18 +0,0 @@
-
-# add_to_all_file_paths('slow_sensor_inner_clock','/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/sensor_prim_lvds/slow_noprim/slow_sensor_inner_clock.sv')
-# real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/sensor_prim_lvds/slow_noprim/slow_sensor_inner_clock.sv'
-TdlBuild.slow_sensor_inner_clock do 
-self.real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/sensor_prim_lvds/slow_noprim/slow_sensor_inner_clock.sv'
-self.path = File.expand_path(__FILE__)
-parameter.TARGET_FREQM   5
-parameter.SOURCE_FREQM   100
-parameter.MMCM_FREQM   800
-input - 'cpu_glbl_rstn' 
-input - 'root_lvds_clock' 
-output - 'lvds_logic_clock' 
-output - 'lvds_logic_clock_sp45' 
-output - 'lvds_logic_clock_sp90' 
-output - 'lvds_logic_clock_sp120' 
-output - 'lvds_loigc_rstn' 
-end
-

data/lib/tdl/auto_script/tmp/split_ddr3_ip_wrapper_sdl.rb

@@ -1,45 +0,0 @@
-
-# add_to_all_file_paths('split_ddr3_ip_wrapper','/media/kali/DATA2/work/BK/work/FPGA/Big8_20230920/git_repo/hardware/boneQ_200T/ddr3/split_ddr3_ip_wrapper.sv')
-# real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/Big8_20230920/git_repo/hardware/boneQ_200T/ddr3/split_ddr3_ip_wrapper.sv'
-TdlBuild.split_ddr3_ip_wrapper do 
-self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/Big8_20230920/git_repo/hardware/boneQ_200T/ddr3/split_ddr3_ip_wrapper.sv'
-self.path = File.expand_path(__FILE__)
-parameter.MARK_X   "OFF"
-input - 'ddr_ref_200M' 
-input - 'ddr_rst' 
-output - 'c0_driver_axi4_clk' 
-output - 'c0_driver_axi4_rst' 
-output - 'c1_driver_axi4_clk' 
-output - 'c1_driver_axi4_rst' 
-inout[16] - 'c0_ddr3_dq' 
-inout[2] - 'c0_ddr3_dqs_n' 
-inout[2] - 'c0_ddr3_dqs_p' 
-output[15] - 'c0_ddr3_addr' 
-output[3] - 'c0_ddr3_ba' 
-output - 'c0_ddr3_ras_n' 
-output - 'c0_ddr3_cas_n' 
-output - 'c0_ddr3_we_n' 
-output - 'c0_ddr3_reset_n' 
-output[1] - 'c0_ddr3_ck_p' 
-output[1] - 'c0_ddr3_ck_n' 
-output[1] - 'c0_ddr3_cke' 
-output[2] - 'c0_ddr3_dm' 
-output[1] - 'c0_ddr3_odt' 
-inout[16] - 'c1_ddr3_dq' 
-inout[2] - 'c1_ddr3_dqs_n' 
-inout[2] - 'c1_ddr3_dqs_p' 
-output[15] - 'c1_ddr3_addr' 
-output[3] - 'c1_ddr3_ba' 
-output - 'c1_ddr3_ras_n' 
-output - 'c1_ddr3_cas_n' 
-output - 'c1_ddr3_we_n' 
-output - 'c1_ddr3_reset_n' 
-output[1] - 'c1_ddr3_ck_p' 
-output[1] - 'c1_ddr3_ck_n' 
-output[1] - 'c1_ddr3_cke' 
-output[2] - 'c1_ddr3_dm' 
-output[1] - 'c1_ddr3_odt' 
-port.axi_inf.slaver - 'c0_caxi_inf' 
-port.axi_inf.slaver - 'c1_caxi_inf' 
-end
-

data/lib/tdl/auto_script/tmp/tcp_aux_tpu_upgrade_sdl.rb

@@ -1,50 +0,0 @@
-
-# add_to_all_file_paths('tcp_aux_tpu_upgrade','/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/tpu_app/tcp_aux/compile_out/tcp_aux_tpu_upgrade.sv')
-# real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/tpu_app/tcp_aux/compile_out/tcp_aux_tpu_upgrade.sv'
-TdlBuild.tcp_aux_tpu_upgrade do 
-self.real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/tpu_app/tcp_aux/compile_out/tcp_aux_tpu_upgrade.sv'
-self.path = File.expand_path(__FILE__)
-parameter.UPGRADE_FLAG   "16'hb7"
-output[16] - 'send_seq_h' 
-output[16] - 'send_seq_l' 
-output[16] - 'send_axi4_addr_h' 
-output[16] - 'send_axi4_addr_l' 
-output[16] - 'send_axi4_len_h' 
-output[16] - 'send_axi4_len_l' 
-output[16] - 'op_a_h' 
-output[16] - 'op_a_l' 
-output[16] - 'op_b_h' 
-output[16] - 'op_b_l' 
-output[4] - 'op_type' 
-output[18] - 'curr_status' 
-output[18] - 'curr_status_main' 
-output[16] - 'mark_ack_seq_h' 
-output[16] - 'mark_ack_seq_l' 
-input[1] - 'rv_tri' 
-input[1] - 'fin_tri' 
-input[1] - 'sync_tri' 
-input[16] - 'win_size_h' 
-input[16] - 'win_size_l' 
-input[16] - 'ack_seq_h' 
-input[16] - 'ack_seq_l' 
-input[1] - 'send_tri' 
-input[16] - 'send_addr_h' 
-input[16] - 'send_addr_l' 
-input[16] - 'send_length_h' 
-input[16] - 'send_length_l' 
-input[16] - 'op_c_h' 
-input[16] - 'op_c_l' 
-input[16] - 'time_ms' 
-input[1] - 'resend_tri' 
-input[16] - 'ack_compare' 
-output[1] - 'clear_rv_tri' 
-output[1] - 'clear_fin_tri' 
-output[1] - 'clear_sync_tri' 
-output[1] - 'clear_send_tri' 
-output[1] - 'send_axi4_req_tri' 
-output[1] - 'clear_resend_tri' 
-port.axi_stream_inf.master - 'axis_out_inf' 
-port.axi_stream_inf.mirror - 'ctrl_tap_inf' 
-port.axi_stream_inf.master - 'to_ctrl_tap_in_inf' 
-end
-

data/lib/tdl/auto_script/tmp/tcp_check_sum_sdl.rb

@@ -1,15 +0,0 @@
-
-# add_to_all_file_paths('tcp_check_sum','/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/wmy/ethernet_protocol/TCP/tcp_check_sum.sv')
-# real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/wmy/ethernet_protocol/TCP/tcp_check_sum.sv'
-TdlBuild.tcp_check_sum do 
-self.real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/wmy/ethernet_protocol/TCP/tcp_check_sum.sv'
-self.path = File.expand_path(__FILE__)
-input - 'clock' 
-input - 'rst_n' 
-input[32] - 'ip_s_addr' 
-input[32] - 'ip_d_addr' 
-input[16] - 'total_length' 
-input[32] - 'tcp_frame_sum' 
-output[16] - 'sum' 
-end
-

data/lib/tdl/auto_script/tmp/tcp_ctrl_set_sdl.rb

@@ -1,13 +0,0 @@
-
-# add_to_all_file_paths('tcp_ctrl_set','/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/software/tcp_feature_extend/udp_ctrl_compatible/tcp_ctrl_set.sv')
-# real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/software/tcp_feature_extend/udp_ctrl_compatible/tcp_ctrl_set.sv'
-TdlBuild.tcp_ctrl_set do 
-self.real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/software/tcp_feature_extend/udp_ctrl_compatible/tcp_ctrl_set.sv'
-self.path = File.expand_path(__FILE__)
-input[16] - 'board_id' 
-port.axi_stream_inf.slaver - 'rx_tcp_ctrl_inf' 
-port.axi_stream_inf.master - 'tx_tcp_ctrl_inf' 
-port.axi_stream_inf.out_mirror - 'out_tap_inf' 
-port.axi_stream_inf.slaver - 'in_tap_inf' 
-end
-

data/lib/tdl/auto_script/tmp/tcp_option_split_B1_sdl.rb

@@ -1,10 +0,0 @@
-
-# add_to_all_file_paths('tcp_option_split_B1','/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/wmy/ethernet_protocol/TCP/tcp_flag_branch/tcp_option_split_B1.sv')
-# real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/wmy/ethernet_protocol/TCP/tcp_flag_branch/tcp_option_split_B1.sv'
-TdlBuild.tcp_option_split_B1 do 
-self.real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/wmy/ethernet_protocol/TCP/tcp_flag_branch/tcp_option_split_B1.sv'
-self.path = File.expand_path(__FILE__)
-port.axi_stream_inf.slaver - 'tcp_option_inf' 
-port.axi_stream_inf.master - 'split_inf' 
-end
-

data/lib/tdl/auto_script/tmp/test_red5dl_lvds_sdl.rb

@@ -1,9 +0,0 @@
-
-# add_to_all_file_paths('test_red5dl_lvds','/media/kali/DATA2/work/BK/work/FPGA/Red5_20230605/git_repo/hardware/four_red5_lvds/test_red5dl_lvds.sv')
-# real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/Red5_20230605/git_repo/hardware/four_red5_lvds/test_red5dl_lvds.sv'
-TdlBuild.test_red5dl_lvds do 
-self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/Red5_20230605/git_repo/hardware/four_red5_lvds/test_red5dl_lvds.sv'
-self.path = File.expand_path(__FILE__)
-port.axi_stream_inf.master - 'tap_udp_inf' 
-end
-

data/lib/tdl/auto_script/tmp/time_delay_ctrl_sdl.rb

@@ -1,13 +0,0 @@
-
-# add_to_all_file_paths('time_delay_ctrl','/media/kali/data/FPGA/newQQ/ch50_eth_base/coda_repo/wmy/time_ctrl/time_delay_ctrl.sv')
-# real_sv_path = '/media/kali/data/FPGA/newQQ/ch50_eth_base/coda_repo/wmy/time_ctrl/time_delay_ctrl.sv'
-TdlBuild.time_delay_ctrl do 
-self.real_sv_path = '/media/kali/data/FPGA/newQQ/ch50_eth_base/coda_repo/wmy/time_ctrl/time_delay_ctrl.sv'
-self.path = File.expand_path(__FILE__)
-parameter.TOTAL   1000
-input - 'clock' 
-input - 'clken' 
-input - 'enable' 
-output - 'delay_done' 
-end
-

data/lib/tdl/auto_script/tmp/time_enable_scaler_sdl.rb

@@ -1,12 +0,0 @@
-
-# add_to_all_file_paths('time_enable_scaler','/media/kali/data/FPGA/newQQ/ch50_eth_base/coda_repo/wmy/time_ctrl/time_enable_scaler.sv')
-# real_sv_path = '/media/kali/data/FPGA/newQQ/ch50_eth_base/coda_repo/wmy/time_ctrl/time_enable_scaler.sv'
-TdlBuild.time_enable_scaler do 
-self.real_sv_path = '/media/kali/data/FPGA/newQQ/ch50_eth_base/coda_repo/wmy/time_ctrl/time_enable_scaler.sv'
-self.path = File.expand_path(__FILE__)
-parameter.SCALE   100      
-input - 'clock' 
-input - 'clken' 
-output - 'out_pulse' 
-end
-

data/lib/tdl/auto_script/tmp/time_step_module_A1_sdl.rb

@@ -1,14 +0,0 @@
-
-# add_to_all_file_paths('time_step_module_A1','/media/kali/data/FPGA/newQQ/ch50_eth_base/coda_repo/wmy/time_ctrl/time_step_module_A1.sv')
-# real_sv_path = '/media/kali/data/FPGA/newQQ/ch50_eth_base/coda_repo/wmy/time_ctrl/time_step_module_A1.sv'
-TdlBuild.time_step_module_A1 do 
-self.real_sv_path = '/media/kali/data/FPGA/newQQ/ch50_eth_base/coda_repo/wmy/time_ctrl/time_step_module_A1.sv'
-self.path = File.expand_path(__FILE__)
-parameter.SYS_CLK_FREQ   100
-parameter.Xms   "1.0"
-parameter.Sim_Xms   "0.00032"
-input - 'clock' 
-input - 'restart' 
-output - 'step_pulse' 
-end
-

data/lib/tdl/auto_script/tmp/time_step_module_sdl.rb

@@ -1,13 +0,0 @@
-
-# add_to_all_file_paths('time_step_module','/media/kali/data/FPGA/newQQ/ch50_eth_base/coda_repo/wmy/time_ctrl/time_step_module.sv')
-# real_sv_path = '/media/kali/data/FPGA/newQQ/ch50_eth_base/coda_repo/wmy/time_ctrl/time_step_module.sv'
-TdlBuild.time_step_module do 
-self.real_sv_path = '/media/kali/data/FPGA/newQQ/ch50_eth_base/coda_repo/wmy/time_ctrl/time_step_module.sv'
-self.path = File.expand_path(__FILE__)
-parameter.SYS_CLK_FREQ   100
-parameter.Xms   "1.0"
-parameter.Sim_Xms   "0.00032"
-input - 'clock' 
-output - 'step_pulse' 
-end
-

data/lib/tdl/auto_script/tmp/tpu_bypass_iic_upgrade_sdl.rb

@@ -1,29 +0,0 @@
-
-# add_to_all_file_paths('tpu_bypass_iic_upgrade','/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/tpu_app/bypass_iic/compile_out/tpu_bypass_iic_upgrade.sv')
-# real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/tpu_app/bypass_iic/compile_out/tpu_bypass_iic_upgrade.sv'
-TdlBuild.tpu_bypass_iic_upgrade do 
-self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/tpu_app/bypass_iic/compile_out/tpu_bypass_iic_upgrade.sv'
-self.path = File.expand_path(__FILE__)
-parameter.UPGRADE_FLAG   "16'hb5"
-output - 'sda_out' 
-input - 'sda_in' 
-output[8] - 'rd_data_b0' 
-output[8] - 'rd_data_b1' 
-input[8] - 'iic_addr' 
-input[1] - 'req_wr_1byte' 
-input[8] - 'wr_data_b0' 
-input[1] - 'req_wr_3bytes' 
-input[8] - 'wr_data_b1' 
-input[8] - 'wr_data_b2' 
-input[1] - 'req_wr_1b_rd_2b' 
-output[1] - 'scl' 
-output[1] - 'tri_ctrl' 
-output[1] - 'clean_wr_1byte' 
-output[1] - 'clean_wr_3bytes' 
-output[1] - 'clean_wr_1b_rd_2b' 
-output[1] - 'ack_req' 
-port.axi_stream_inf.master - 'axis_out_inf' 
-port.axi_stream_inf.mirror - 'ctrl_tap_inf' 
-port.axi_stream_inf.master - 'to_ctrl_tap_in_inf' 
-end
-

data/lib/tdl/auto_script/tmp/tpu_common_iic_upgrade_sdl.rb

@@ -1,25 +0,0 @@
-
-# add_to_all_file_paths('tpu_common_iic_upgrade','/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/tpu_app/common_iic_bus/compile_out/tpu_common_iic_upgrade.sv')
-# real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/tpu_app/common_iic_bus/compile_out/tpu_common_iic_upgrade.sv'
-TdlBuild.tpu_common_iic_upgrade do 
-self.real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/tpu_app/common_iic_bus/compile_out/tpu_common_iic_upgrade.sv'
-self.path = File.expand_path(__FILE__)
-parameter.UPGRADE_FLAG   "16'hb5"
-output - 'sda_out' 
-input - 'sda_in' 
-input[1] - 'iic_req' 
-input[8] - 'recv_len' 
-input[8] - 'send_len' 
-input[8] - 'iic_addr' 
-input[1] - 'fifo_empty' 
-input[8] - 'fifo_data' 
-input[16] - 'tap_type' 
-output[1] - 'scl' 
-output[1] - 'tri_ctrl' 
-output[1] - 'fifo_rd_en' 
-output[1] - 'clear_iic_req' 
-port.axi_stream_inf.master - 'axis_out_inf' 
-port.axi_stream_inf.mirror - 'ctrl_tap_inf' 
-port.axi_stream_inf.master - 'to_ctrl_tap_in_inf' 
-end
-

data/lib/tdl/auto_script/tmp/tpu_custom_iic_bus_C1_wrapper_gray_sdl.rb

@@ -1,19 +0,0 @@
-
-# add_to_all_file_paths('tpu_custom_iic_bus_C1_wrapper_gray','/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/tpu_app/custom_iic_bus_verc/tpu_custom_iic_bus_C1_wrapper_gray.sv')
-# real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/tpu_app/custom_iic_bus_verc/tpu_custom_iic_bus_C1_wrapper_gray.sv'
-TdlBuild.tpu_custom_iic_bus_C1_wrapper_gray do 
-self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/tpu_app/custom_iic_bus_verc/tpu_custom_iic_bus_C1_wrapper_gray.sv'
-self.path = File.expand_path(__FILE__)
-output - 'scl' 
-inout - 'sda' 
-output - 'mcp4728_ldac' 
-input[8] - 'moto_curr_status' 
-input[3] - 'curr_board_cs_code' 
-input - 'curr_sync' 
-port.axi_stream_inf.mirror - 'ctrl_tap_inf' 
-port.axi_stream_inf.master - 'to_ctrl_tap_in_inf' 
-port.axi_stream_inf.master - 'axis_out_inf' 
-port.data_inf_c.master - 'adc_cs_ctrl_inf' 
-port.data_inf_c.mirror - 'mirror_set_reg_status_inf' 
-end
-

data/lib/tdl/auto_script/tmp/tpu_custom_iic_bus_C1_wrapper_sdl.rb

@@ -1,20 +0,0 @@
-
-# add_to_all_file_paths('tpu_custom_iic_bus_C1_wrapper','/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/tpu_app/custom_iic_bus_verc/tpu_custom_iic_bus_C1_wrapper.sv')
-# real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/tpu_app/custom_iic_bus_verc/tpu_custom_iic_bus_C1_wrapper.sv'
-TdlBuild.tpu_custom_iic_bus_C1_wrapper do 
-self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/tpu_app/custom_iic_bus_verc/tpu_custom_iic_bus_C1_wrapper.sv'
-self.path = File.expand_path(__FILE__)
-output - 'scl' 
-inout - 'sda' 
-output - 'mcp4728_ldac' 
-input[8] - 'moto_curr_status' 
-input[3] - 'curr_board_cs_code' 
-input - 'curr_sync' 
-output[6] - 'adc_board_cs' 
-port.axi_stream_inf.mirror - 'ctrl_tap_inf' 
-port.axi_stream_inf.master - 'to_ctrl_tap_in_inf' 
-port.axi_stream_inf.master - 'axis_out_inf' 
-port.data_inf_c.master - 'adc_cs_ctrl_inf' 
-port.data_inf_c.mirror - 'mirror_set_reg_status_inf' 
-end
-

data/lib/tdl/auto_script/tmp/tpu_custom_iic_bus_C1_wrapper_verb_sdl.rb

@@ -1,19 +0,0 @@
-
-# add_to_all_file_paths('tpu_custom_iic_bus_C1_wrapper_verb','/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/tpu_app/custom_iic_bus_verc/tpu_custom_iic_bus_C1_wrapper_verb.sv')
-# real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/tpu_app/custom_iic_bus_verc/tpu_custom_iic_bus_C1_wrapper_verb.sv'
-TdlBuild.tpu_custom_iic_bus_C1_wrapper_verb do 
-self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/tpu_app/custom_iic_bus_verc/tpu_custom_iic_bus_C1_wrapper_verb.sv'
-self.path = File.expand_path(__FILE__)
-output - 'scl' 
-inout - 'sda' 
-output - 'mcp4728_ldac' 
-input[8] - 'moto_curr_status' 
-input[3] - 'curr_board_cs_code' 
-input - 'curr_sync' 
-port.axi_stream_inf.mirror - 'ctrl_tap_inf' 
-port.axi_stream_inf.master - 'to_ctrl_tap_in_inf' 
-port.axi_stream_inf.master - 'axis_out_inf' 
-port.data_inf_c.master - 'adc_cs_ctrl_inf' 
-port.data_inf_c.mirror - 'mirror_set_reg_status_inf' 
-end
-

data/lib/tdl/auto_script/tmp/tpu_custom_iic_bus_C1_wrapper_x7_gray_sdl.rb

@@ -1,19 +0,0 @@
-
-# add_to_all_file_paths('tpu_custom_iic_bus_C1_wrapper_x7_gray','/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/tpu_app/custom_iic_bus_verc/tpu_custom_iic_bus_C1_wrapper_x7_gray.sv')
-# real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/tpu_app/custom_iic_bus_verc/tpu_custom_iic_bus_C1_wrapper_x7_gray.sv'
-TdlBuild.tpu_custom_iic_bus_C1_wrapper_x7_gray do 
-self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/tpu_app/custom_iic_bus_verc/tpu_custom_iic_bus_C1_wrapper_x7_gray.sv'
-self.path = File.expand_path(__FILE__)
-output - 'scl' 
-inout - 'sda' 
-output - 'mcp4728_ldac' 
-input[8] - 'moto_curr_status' 
-input[3] - 'curr_board_cs_code' 
-input - 'curr_sync' 
-port.axi_stream_inf.mirror - 'ctrl_tap_inf' 
-port.axi_stream_inf.master - 'to_ctrl_tap_in_inf' 
-port.axi_stream_inf.master - 'axis_out_inf' 
-port.data_inf_c.master - 'adc_cs_ctrl_inf' 
-port.data_inf_c.mirror - 'mirror_set_reg_status_inf' 
-end
-

data/lib/tdl/auto_script/tmp/tpu_custom_iic_bus_verc_v2_array_sdl.rb

@@ -1,15 +0,0 @@
-
-# add_to_all_file_paths('tpu_custom_iic_bus_verc_v2_array','/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/tpu_app/iic_bus_diffr_v2/tpu_custom_iic_bus_verc_v2_array.sv')
-# real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/tpu_app/iic_bus_diffr_v2/tpu_custom_iic_bus_verc_v2_array.sv'
-TdlBuild.tpu_custom_iic_bus_verc_v2_array do 
-self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/tpu_app/iic_bus_diffr_v2/tpu_custom_iic_bus_verc_v2_array.sv'
-self.path = File.expand_path(__FILE__)
-parameter.NUM   6
-output[ param.NUM] - 'scl' 
-inout[ param.NUM] - 'sda' 
-port.axi_stream_inf.mirror - 'ctrl_tap_inf' 
-port.axi_stream_inf.master - 'to_ctrl_tap_in_inf' 
-port.axi_stream_inf.master - 'axis_out_inf' 
-port.data_inf_c.slaver - 'pca9557_io567_ctrl_inf' 
-end
-

data/lib/tdl/auto_script/tmp/tpu_custom_iic_bus_verc_v3_wrapper_sdl.rb

@@ -1,17 +0,0 @@
-
-# add_to_all_file_paths('tpu_custom_iic_bus_verc_v3_wrapper','/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/tpu_app/iic_bus_diffr_v2/tpu_custom_iic_bus_verc_v3_wrapper.sv')
-# real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/tpu_app/iic_bus_diffr_v2/tpu_custom_iic_bus_verc_v3_wrapper.sv'
-TdlBuild.tpu_custom_iic_bus_verc_v3_wrapper do 
-self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/tpu_app/iic_bus_diffr_v2/tpu_custom_iic_bus_verc_v3_wrapper.sv'
-self.path = File.expand_path(__FILE__)
-parameter.PCA9557_IIC_NUM   0
-output - 'scl' 
-inout - 'sda' 
-port.axi_stream_inf.master - 'ads1015_data_inf' 
-port.axi_stream_inf.mirror - 'ctrl_tap_inf' 
-port.axi_stream_inf.master - 'to_ctrl_tap_in_inf' 
-port.data_inf_c.slaver - 'mcp4728_set_inf' 
-port.data_inf_c.slaver - 'ads1015_req_inf' 
-port.data_inf_c.slaver - 'pca9557_set_inf' 
-end
-

data/lib/tdl/auto_script/tmp/tpu_custom_iic_bus_verc_v4_wrapper_sdl.rb

@@ -1,19 +0,0 @@
-
-# add_to_all_file_paths('tpu_custom_iic_bus_verc_v4_wrapper','/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/tpu_app/iic_bus_diffr_v2/tpu_custom_iic_bus_verc_v4_wrapper.sv')
-# real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/tpu_app/iic_bus_diffr_v2/tpu_custom_iic_bus_verc_v4_wrapper.sv'
-TdlBuild.tpu_custom_iic_bus_verc_v4_wrapper do 
-self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/tpu_app/iic_bus_diffr_v2/tpu_custom_iic_bus_verc_v4_wrapper.sv'
-self.path = File.expand_path(__FILE__)
-parameter.PCA9557_IIC_NUM   0
-output - 'scl' 
-inout - 'sda' 
-port.axi_stream_inf.master - 'ads1015_data_inf' 
-port.axi_stream_inf.mirror - 'ctrl_tap_inf' 
-port.axi_stream_inf.master - 'to_ctrl_tap_in_inf' 
-port.data_inf_c.slaver - 'mcp4728_set_inf' 
-port.data_inf_c.slaver - 'ads1015_req_inf' 
-port.data_inf_c.slaver - 'pca9557_set_inf' 
-port.data_inf_c.slaver - 'dac43204_set_inf' 
-port.data_inf_c.slaver - 'dac43204_req_inf' 
-end
-

data/lib/tdl/auto_script/tmp/tpu_custom_iic_bus_verc_v5_wrapper_sdl.rb

@@ -1,20 +0,0 @@
-
-# add_to_all_file_paths('tpu_custom_iic_bus_verc_v5_wrapper','/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/tpu_app/iic_bus_diffr_v2/tpu_custom_iic_bus_verc_v5_wrapper.sv')
-# real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/tpu_app/iic_bus_diffr_v2/tpu_custom_iic_bus_verc_v5_wrapper.sv'
-TdlBuild.tpu_custom_iic_bus_verc_v5_wrapper do 
-self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/tpu_app/iic_bus_diffr_v2/tpu_custom_iic_bus_verc_v5_wrapper.sv'
-self.path = File.expand_path(__FILE__)
-parameter.PCA9557_IIC_NUM   0
-output - 'scl' 
-inout - 'sda' 
-port.axi_stream_inf.master - 'ads1015_data_inf' 
-port.axi_stream_inf.master - 'dac43204_data_inf' 
-port.axi_stream_inf.mirror - 'ctrl_tap_inf' 
-port.axi_stream_inf.master - 'to_ctrl_tap_in_inf' 
-port.data_inf_c.slaver - 'mcp4728_set_inf' 
-port.data_inf_c.slaver - 'ads1015_req_inf' 
-port.data_inf_c.slaver - 'pca9557_set_inf' 
-port.data_inf_c.slaver - 'dac43204_set_inf' 
-port.data_inf_c.slaver - 'dac43204_req_inf' 
-end
-

data/lib/tdl/auto_script/tmp/tpu_custom_iic_bus_verc_wrapper_sdl.rb

@@ -1,20 +0,0 @@
-
-# add_to_all_file_paths('tpu_custom_iic_bus_verc_wrapper','/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/tpu_app/custom_iic_bus_verc/tpu_custom_iic_bus_verc_wrapper.sv')
-# real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/tpu_app/custom_iic_bus_verc/tpu_custom_iic_bus_verc_wrapper.sv'
-TdlBuild.tpu_custom_iic_bus_verc_wrapper do 
-self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/tpu_app/custom_iic_bus_verc/tpu_custom_iic_bus_verc_wrapper.sv'
-self.path = File.expand_path(__FILE__)
-output - 'scl' 
-inout - 'sda' 
-output - 'mcp4728_ldac' 
-input[8] - 'moto_curr_status' 
-input[3] - 'curr_board_cs_code' 
-input - 'curr_sync' 
-output[6] - 'adc_board_cs' 
-port.axi_stream_inf.mirror - 'ctrl_tap_inf' 
-port.axi_stream_inf.master - 'to_ctrl_tap_in_inf' 
-port.axi_stream_inf.master - 'axis_out_inf' 
-port.data_inf_c.master - 'adc_cs_ctrl_inf' 
-port.data_inf_c.mirror - 'mirror_set_reg_status_inf' 
-end
-