axi_tdl 0.2.7 → 0.2.10

data/lib/axi/xilinx_clock_reset/xilinx_reset_sync.v

@@ -1,91 +0,0 @@
-/**********************************************
-_______________________________________ 
-___________    Cook Darwin   __________    
-_______________________________________
-descript:
-author : Cook.Darwin
-Version: VERA.0.0
-creaded: 
-madified:
-***********************************************/
-`timescale 1ps/1ps
-
-(* dont_touch = "yes" *)
-module xilinx_reset_sync #(
-  parameter INITIALISE = 1'b1,
-  parameter DEPTH = 5
-)
-(
-   input       reset_in,
-   input       clk,
-   input       enable,
-   output      reset_out
-);
-
-
-  wire     reset_sync_reg0;
-  wire     reset_sync_reg1;
-  wire     reset_sync_reg2;
-  wire     reset_sync_reg3;
-  wire     reset_sync_reg4;
-
-  (* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *)
-  FDPE #(
-   .INIT (INITIALISE[0])
-  ) reset_sync0 (
-  .C  (clk),
-  .CE (enable),
-  .PRE(reset_in),
-  .D  (1'b0),
-  .Q  (reset_sync_reg0)
-  );
-
-  (* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *)
-  FDPE #(
-   .INIT (INITIALISE[0])
-  ) reset_sync1 (
-  .C  (clk),
-  .CE (enable),
-  .PRE(reset_in),
-  .D  (reset_sync_reg0),
-  .Q  (reset_sync_reg1)
-  );
-
-  (* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *)
-  FDPE #(
-   .INIT (INITIALISE[0])
-  ) reset_sync2 (
-  .C  (clk),
-  .CE (enable),
-  .PRE(reset_in),
-  .D  (reset_sync_reg1),
-  .Q  (reset_sync_reg2)
-  );
-
-  (* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *)
-  FDPE #(
-   .INIT (INITIALISE[0])
-  ) reset_sync3 (
-  .C  (clk),
-  .CE (enable),
-  .PRE(reset_in),
-  .D  (reset_sync_reg2),
-  .Q  (reset_sync_reg3)
-  );
-
-  (* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *)
-  FDPE #(
-   .INIT (INITIALISE[0])
-  ) reset_sync4 (
-  .C  (clk),
-  .CE (enable),
-  .PRE(reset_in),
-  .D  (reset_sync_reg3),
-  .Q  (reset_sync_reg4)
-  );
-
-
-assign reset_out = reset_sync_reg4;
-
-
-endmodule

data/lib/axi/xilinx_clock_reset/xilinx_reset_sync_A1.sv

@@ -1,112 +0,0 @@
-/**********************************************
-_______________________________________ 
-___________    Cook Darwin   __________    
-_______________________________________
-descript:
-author : Cook.Darwin
-Version: VERA.1.0 2018/3/7 
-    long latency
-creaded: 2016/12/9 
-madified:
-***********************************************/
-`timescale 1ps/1ps
-
-(* dont_touch = "yes" *)
-module xilinx_reset_sync_A1 #(
-  parameter INITIALISE = 1'b1,
-  parameter DEPTH = 5
-)
-(
-   input       reset_in,
-   input       clk,
-   input       enable,
-   output      reset_out
-);
-
-
-logic           long_rst;
-logic[15:0]     long_rst_cnt;
-
-always@(posedge clk,posedge reset_in)
-    if(reset_in)    long_rst_cnt    <= '0;
-    else begin
-        if(long_rst_cnt < 16'd1024)
-                long_rst_cnt <= long_rst_cnt + 1'b1;
-        else    long_rst_cnt <= long_rst_cnt;
-    end
-
-always@(posedge clk,posedge reset_in)
-    if(reset_in)    long_rst <= 1'b1;
-    else begin
-        if(long_rst_cnt >= 16'd1024)
-                long_rst <= 1'b0;
-        else    long_rst <= 1'b1;
-    end
-
-
-  wire     reset_sync_reg0;
-  wire     reset_sync_reg1;
-  wire     reset_sync_reg2;
-  wire     reset_sync_reg3;
-  wire     reset_sync_reg4;
-
-  (* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *)
-  FDPE #(
-   .INIT (INITIALISE[0])
-  ) reset_sync0 (
-  .C  (clk),
-  .CE (enable),
-  .PRE(reset_in || long_rst),
-  .D  (1'b0),
-  .Q  (reset_sync_reg0)
-  );
-
-  (* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *)
-  FDPE #(
-   .INIT (INITIALISE[0])
-  ) reset_sync1 (
-  .C  (clk),
-  .CE (enable),
-  .PRE(reset_in || long_rst),
-  .D  (reset_sync_reg0),
-  .Q  (reset_sync_reg1)
-  );
-
-  (* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *)
-  FDPE #(
-   .INIT (INITIALISE[0])
-  ) reset_sync2 (
-  .C  (clk),
-  .CE (enable),
-  .PRE(reset_in || long_rst),
-  .D  (reset_sync_reg1),
-  .Q  (reset_sync_reg2)
-  );
-
-  (* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *)
-  FDPE #(
-   .INIT (INITIALISE[0])
-  ) reset_sync3 (
-  .C  (clk),
-  .CE (enable),
-  .PRE(reset_in || long_rst),
-  .D  (reset_sync_reg2),
-  .Q  (reset_sync_reg3)
-  );
-
-  (* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *)
-  FDPE #(
-   .INIT (INITIALISE[0])
-  ) reset_sync4 (
-  .C  (clk),
-  .CE (enable),
-  .PRE(reset_in || long_rst),
-  .D  (reset_sync_reg3),
-  .Q  (reset_sync_reg4)
-  );
-
-
-assign reset_out = reset_sync_reg4;
-
-
-endmodule

data/lib/axi/xilinx_clock_reset/xilinx_share_reset.sv

@@ -1,123 +0,0 @@
-
-/**********************************************
-_______________________________________ 
-___________    Cook Darwin   __________    
-_______________________________________
-descript:
-author : Cook.Darwin
-Version: VERA.0.0
-creaded: 
-madified:
-***********************************************/
-`timescale 1ns / 1ps
-module xilinx_share_reset
-(
-    input           glbl_rstn,
-    input           refclk,
-    input           idelayctrl_ready,
-    output          idelayctrl_reset_out,
-    input           to_mmcm_inclk,
-    input           from_mmcm_locked,
-    output          to_mmcm_rst_out           // The reset pulse for the MMCM.
-);
-
-   wire             glbl_rst;
-
-   wire             idelayctrl_reset_in;       // Used to trigger reset_sync generation in refclk domain.
-   wire             idelayctrl_reset_sync;     // Used to create a reset pulse in the IDELAYCTRL refclk domain.
-   reg   [3:0]      idelay_reset_cnt;          // Counter to create a long IDELAYCTRL reset pulse.
-   reg              idelayctrl_reset;
-
-   wire             gtx_mmcm_rst_in;
-   wire             from_mmcm_locked_int;
-   wire             from_mmcm_locked_sync;
-   reg              from_mmcm_locked_reg = 1;
-   reg              from_mmcm_locked_edge = 1;
-
-
- assign glbl_rst              = !glbl_rstn;
-
- //----------------------------------------------------------------------------
- // Reset circuitry associated with the IDELAYCTRL
- //----------------------------------------------------------------------------
-
- assign idelayctrl_reset_out  = idelayctrl_reset;
- assign idelayctrl_reset_in   = glbl_rst || !idelayctrl_ready;
-
-   // Create a synchronous reset in the IDELAYCTRL refclk clock domain.
-   xilinx_reset_sync idelayctrl_reset_gen (
-      .clk              (refclk),
-      .enable           (1'b1),
-      .reset_in         (idelayctrl_reset_in),
-      .reset_out        (idelayctrl_reset_sync)
-   );
-
-   // Reset circuitry for the IDELAYCTRL reset.
-
-   // The IDELAYCTRL must experience a pulse which is at least 50 ns in
-   // duration.  This is ten clock cycles of the 200MHz refclk.  Here we
-   // drive the reset pulse for 12 clock cycles.
-   always @(posedge refclk)
-   begin
-      if (idelayctrl_reset_sync) begin
-         idelay_reset_cnt     <= 4'b0000;
-         idelayctrl_reset     <= 1'b1;
-      end
-      else begin
-         case (idelay_reset_cnt)
-            4'b0000 : idelay_reset_cnt <= 4'b0001;
-            4'b0001 : idelay_reset_cnt <= 4'b0010;
-            4'b0010 : idelay_reset_cnt <= 4'b0011;
-            4'b0011 : idelay_reset_cnt <= 4'b0100;
-            4'b0100 : idelay_reset_cnt <= 4'b0101;
-            4'b0101 : idelay_reset_cnt <= 4'b0110;
-            4'b0110 : idelay_reset_cnt <= 4'b0111;
-            4'b0111 : idelay_reset_cnt <= 4'b1000;
-            4'b1000 : idelay_reset_cnt <= 4'b1001;
-            4'b1001 : idelay_reset_cnt <= 4'b1010;
-            4'b1010 : idelay_reset_cnt <= 4'b1011;
-            4'b1011 : idelay_reset_cnt <= 4'b1100;
-            default : idelay_reset_cnt <= 4'b1100;
-         endcase
-         if (idelay_reset_cnt == 4'b1100) begin
-            idelayctrl_reset  <= 1'b0;
-         end
-         else begin
-            idelayctrl_reset  <= 1'b1;
-         end
-      end
-   end
-
-
-  //----------------------------------------------------------------------------
-  // Reset circuitry associated with the MMCM
-  //----------------------------------------------------------------------------
-
-  assign gtx_mmcm_rst_in = glbl_rst | from_mmcm_locked_edge;
-
-  // Synchronise the async dcm_locked into the to_mmcm_inclk clock domain
-   xilinx_sync_block lock_sync (
-     .clk                   (to_mmcm_inclk),
-     .data_in               (from_mmcm_locked),
-     .data_out              (from_mmcm_locked_sync)
-  );
-
-  // for the falling edge detect we want to force this at power on so init the flop to 1
-  always @(posedge to_mmcm_inclk)
-  begin
-     from_mmcm_locked_reg     <= from_mmcm_locked_sync;
-     from_mmcm_locked_edge    <= from_mmcm_locked_reg & !from_mmcm_locked_sync;
-  end
-
-  // the MMCM reset should be at least 5ns - that is one cycle of the input clock -
-  // since the source of the input reset is unknown (a push switch in board design)
-  // this needs to be debounced
-   xilinx_reset_sync mmcm_reset_gen (
-      .clk                  (to_mmcm_inclk),
-      .enable               (1'b1),
-      .reset_in             (gtx_mmcm_rst_in),
-      .reset_out            (to_mmcm_rst_out)
-   );
-
-
-endmodule

data/lib/axi/xilinx_clock_reset/xilinx_sync_block.v

@@ -1,90 +0,0 @@
-/**********************************************
-_______________________________________ 
-___________    Cook Darwin   __________    
-_______________________________________
-descript:
-author : Cook.Darwin
-Version: VERA.0.0
-creaded: 
-madified:
-***********************************************/
-`timescale 1ps / 1ps
-
-(* dont_touch = "yes" *)
-module xilinx_sync_block #(
-  parameter INITIALISE = 1'b0,
-  parameter DEPTH = 5
-)
-(
-  input        clk,              // clock to be sync'ed to
-  input        data_in,          // Data to be 'synced'
-  output       data_out          // synced data
-);
-
-  // Internal Signals
-  wire   data_sync0;
-  wire   data_sync1;
-  wire   data_sync2;
-  wire   data_sync3;
-  wire   data_sync4;
-
-
-  (* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *)
-  FDRE #(
-    .INIT (INITIALISE[0])
-  ) data_sync_reg0 (
-    .C  (clk),
-    .D  (data_in),
-    .Q  (data_sync0),
-	.CE (1'b1),
-    .R  (1'b0)
-  );
-
-  (* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *)
-  FDRE #(
-   .INIT (INITIALISE[0])
-  ) data_sync_reg1 (
-  .C  (clk),
-  .D  (data_sync0),
-  .Q  (data_sync1),
-  .CE (1'b1),
-  .R  (1'b0)
-  );
-
-  (* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *)
-  FDRE #(
-   .INIT (INITIALISE[0])
-  ) data_sync_reg2 (
-  .C  (clk),
-  .D  (data_sync1),
-  .Q  (data_sync2),
-  .CE (1'b1),
-  .R  (1'b0)
-  );
-
-  (* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *)
-  FDRE #(
-   .INIT (INITIALISE[0])
-  ) data_sync_reg3 (
-  .C  (clk),
-  .D  (data_sync2),
-  .Q  (data_sync3),
-  .CE (1'b1),
-  .R  (1'b0)
-  );
-
-  (* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *)
-  FDRE #(
-   .INIT (INITIALISE[0])
-  ) data_sync_reg4 (
-  .C  (clk),
-  .D  (data_sync3),
-  .Q  (data_sync4),
-  .CE (1'b1),
-  .R  (1'b0)
-  );
-
-  assign data_out = data_sync4;
-
-
-endmodule

data/lib/tdl/auto_script/tmp/MAC_FCS_sdl.rb

@@ -1,13 +0,0 @@
-
-# add_to_all_file_paths('MAC_FCS','/media/kali/data/FPGA/newQQ/ch50_eth_base/coda_repo/wmy/ethernet_protocol/mac/MAC_FCS.sv')
-# real_sv_path = '/media/kali/data/FPGA/newQQ/ch50_eth_base/coda_repo/wmy/ethernet_protocol/mac/MAC_FCS.sv'
-TdlBuild.MAC_FCS do 
-self.real_sv_path = '/media/kali/data/FPGA/newQQ/ch50_eth_base/coda_repo/wmy/ethernet_protocol/mac/MAC_FCS.sv'
-self.path = File.expand_path(__FILE__)
-input - 'rst' 
-input - 'clk' 
-input[8] - 'data_in' 
-input - 'data_en' 
-output[32] - 'fcs_out' 
-end
-

data/lib/tdl/auto_script/tmp/TPU_reprogram_wrapper_verb_sdl.rb

@@ -1,16 +0,0 @@
-
-# add_to_all_file_paths('TPU_reprogram_wrapper_verb','/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/tpu_app/xilinx_reprogram_verb/TPU_reprogram_wrapper_verb.sv')
-# real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/tpu_app/xilinx_reprogram_verb/TPU_reprogram_wrapper_verb.sv'
-TdlBuild.TPU_reprogram_wrapper_verb do 
-self.real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/tpu_app/xilinx_reprogram_verb/TPU_reprogram_wrapper_verb.sv'
-self.path = File.expand_path(__FILE__)
-output - 'spi_csn' 
-output - 'spi_mosi' 
-input - 'spi_miso' 
-output - 'spi_hold' 
-output - 'spi_wp' 
-port.axi_stream_inf.mirror - 'ctrl_tap_inf' 
-port.axi_stream_inf.master - 'to_ctrl_tap_in_inf' 
-port.axi_stream_inf.master - 'axis_out_inf' 
-end
-

data/lib/tdl/auto_script/tmp/adc_1015_tpu_array_B1_sdl.rb

@@ -1,20 +0,0 @@
-
-# add_to_all_file_paths('adc_1015_tpu_array_B1','/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/tpu_app/adc_1015_tpu/adc_1015_tpu_array_B1.sv')
-# real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/tpu_app/adc_1015_tpu/adc_1015_tpu_array_B1.sv'
-TdlBuild.adc_1015_tpu_array_B1 do 
-self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/tpu_app/adc_1015_tpu/adc_1015_tpu_array_B1.sv'
-self.path = File.expand_path(__FILE__)
-parameter.NUM   6
-output[ param.NUM] - 'scl' 
-inout[ param.NUM] - 'sda' 
-input[8] - 'moto_curr_status' 
-input[3] - 'curr_board_cs_code' 
-input - 'curr_sync' 
-output[6] - 'adc_board_cs' 
-port.axi_stream_inf.mirror - 'ctrl_tap_inf' 
-port.axi_stream_inf.master - 'to_ctrl_tap_in_inf' 
-port.axi_stream_inf.master - 'axis_out_inf' 
-port.data_inf_c.master - 'adc_cs_ctrl_inf' 
-port.data_inf_c.mirror - 'mirror_set_reg_status_inf' 
-end
-

data/lib/tdl/auto_script/tmp/adc_1015_tpu_array_gray_sdl.rb

@@ -1,19 +0,0 @@
-
-# add_to_all_file_paths('adc_1015_tpu_array_gray','/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/tpu_app/adc_1015_tpu/adc_1015_tpu_array_gray.sv')
-# real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/tpu_app/adc_1015_tpu/adc_1015_tpu_array_gray.sv'
-TdlBuild.adc_1015_tpu_array_gray do 
-self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/tpu_app/adc_1015_tpu/adc_1015_tpu_array_gray.sv'
-self.path = File.expand_path(__FILE__)
-parameter.NUM   6
-output[ param.NUM] - 'scl' 
-inout[ param.NUM] - 'sda' 
-input[8] - 'moto_curr_status' 
-input[3] - 'curr_board_cs_code' 
-input - 'curr_sync' 
-port.axi_stream_inf.mirror - 'ctrl_tap_inf' 
-port.axi_stream_inf.master - 'to_ctrl_tap_in_inf' 
-port.axi_stream_inf.master - 'axis_out_inf' 
-port.data_inf_c.master - 'adc_cs_ctrl_inf' 
-port.data_inf_c.mirror - 'mirror_set_reg_status_inf' 
-end
-

data/lib/tdl/auto_script/tmp/adc_1015_tpu_array_sdl.rb

@@ -1,19 +0,0 @@
-
-# add_to_all_file_paths('adc_1015_tpu_array','/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/tpu_app/adc_1015_tpu/adc_1015_tpu_array.sv')
-# real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/tpu_app/adc_1015_tpu/adc_1015_tpu_array.sv'
-TdlBuild.adc_1015_tpu_array do 
-self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/tpu_app/adc_1015_tpu/adc_1015_tpu_array.sv'
-self.path = File.expand_path(__FILE__)
-output[5] - 'scl' 
-inout[5] - 'sda' 
-input[8] - 'moto_curr_status' 
-input[3] - 'curr_board_cs_code' 
-input - 'curr_sync' 
-output[6] - 'adc_board_cs' 
-port.axi_stream_inf.mirror - 'ctrl_tap_inf' 
-port.axi_stream_inf.master - 'to_ctrl_tap_in_inf' 
-port.axi_stream_inf.master - 'axis_out_inf' 
-port.data_inf_c.master - 'adc_cs_ctrl_inf' 
-port.data_inf_c.mirror - 'mirror_set_reg_status_inf' 
-end
-

data/lib/tdl/auto_script/tmp/adc_1015_tpu_array_verb_sdl.rb

@@ -1,19 +0,0 @@
-
-# add_to_all_file_paths('adc_1015_tpu_array_verb','/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/tpu_app/adc_1015_tpu/adc_1015_tpu_array_verb.sv')
-# real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/tpu_app/adc_1015_tpu/adc_1015_tpu_array_verb.sv'
-TdlBuild.adc_1015_tpu_array_verb do 
-self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/tpu_app/adc_1015_tpu/adc_1015_tpu_array_verb.sv'
-self.path = File.expand_path(__FILE__)
-output[6] - 'scl' 
-inout[6] - 'sda' 
-input[8] - 'moto_curr_status' 
-input[3] - 'curr_board_cs_code' 
-input - 'curr_sync' 
-output[6] - 'adc_board_cs' 
-port.axi_stream_inf.mirror - 'ctrl_tap_inf' 
-port.axi_stream_inf.master - 'to_ctrl_tap_in_inf' 
-port.axi_stream_inf.master - 'axis_out_inf' 
-port.data_inf_c.master - 'adc_cs_ctrl_inf' 
-port.data_inf_c.mirror - 'mirror_set_reg_status_inf' 
-end
-

data/lib/tdl/auto_script/tmp/adc_1015_tpu_array_verc_diffr_pca9557_sdl.rb

@@ -1,18 +0,0 @@
-
-# add_to_all_file_paths('adc_1015_tpu_array_verc_diffr_pca9557','/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/tpu_app/adc_1015_tpu/adc_1015_tpu_array_verc_diffr_pca9557.sv')
-# real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/tpu_app/adc_1015_tpu/adc_1015_tpu_array_verc_diffr_pca9557.sv'
-TdlBuild.adc_1015_tpu_array_verc_diffr_pca9557 do 
-self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/tpu_app/adc_1015_tpu/adc_1015_tpu_array_verc_diffr_pca9557.sv'
-self.path = File.expand_path(__FILE__)
-parameter.NUM   6
-output[ param.NUM] - 'scl' 
-inout[ param.NUM] - 'sda' 
-input[3] - 'curr_board_cs_code' 
-input - 'curr_sync' 
-port.axi_stream_inf.mirror - 'ctrl_tap_inf' 
-port.axi_stream_inf.master - 'to_ctrl_tap_in_inf' 
-port.axi_stream_inf.master - 'axis_out_inf' 
-port.data_inf_c.master - 'adc_cs_ctrl_inf' 
-port.data_inf_c.mirror - 'mirror_set_reg_status_inf' 
-end
-

data/lib/tdl/auto_script/tmp/adc_1015_tpu_array_verc_diffr_sdl.rb

@@ -1,19 +0,0 @@
-
-# add_to_all_file_paths('adc_1015_tpu_array_verc_diffr','/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/tpu_app/adc_1015_tpu/adc_1015_tpu_array_verc_diffr.sv')
-# real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/tpu_app/adc_1015_tpu/adc_1015_tpu_array_verc_diffr.sv'
-TdlBuild.adc_1015_tpu_array_verc_diffr do 
-self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/tpu_app/adc_1015_tpu/adc_1015_tpu_array_verc_diffr.sv'
-self.path = File.expand_path(__FILE__)
-parameter.NUM   6
-output[ param.NUM] - 'scl' 
-inout[ param.NUM] - 'sda' 
-input[8] - 'moto_curr_status' 
-input[3] - 'curr_board_cs_code' 
-input - 'curr_sync' 
-port.axi_stream_inf.mirror - 'ctrl_tap_inf' 
-port.axi_stream_inf.master - 'to_ctrl_tap_in_inf' 
-port.axi_stream_inf.master - 'axis_out_inf' 
-port.data_inf_c.master - 'adc_cs_ctrl_inf' 
-port.data_inf_c.mirror - 'mirror_set_reg_status_inf' 
-end
-

data/lib/tdl/auto_script/tmp/adc_1015_tpu_array_verc_sdl.rb

@@ -1,19 +0,0 @@
-
-# add_to_all_file_paths('adc_1015_tpu_array_verc','/media/kali/DATA2/work/BK/work/FPGA/mamo_x7_20250512_recall/git_repo/tpu_app/adc_1015_tpu/adc_1015_tpu_array_verc.sv')
-# real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/mamo_x7_20250512_recall/git_repo/tpu_app/adc_1015_tpu/adc_1015_tpu_array_verc.sv'
-TdlBuild.adc_1015_tpu_array_verc do 
-self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/mamo_x7_20250512_recall/git_repo/tpu_app/adc_1015_tpu/adc_1015_tpu_array_verc.sv'
-self.path = File.expand_path(__FILE__)
-parameter.NUM   6
-output[ param.NUM] - 'scl' 
-inout[ param.NUM] - 'sda' 
-input[8] - 'moto_curr_status' 
-input[3] - 'curr_board_cs_code' 
-input - 'curr_sync' 
-port.axi_stream_inf.mirror - 'ctrl_tap_inf' 
-port.axi_stream_inf.master - 'to_ctrl_tap_in_inf' 
-port.axi_stream_inf.master - 'axis_out_inf' 
-port.data_inf_c.master - 'adc_cs_ctrl_inf' 
-port.data_inf_c.mirror - 'mirror_set_reg_status_inf' 
-end
-

data/lib/tdl/auto_script/tmp/adc_1015_tpu_array_x7_gray_sdl.rb

@@ -1,19 +0,0 @@
-
-# add_to_all_file_paths('adc_1015_tpu_array_x7_gray','/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/tpu_app/adc_1015_tpu/adc_1015_tpu_array_x7_gray.sv')
-# real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/tpu_app/adc_1015_tpu/adc_1015_tpu_array_x7_gray.sv'
-TdlBuild.adc_1015_tpu_array_x7_gray do 
-self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/tpu_app/adc_1015_tpu/adc_1015_tpu_array_x7_gray.sv'
-self.path = File.expand_path(__FILE__)
-parameter.NUM   6
-output[ param.NUM] - 'scl' 
-inout[ param.NUM] - 'sda' 
-input[8] - 'moto_curr_status' 
-input[3] - 'curr_board_cs_code' 
-input - 'curr_sync' 
-port.axi_stream_inf.mirror - 'ctrl_tap_inf' 
-port.axi_stream_inf.master - 'to_ctrl_tap_in_inf' 
-port.axi_stream_inf.master - 'axis_out_inf' 
-port.data_inf_c.master - 'adc_cs_ctrl_inf' 
-port.data_inf_c.mirror - 'mirror_set_reg_status_inf' 
-end
-

data/lib/tdl/auto_script/tmp/adc_1015_tpu_wrapper_sdl.rb

@@ -1,20 +0,0 @@
-
-# add_to_all_file_paths('adc_1015_tpu_wrapper','/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/tpu_app/adc_1015_tpu/adc_1015_tpu_wrapper.sv')
-# real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/tpu_app/adc_1015_tpu/adc_1015_tpu_wrapper.sv'
-TdlBuild.adc_1015_tpu_wrapper do 
-self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/tpu_app/adc_1015_tpu/adc_1015_tpu_wrapper.sv'
-self.path = File.expand_path(__FILE__)
-parameter.BOARD_INDEX   "16'd0"
-output - 'scl' 
-inout - 'sda' 
-input[8] - 'moto_curr_status' 
-input[3] - 'curr_board_cs_code' 
-input - 'curr_sync' 
-output[6] - 'adc_board_cs' 
-port.axi_stream_inf.mirror - 'ctrl_tap_inf' 
-port.axi_stream_inf.master - 'to_ctrl_tap_in_inf' 
-port.axi_stream_inf.master - 'axis_out_inf' 
-port.data_inf_c.master - 'adc_cs_ctrl_inf' 
-port.data_inf_c.mirror - 'mirror_set_reg_status_inf' 
-end
-

data/lib/tdl/auto_script/tmp/aec_alarm_check_A1_sdl.rb

@@ -1,14 +0,0 @@
-
-# add_to_all_file_paths('aec_alarm_check_A1','/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/jlw0708/red5_aec/aec_alarm_check_A1.sv')
-# real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/jlw0708/red5_aec/aec_alarm_check_A1.sv'
-TdlBuild.aec_alarm_check_A1 do 
-self.real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/jlw0708/red5_aec/aec_alarm_check_A1.sv'
-self.path = File.expand_path(__FILE__)
-input - 'aec_alarm' 
-output - 'udp_sync' 
-port.axi_stream_inf.mirror - 'ctrl_tap_inf' 
-port.axi_stream_inf.master - 'to_ctrl_tap_in_inf' 
-port.axi_stream_inf.master - 'msg_out_inf' 
-port.data_inf_c.master - 'aec_check_comb_s' 
-end
-

data/lib/tdl/auto_script/tmp/aec_alarm_check_A2_sdl.rb

@@ -1,14 +0,0 @@
-
-# add_to_all_file_paths('aec_alarm_check_A2','/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/jlw0708/red5_aec/aec_alarm_check_A2.sv')
-# real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/jlw0708/red5_aec/aec_alarm_check_A2.sv'
-TdlBuild.aec_alarm_check_A2 do 
-self.real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/jlw0708/red5_aec/aec_alarm_check_A2.sv'
-self.path = File.expand_path(__FILE__)
-input - 'aec_alarm' 
-output - 'sync_open_flag' 
-port.axi_stream_inf.mirror - 'ctrl_tap_inf' 
-port.axi_stream_inf.master - 'to_ctrl_tap_in_inf' 
-port.axi_stream_inf.master - 'msg_out_inf' 
-port.data_inf_c.master - 'aec_check_comb_s' 
-end
-