axi_tdl 0.2.7 → 0.2.10

data/lib/tdl/auto_script/tmp/lvds_ibufds_array_r8_1x6_NOBUFF_sdl.rb

@@ -1,16 +0,0 @@
-
-# add_to_all_file_paths('lvds_ibufds_array_r8_1x6_NOBUFF','/media/kali/DATA2/work/BK/work/FPGA/red8_1x6_20230925/git_repo/hardware/diffr_lvds/lvds_ibufds_array_r8_1x6_NOBUFF.sv')
-# real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/red8_1x6_20230925/git_repo/hardware/diffr_lvds/lvds_ibufds_array_r8_1x6_NOBUFF.sv'
-TdlBuild.lvds_ibufds_array_r8_1x6_NOBUFF do 
-self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/red8_1x6_20230925/git_repo/hardware/diffr_lvds/lvds_ibufds_array_r8_1x6_NOBUFF.sv'
-self.path = File.expand_path(__FILE__)
-parameter.GNUM   4
-parameter.SNUM   6
-input[ param.GNUM] - 'lvds_clock_p' 
-input[ param.GNUM] - 'lvds_clock_n' 
-output[ param.GNUM] - 'lvds_clock_nb' 
-input[ param.GNUM* param.SNUM] - 'lvds_p' 
-input[ param.GNUM* param.SNUM] - 'lvds_n' 
-output[ param.GNUM* param.SNUM] - 'bf_data_i' 
-end
-

data/lib/tdl/auto_script/tmp/lvds_ibufds_array_r8_1x6_OB_sdl.rb

@@ -1,19 +0,0 @@
-
-# add_to_all_file_paths('lvds_ibufds_array_r8_1x6_OB','/media/kali/DATA2/work/BK/work/FPGA/red8_1x6_20230925/git_repo/hardware/diffr_lvds/lvds_ibufds_array_r8_1x6_OB.sv')
-# real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/red8_1x6_20230925/git_repo/hardware/diffr_lvds/lvds_ibufds_array_r8_1x6_OB.sv'
-TdlBuild.lvds_ibufds_array_r8_1x6_OB do 
-self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/red8_1x6_20230925/git_repo/hardware/diffr_lvds/lvds_ibufds_array_r8_1x6_OB.sv'
-self.path = File.expand_path(__FILE__)
-parameter.GNUM   4
-parameter.SNUM   6
-input[ param.GNUM] - 'lvds_clock_p' 
-input[ param.GNUM] - 'lvds_clock_n' 
-output[ param.GNUM] - 'clk_100M_phs0' 
-output[ param.GNUM] - 'clk_100M_phs22' 
-output[ param.GNUM] - 'clk_100M_phs45' 
-input[ param.GNUM* param.SNUM] - 'lvds_p' 
-input[ param.GNUM* param.SNUM] - 'lvds_n' 
-output[ param.GNUM* param.SNUM] - 'bf_data_i' 
-output[ param.GNUM* param.SNUM] - 'bf_data_ib' 
-end
-

data/lib/tdl/auto_script/tmp/lvds_ibufds_array_sdl.rb

@@ -1,15 +0,0 @@
-
-# add_to_all_file_paths('lvds_ibufds_array','/media/kali/DATA2/work/BK/work/FPGA/red8_1x6_20230925/git_repo/hardware/diffr_lvds/lvds_ibufds_array.sv')
-# real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/red8_1x6_20230925/git_repo/hardware/diffr_lvds/lvds_ibufds_array.sv'
-TdlBuild.lvds_ibufds_array do 
-self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/red8_1x6_20230925/git_repo/hardware/diffr_lvds/lvds_ibufds_array.sv'
-self.path = File.expand_path(__FILE__)
-parameter.NUM   12
-input[ param.NUM] - 'lvds_clock_p' 
-input[ param.NUM] - 'lvds_clock_n' 
-output[ param.NUM] - 'lvds_clock_nb' 
-input[ param.NUM] - 'lvds_p' 
-input[ param.NUM] - 'lvds_n' 
-output[ param.NUM] - 'bf_data_i' 
-end
-

data/lib/tdl/auto_script/tmp/lvds_tb_block_A1_sdl.rb

@@ -1,16 +0,0 @@
-
-# add_to_all_file_paths('lvds_tb_block_A1','/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/single_chip_lvds/lvds_tb_block_A1.sv')
-# real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/single_chip_lvds/lvds_tb_block_A1.sv'
-TdlBuild.lvds_tb_block_A1 do 
-self.real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/single_chip_lvds/lvds_tb_block_A1.sv'
-self.path = File.expand_path(__FILE__)
-parameter.HEAD   "20'b0000_0000_10100111"
-parameter.BITS   8
-parameter.LENGTH   256*256
-input - 'clock' 
-input - 'rst_n' 
-input - 'cs' 
-output - 'lvds_data_p' 
-output - 'lvds_data_n' 
-end
-

data/lib/tdl/auto_script/tmp/mac_to_file_sdl.rb

@@ -1,11 +0,0 @@
-
-# add_to_all_file_paths('mac_to_file','/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/itgt_ethernet_1g/mac_to_file.sv')
-# real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/itgt_ethernet_1g/mac_to_file.sv'
-TdlBuild.mac_to_file do 
-self.real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/itgt_ethernet_1g/mac_to_file.sv'
-self.path = File.expand_path(__FILE__)
-parameter.FILE_PATH   """"
-parameter.FIlE_NAME   "pack"
-port.axi_stream_inf.mirror - 'mac_axis_inf' 
-end
-

data/lib/tdl/auto_script/tmp/manchester_router_sdl.rb

@@ -1,13 +0,0 @@
-
-# add_to_all_file_paths('manchester_router','/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/hardware/manchester/manchester_router.sv')
-# real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/hardware/manchester/manchester_router.sv'
-TdlBuild.manchester_router do 
-self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/hardware/manchester/manchester_router.sv'
-self.path = File.expand_path(__FILE__)
-parameter.NUM   32
-output[ param.NUM] - 'mch_dataout' 
-input[ param.NUM] - 'mch_datain' 
-port.axi_stream_inf.slaver - 'to_ct_databoard_inf' 
-port.axi_stream_inf.master - 'from_ct_databoard_inf' 
-end
-

data/lib/tdl/auto_script/tmp/mdio_model_sdl.rb

@@ -1,11 +0,0 @@
-
-# add_to_all_file_paths('mdio_model','/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/wmy/ethernet_protocol/model/mdio_model.sv')
-# real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/wmy/ethernet_protocol/model/mdio_model.sv'
-TdlBuild.mdio_model do 
-self.real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/wmy/ethernet_protocol/model/mdio_model.sv'
-self.path = File.expand_path(__FILE__)
-input - 'reset' 
-inout - 'mdio' 
-input - 'mdc' 
-end
-

data/lib/tdl/auto_script/tmp/mdio_proto_sdl.rb

@@ -1,24 +0,0 @@
-
-# add_to_all_file_paths('mdio_proto','/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/mdio_bus/mdio_proto.sv')
-# real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/mdio_bus/mdio_proto.sv'
-TdlBuild.mdio_proto do 
-self.real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/mdio_bus/mdio_proto.sv'
-self.path = File.expand_path(__FILE__)
-parameter.FreqM   100
-input - 'clock' 
-input - 'rst_n' 
-input[2] - 'st_code' 
-input[2] - 'op_code' 
-input[5] - 'phy_addr' 
-input[5] - 'val_addr' 
-input[16] - 'wr_data' 
-input - 'in_vld' 
-output - 'in_ready' 
-output[16] - 'rd_data' 
-output - 'out_valid' 
-output - 'mdc' 
-output - 'mdio_o' 
-input - 'mdio_i' 
-output - 'mdio_t' 
-end
-

data/lib/tdl/auto_script/tmp/mirror_mac_arp_iic_sdl.rb

@@ -1,10 +0,0 @@
-
-# add_to_all_file_paths('mirror_mac_arp_iic','/media/kali/DATA2/work/BK/work/FPGA/singeRedx_10G_20240708/git_repo/tpu_app/a7_2x4_iic/mirror_mac_arp_iic.sv')
-# real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/singeRedx_10G_20240708/git_repo/tpu_app/a7_2x4_iic/mirror_mac_arp_iic.sv'
-TdlBuild.mirror_mac_arp_iic do 
-self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/singeRedx_10G_20240708/git_repo/tpu_app/a7_2x4_iic/mirror_mac_arp_iic.sv'
-self.path = File.expand_path(__FILE__)
-port.axi_stream_inf.mirror - 'ctrl_tap_inf' 
-port.axi_stream_inf.master - 'to_ctrl_tap_in_inf' 
-end
-

data/lib/tdl/auto_script/tmp/modified_eth_2G5_top_sdl.rb

@@ -1,16 +0,0 @@
-
-# add_to_all_file_paths('modified_eth_2G5_top','/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/hand_2G5/modified_eth_2G5_top.sv')
-# real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/hand_2G5/modified_eth_2G5_top.sv'
-TdlBuild.modified_eth_2G5_top do 
-self.real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/hand_2G5/modified_eth_2G5_top.sv'
-self.path = File.expand_path(__FILE__)
-input - 'gtrefclk_p' 
-input - 'gtrefclk_n' 
-output - 'txp' 
-output - 'txn' 
-input - 'rxp' 
-input - 'rxn' 
-port.axi_stream_inf.master - 'rx_stream_inf' 
-port.axi_stream_inf.slaver - 'tx_stream_inf' 
-end
-

data/lib/tdl/auto_script/tmp/multiple_steps_676_sdl.rb

@@ -1,15 +0,0 @@
-
-# add_to_all_file_paths('multiple_steps_676','/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/hardware/itgt_moto/moto_driver/multiple_steps_676.sv')
-# real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/hardware/itgt_moto/moto_driver/multiple_steps_676.sv'
-TdlBuild.multiple_steps_676 do 
-self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/hardware/itgt_moto/moto_driver/multiple_steps_676.sv'
-self.path = File.expand_path(__FILE__)
-parameter.SYS_CLK_FREQ   "100.0"
-output - 'moto_enable' 
-output - 'moto_direct' 
-output - 'moto_pulse' 
-port.data_inf_c.slaver - 'update_num' 
-port.data_inf_c.slaver - 'req_num' 
-port.data_inf_c.master - 'trigger_done_inf' 
-end
-

data/lib/tdl/auto_script/tmp/multiple_steps_A2_sdl.rb

@@ -1,15 +0,0 @@
-
-# add_to_all_file_paths('multiple_steps_A2','/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/hardware/itgt_moto/moto_driver/multiple_steps_A2.sv')
-# real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/hardware/itgt_moto/moto_driver/multiple_steps_A2.sv'
-TdlBuild.multiple_steps_A2 do 
-self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/hardware/itgt_moto/moto_driver/multiple_steps_A2.sv'
-self.path = File.expand_path(__FILE__)
-parameter.SYS_CLK_FREQ   "100.0"
-output - 'moto_enable' 
-output - 'moto_direct' 
-output - 'moto_pulse' 
-port.data_inf_c.slaver - 'update_num' 
-port.data_inf_c.slaver - 'req_num' 
-port.data_inf_c.master - 'trigger_done_inf' 
-end
-

data/lib/tdl/auto_script/tmp/odata_pool_axi4_A2_sdl.rb

@@ -1,11 +0,0 @@
-
-# add_to_all_file_paths('odata_pool_axi4_A2','/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/AXI4/odata_pool_axi4_A2.sv')
-# real_sv_path = '/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/AXI4/odata_pool_axi4_A2.sv'
-TdlBuild.odata_pool_axi4_A2 do 
-self.real_sv_path = '/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/AXI4/odata_pool_axi4_A2.sv'
-self.path = File.expand_path(__FILE__)
-port.axi_stream_inf.master - 'out_axis' 
-port.axi_inf.master_rd - 'axi_master' 
-port.data_inf_c.slaver - 'addr_size_inf' 
-end
-

data/lib/tdl/auto_script/tmp/odata_pool_axi4_A3_sdl.rb

@@ -1,14 +0,0 @@
-
-# add_to_all_file_paths('odata_pool_axi4_A3','/home/kali/work/FPGA/axi_tdl/lib/axi/AXI4/odata_pool_axi4_A3.sv')
-# real_sv_path = '/home/kali/work/FPGA/axi_tdl/lib/axi/AXI4/odata_pool_axi4_A3.sv'
-TdlBuild.odata_pool_axi4_A3 do 
-self.real_sv_path = '/home/kali/work/FPGA/axi_tdl/lib/axi/AXI4/odata_pool_axi4_A3.sv'
-self.path = File.expand_path(__FILE__)
-parameter.DSIZE   32
-input[ param.DSIZE] - 'in_ex_info' 
-output[ param.DSIZE] - 'out_ex_info' 
-port.axi_stream_inf.master - 'out_axis' 
-port.axi_inf.master_rd - 'axi_master' 
-port.data_inf_c.slaver - 'addr_size_inf' 
-end
-

data/lib/tdl/auto_script/tmp/outSt_combin_spi_core_sdl.rb

@@ -1,22 +0,0 @@
-
-# add_to_all_file_paths('outSt_combin_spi_core','/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/hardware/fast_spi/outSt_combin_spi_core.sv')
-# real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/hardware/fast_spi/outSt_combin_spi_core.sv'
-TdlBuild.outSt_combin_spi_core do 
-self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/hardware/fast_spi/outSt_combin_spi_core.sv'
-self.path = File.expand_path(__FILE__)
-parameter.CH_TOTAL   12
-input - 'dr_spi_clk' 
-input - 'dr_spi_clk_en' 
-input - 'dr_spi_clk_en_lat' 
-input - 'dr_spi_clk_en_x2' 
-input - 'dr_spi_rstn' 
-output[32] - 'curr_spi_stream_len' 
-output - 'spi_send_done' 
-output - 'spi_cs' 
-output - 'spi_sclk' 
-input[ param.CH_TOTAL] - 'spi_miso' 
-output[ param.CH_TOTAL] - 'spi_mosi' 
-port.axi_stream_inf.slaver - 'spi_data_inf' 
-port.axi_stream_inf.master - 'spi_rd_data_inf' 
-end
-

data/lib/tdl/auto_script/tmp/outSt_eth_to_ct_databoard_sdl.rb

@@ -1,13 +0,0 @@
-
-# add_to_all_file_paths('outSt_eth_to_ct_databoard','/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/hardware/manchester/outSt_eth_to_ct_databoard.sv')
-# real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/hardware/manchester/outSt_eth_to_ct_databoard.sv'
-TdlBuild.outSt_eth_to_ct_databoard do 
-self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/hardware/manchester/outSt_eth_to_ct_databoard.sv'
-self.path = File.expand_path(__FILE__)
-parameter.FLAG   "16'h1C1"
-port.axi_stream_inf.mirror - 'ctrl_tap_inf' 
-port.axi_stream_inf.master - 'to_ctrl_tap_in_inf' 
-port.axi_stream_inf.master - 'to_ct_databoard_inf' 
-port.axi_stream_inf.slaver - 'from_ct_databoard_inf' 
-end
-

data/lib/tdl/auto_script/tmp/outSt_eth_to_multi_spi_with_ack_sdl.rb

@@ -1,19 +0,0 @@
-
-# add_to_all_file_paths('outSt_eth_to_multi_spi_with_ack','/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/fpga_dire_flash/outSt_eth_to_multi_spi_with_ack.sv')
-# real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/fpga_dire_flash/outSt_eth_to_multi_spi_with_ack.sv'
-TdlBuild.outSt_eth_to_multi_spi_with_ack do 
-self.real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/fpga_dire_flash/outSt_eth_to_multi_spi_with_ack.sv'
-self.path = File.expand_path(__FILE__)
-parameter.SPI_NUM   8
-parameter.FLAG   "16'h1BF"
-parameter.EDIV   4                
-output - 'spi_cs' 
-output - 'spi_sclk' 
-input[ param.SPI_NUM] - 'spi_miso' 
-output[ param.SPI_NUM] - 'spi_mosi' 
-output - 'busy' 
-port.axi_stream_inf.mirror - 'ctrl_tap_inf' 
-port.axi_stream_inf.master - 'to_ctrl_tap_in_inf' 
-port.data_inf_c.master - 'switch_tri_inf' 
-end
-

data/lib/tdl/auto_script/tmp/outSt_eth_to_spi_sdl.rb

@@ -1,20 +0,0 @@
-
-# add_to_all_file_paths('outSt_eth_to_spi','/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/fast_spi/outSt_eth_to_spi.sv')
-# real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/fast_spi/outSt_eth_to_spi.sv'
-TdlBuild.outSt_eth_to_spi do 
-self.real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/fast_spi/outSt_eth_to_spi.sv'
-self.path = File.expand_path(__FILE__)
-parameter.FLAG   "16'hBF"
-parameter.DSIZE   8
-parameter.ASIZE   8
-parameter.FreQM   "100.0"
-parameter.SCK_FreQM   "50.0"
-output - 'spi_cs' 
-output - 'spi_sclk' 
-input - 'spi_miso' 
-output - 'spi_mosi' 
-output - 'switch_tri' 
-port.axi_stream_inf.mirror - 'ctrl_tap_inf' 
-port.axi_stream_inf.master - 'to_ctrl_tap_in_inf' 
-end
-

data/lib/tdl/auto_script/tmp/outSt_eth_to_spi_verb_sdl.rb

@@ -1,17 +0,0 @@
-
-# add_to_all_file_paths('outSt_eth_to_spi_verb','/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/fast_spi/outSt_eth_to_spi_verb.sv')
-# real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/fast_spi/outSt_eth_to_spi_verb.sv'
-TdlBuild.outSt_eth_to_spi_verb do 
-self.real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/fast_spi/outSt_eth_to_spi_verb.sv'
-self.path = File.expand_path(__FILE__)
-parameter.FLAG   "16'h1BF"
-parameter.EDIV   4                
-output - 'spi_cs' 
-output - 'spi_sclk' 
-input - 'spi_miso' 
-output - 'spi_mosi' 
-port.axi_stream_inf.mirror - 'ctrl_tap_inf' 
-port.axi_stream_inf.master - 'to_ctrl_tap_in_inf' 
-port.data_inf_c.master - 'switch_tri_inf' 
-end
-

data/lib/tdl/auto_script/tmp/outSt_eth_to_spi_with_ack_sdl.rb

@@ -1,17 +0,0 @@
-
-# add_to_all_file_paths('outSt_eth_to_spi_with_ack','/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/fast_spi/outSt_eth_to_spi_with_ack.sv')
-# real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/fast_spi/outSt_eth_to_spi_with_ack.sv'
-TdlBuild.outSt_eth_to_spi_with_ack do 
-self.real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/fast_spi/outSt_eth_to_spi_with_ack.sv'
-self.path = File.expand_path(__FILE__)
-parameter.FLAG   "16'h1BF"
-parameter.EDIV   4                
-output - 'spi_cs' 
-output - 'spi_sclk' 
-input - 'spi_miso' 
-output - 'spi_mosi' 
-port.axi_stream_inf.mirror - 'ctrl_tap_inf' 
-port.axi_stream_inf.master - 'to_ctrl_tap_in_inf' 
-port.data_inf_c.master - 'switch_tri_inf' 
-end
-

data/lib/tdl/auto_script/tmp/outSt_spi_core_B1_sdl.rb

@@ -1,21 +0,0 @@
-
-# add_to_all_file_paths('outSt_spi_core_B1','/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/hardware/fast_spi/outSt_spi_core_B1.sv')
-# real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/hardware/fast_spi/outSt_spi_core_B1.sv'
-TdlBuild.outSt_spi_core_B1 do 
-self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/hardware/fast_spi/outSt_spi_core_B1.sv'
-self.path = File.expand_path(__FILE__)
-input - 'dr_spi_clk' 
-input - 'dr_spi_clk_en' 
-input - 'dr_spi_clk_en_lat' 
-input - 'dr_spi_clk_en_x2' 
-input - 'dr_spi_rstn' 
-output[32] - 'curr_spi_stream_len' 
-output - 'spi_send_done' 
-output - 'spi_cs' 
-output - 'spi_sclk' 
-input - 'spi_miso' 
-output - 'spi_mosi' 
-port.axi_stream_inf.slaver - 'spi_data_inf' 
-port.axi_stream_inf.master - 'spi_rd_data_inf' 
-end
-

data/lib/tdl/auto_script/tmp/pack_ip_mac_B1_sdl.rb

@@ -1,15 +0,0 @@
-
-# add_to_all_file_paths('pack_ip_mac_B1','/media/kali/data/FPGA/newQQ/ch50_eth_base/coda_repo/wmy/ethernet_protocol/ethernet_proto/pack_ip_mac_B1.sv')
-# real_sv_path = '/media/kali/data/FPGA/newQQ/ch50_eth_base/coda_repo/wmy/ethernet_protocol/ethernet_proto/pack_ip_mac_B1.sv'
-TdlBuild.pack_ip_mac_B1 do 
-self.real_sv_path = '/media/kali/data/FPGA/newQQ/ch50_eth_base/coda_repo/wmy/ethernet_protocol/ethernet_proto/pack_ip_mac_B1.sv'
-self.path = File.expand_path(__FILE__)
-input[32] - 'ip_s_addr' 
-input[32] - 'ip_d_addr' 
-input[48] - 'mac_s_addr' 
-input[48] - 'mac_d_addr' 
-port.axi_stream_inf.slaver - 'tcp_axis_in' 
-port.axi_stream_inf.slaver - 'udp_axis_in' 
-port.axi_stream_inf.master - 'tx_inf' 
-end
-

data/lib/tdl/auto_script/tmp/pack_ip_mac_verb_sdl.rb

@@ -1,15 +0,0 @@
-
-# add_to_all_file_paths('pack_ip_mac_verb','/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/wmy/ethernet_protocol/ethernet_proto/pack_ip_mac_verb.sv')
-# real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/wmy/ethernet_protocol/ethernet_proto/pack_ip_mac_verb.sv'
-TdlBuild.pack_ip_mac_verb do 
-self.real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/wmy/ethernet_protocol/ethernet_proto/pack_ip_mac_verb.sv'
-self.path = File.expand_path(__FILE__)
-input[32] - 'ip_s_addr' 
-input[32] - 'ip_d_addr' 
-input[48] - 'mac_s_addr' 
-input[48] - 'mac_d_addr' 
-port.axi_stream_inf.slaver - 'tcp_axis_in' 
-port.axi_stream_inf.slaver - 'udp_axis_in' 
-port.axi_stream_inf.master - 'tx_inf' 
-end
-

data/lib/tdl/auto_script/tmp/parse_big_field_table_A2_sdl.rb

@@ -1,19 +0,0 @@
-
-# add_to_all_file_paths('parse_big_field_table_A2','/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/AXI_stream/parse_big_field_table_A2.sv')
-# real_sv_path = '/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/AXI_stream/parse_big_field_table_A2.sv'
-TdlBuild.parse_big_field_table_A2 do 
-self.real_sv_path = '/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/AXI_stream/parse_big_field_table_A2.sv'
-self.path = File.expand_path(__FILE__)
-parameter.DSIZE   8
-parameter.FIELD_LEN   16*8
-parameter.FIELD_NAME   "Big Filed"
-parameter.TRY_PARSE   "OFF"
-parameter.TMP_START   0
-input - 'enable' 
-output[( param.TMP_START+1- param.DSIZE* param.FIELD_LEN-1)] - 'value' 
-output - 'out_valid' 
-port.axi_stream_inf.slaver - 'cm_tb_s' 
-port.axi_stream_inf.master - 'cm_tb_m' 
-port.axi_stream_inf.mirror - 'cm_mirror' 
-end
-

data/lib/tdl/auto_script/tmp/parse_big_field_table_main_sdl.rb

@@ -1,15 +0,0 @@
-
-# add_to_all_file_paths('parse_big_field_table_main','/var/lib/gems/2.7.0/gems/axi_tdl-0.2.4/lib/axi/AXI_stream/parse_big_field_table_main.sv')
-# real_sv_path = '/var/lib/gems/2.7.0/gems/axi_tdl-0.2.4/lib/axi/AXI_stream/parse_big_field_table_main.sv'
-TdlBuild.parse_big_field_table_main do 
-self.real_sv_path = '/var/lib/gems/2.7.0/gems/axi_tdl-0.2.4/lib/axi/AXI_stream/parse_big_field_table_main.sv'
-self.path = File.expand_path(__FILE__)
-parameter.DSIZE   8
-parameter.FIELD_LEN   16*8
-parameter.START_INDEX   0
-output[( param.START_INDEX+1- param.DSIZE* param.FIELD_LEN-1)] - 'value' 
-output - 'out_valid' 
-port.axi_stream_inf.slaver - 'cm_tb_s' 
-port.axi_stream_inf.master - 'cm_tb_m' 
-end
-

data/lib/tdl/auto_script/tmp/parse_big_field_table_mirror_sdl.rb

@@ -1,14 +0,0 @@
-
-# add_to_all_file_paths('parse_big_field_table_mirror','/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/AXI_stream/parse_big_field_table_mirror.sv')
-# real_sv_path = '/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/AXI_stream/parse_big_field_table_mirror.sv'
-TdlBuild.parse_big_field_table_mirror do 
-self.real_sv_path = '/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/AXI_stream/parse_big_field_table_mirror.sv'
-self.path = File.expand_path(__FILE__)
-parameter.DSIZE   8
-parameter.FIELD_LEN   16*8
-parameter.START_INDEX   0
-output[( param.START_INDEX+1- param.DSIZE* param.FIELD_LEN-1)] - 'value' 
-output - 'out_valid' 
-port.axi_stream_inf.mirror - 'cm_mirror' 
-end
-

data/lib/tdl/auto_script/tmp/parse_big_field_table_sdl.rb

@@ -1,18 +0,0 @@
-
-# add_to_all_file_paths('parse_big_field_table','/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/AXI_stream/parse_big_field_table.sv')
-# real_sv_path = '/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/AXI_stream/parse_big_field_table.sv'
-TdlBuild.parse_big_field_table do 
-self.real_sv_path = '/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/AXI_stream/parse_big_field_table.sv'
-self.path = File.expand_path(__FILE__)
-parameter.DSIZE   8
-parameter.FIELD_LEN   16*8
-parameter.FIELD_NAME   "Big Filed"
-parameter.TRY_PARSE   "OFF"
-input - 'enable' 
-output[ param.DSIZE* param.FIELD_LEN] - 'value' 
-output - 'out_valid' 
-port.axi_stream_inf.slaver - 'cm_tb_s' 
-port.axi_stream_inf.master - 'cm_tb_m' 
-port.axi_stream_inf.mirror - 'cm_mirror' 
-end
-

data/lib/tdl/auto_script/tmp/parse_big_field_table_slaver_sdl.rb

@@ -1,17 +0,0 @@
-
-# add_to_all_file_paths('parse_big_field_table_slaver','/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/AXI_stream/parse_big_field_table_slaver.sv')
-# real_sv_path = '/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/AXI_stream/parse_big_field_table_slaver.sv'
-TdlBuild.parse_big_field_table_slaver do 
-self.real_sv_path = '/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/AXI_stream/parse_big_field_table_slaver.sv'
-self.path = File.expand_path(__FILE__)
-parameter.DSIZE   8
-parameter.FIELD_LEN   16*8
-parameter.FIELD_NAME   "Big Filed"
-parameter.TMP_START   0
-input - 'enable' 
-output[( param.TMP_START+1- param.DSIZE* param.FIELD_LEN-1)] - 'value' 
-output - 'out_valid' 
-port.axi_stream_inf.slaver - 'cm_tb_s' 
-port.axi_stream_inf.master - 'cm_tb_m' 
-end
-

data/lib/tdl/auto_script/tmp/parse_big_field_table_verb_sdl.rb

@@ -1,17 +0,0 @@
-
-# add_to_all_file_paths('parse_big_field_table_verb','/var/lib/gems/2.7.0/gems/axi_tdl-0.2.4/lib/axi/AXI_stream/parse_big_field_table_verb.sv')
-# real_sv_path = '/var/lib/gems/2.7.0/gems/axi_tdl-0.2.4/lib/axi/AXI_stream/parse_big_field_table_verb.sv'
-TdlBuild.parse_big_field_table_verb do 
-self.real_sv_path = '/var/lib/gems/2.7.0/gems/axi_tdl-0.2.4/lib/axi/AXI_stream/parse_big_field_table_verb.sv'
-self.path = File.expand_path(__FILE__)
-parameter.DSIZE   8
-parameter.FIELD_LEN   16*8
-parameter.TRY_PARSE   "OFF"
-parameter.START_INDEX   0
-output[( param.START_INDEX+1- param.DSIZE* param.FIELD_LEN-1)] - 'value' 
-output - 'out_valid' 
-port.axi_stream_inf.slaver - 'cm_tb_s' 
-port.axi_stream_inf.master - 'cm_tb_m' 
-port.axi_stream_inf.mirror - 'cm_mirror' 
-end
-

data/lib/tdl/auto_script/tmp/parse_common_frame_table_A1_sdl.rb

@@ -1,64 +0,0 @@
-
-# add_to_all_file_paths('parse_common_frame_table_A1','/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/AXI_stream/parse_common_frame_table_A1.sv')
-# real_sv_path = '/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/AXI_stream/parse_common_frame_table_A1.sv'
-TdlBuild.parse_common_frame_table_A1 do 
-self.real_sv_path = '/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/AXI_stream/parse_common_frame_table_A1.sv'
-self.path = File.expand_path(__FILE__)
-parameter.FIELD_TOTLE   11
-parameter.DSIZE   8
-parameter.TRY_PARSE   "OFF"
-parameter.F0_LEN   1
-parameter.F0_NAME   "version+head length"
-parameter.F1_LEN   1
-parameter.F1_NAME   "TOS"
-parameter.F2_LEN   2
-parameter.F2_NAME   "totle length"
-parameter.F3_LEN   2
-parameter.F3_NAME   "identify"
-parameter.F4_LEN   1
-parameter.F4_NAME   "flag + offset MSB"
-parameter.F5_LEN   1
-parameter.F5_NAME   "offset LSB"
-parameter.F6_LEN   1
-parameter.F6_NAME   "TTL"
-parameter.F7_LEN   1
-parameter.F7_NAME   "sub protocol"
-parameter.F8_LEN   2
-parameter.F8_NAME   "head CRC"
-parameter.F9_LEN   4
-parameter.F9_NAME   "source ip addr"
-parameter.F10_LEN   4
-parameter.F10_NAME   "destination ip addr"
-parameter.F11_LEN   1
-parameter.F11_NAME   "Filed 11"
-parameter.F12_LEN   1
-parameter.F12_NAME   "Filed 12"
-parameter.F13_LEN   1
-parameter.F13_NAME   "Field 13"
-parameter.F14_LEN   1
-parameter.F14_NAME   "Field 14"
-parameter.F15_LEN   1
-parameter.F15_NAME   "Field 15"
-input - 'enable' 
-output[( param.F0_LEN * param.DSIZE-1+1-0)] - 'f0_value' 
-output[( param.F1_LEN * param.DSIZE-1+1-0)] - 'f1_value' 
-output[( param.F2_LEN * param.DSIZE-1+1-0)] - 'f2_value' 
-output[( param.F3_LEN * param.DSIZE-1+1-0)] - 'f3_value' 
-output[( param.F4_LEN * param.DSIZE-1+1-0)] - 'f4_value' 
-output[( param.F5_LEN * param.DSIZE-1+1-0)] - 'f5_value' 
-output[( param.F6_LEN * param.DSIZE-1+1-0)] - 'f6_value' 
-output[( param.F7_LEN * param.DSIZE-1+1-0)] - 'f7_value' 
-output[( param.F8_LEN * param.DSIZE-1+1-0)] - 'f8_value' 
-output[( param.F9_LEN * param.DSIZE-1+1-0)] - 'f9_value' 
-output[ param.F10_LEN* param.DSIZE] - 'f10_value' 
-output[ param.F11_LEN* param.DSIZE] - 'f11_value' 
-output[ param.F12_LEN* param.DSIZE] - 'f12_value' 
-output[ param.F13_LEN* param.DSIZE] - 'f13_value' 
-output[ param.F14_LEN* param.DSIZE] - 'f14_value' 
-output[ param.F15_LEN* param.DSIZE] - 'f15_value' 
-output - 'out_valid' 
-port.axi_stream_inf.slaver - 'cm_tb_s' 
-port.axi_stream_inf.master - 'cm_tb_m' 
-port.axi_stream_inf.mirror - 'cm_mirror' 
-end
-

data/lib/tdl/auto_script/tmp/parse_tap_stream_sdl.rb

@@ -1,10 +0,0 @@
-
-# add_to_all_file_paths('parse_tap_stream','/media/kali/DATA2/work/BK/work/FPGA/CT_20250327/git_repo/wmy/ethernet_protocol/udp/tap_stream/parse_tap_stream.sv')
-# real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/CT_20250327/git_repo/wmy/ethernet_protocol/udp/tap_stream/parse_tap_stream.sv'
-TdlBuild.parse_tap_stream do 
-self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/CT_20250327/git_repo/wmy/ethernet_protocol/udp/tap_stream/parse_tap_stream.sv'
-self.path = File.expand_path(__FILE__)
-port.axi_stream_inf.slaver - 'taps_inf' 
-port.axi_stream_inf.master - 'split_inf' 
-end
-

data/lib/tdl/auto_script/tmp/phase_red8_sensor_lvds_block_red8_sdl.rb

@@ -1,22 +0,0 @@
-
-# add_to_all_file_paths('phase_red8_sensor_lvds_block_red8','/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/hardware/phase_lvds/phase_red8_sensor_lvds_block_red8.sv')
-# real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/hardware/phase_lvds/phase_red8_sensor_lvds_block_red8.sv'
-TdlBuild.phase_red8_sensor_lvds_block_red8 do 
-self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/hardware/phase_lvds/phase_red8_sensor_lvds_block_red8.sv'
-self.path = File.expand_path(__FILE__)
-parameter.NUM   24
-parameter.DATA_LENGTH   291*288
-parameter.BASEADDR   "16/128"
-input - 'clock' 
-input - 'rst_n' 
-input[ param.NUM] - 'origin_lvds_clk' 
-input[8] - 'sensor_xlocal' 
-input - 'sensre_data_reset' 
-input[3] - 'cs_vector' 
-input[ param.NUM] - 'senser_lvds_clock_p' 
-input[ param.NUM] - 'senser_lvds_clock_n' 
-input[ param.NUM] - 'senser_lvds_p' 
-input[ param.NUM] - 'senser_lvds_n' 
-port.axi_inf.master_wr[ param.NUM] - 'caxi4_inf' 
-end
-