axi_tdl 0.2.7 → 0.2.10

data/lib/tdl/auto_script/tmp/tpu_eth4_iic_bus_wrapper_sdl.rb

@@ -1,15 +0,0 @@
-
-# add_to_all_file_paths('tpu_eth4_iic_bus_wrapper','/media/kali/DATA2/work/BK/work/FPGA/Red8_x4_Eth4_20240923/git_repo/tpu_app/eth4_iic_bus/tpu_eth4_iic_bus_wrapper.sv')
-# real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/Red8_x4_Eth4_20240923/git_repo/tpu_app/eth4_iic_bus/tpu_eth4_iic_bus_wrapper.sv'
-TdlBuild.tpu_eth4_iic_bus_wrapper do 
-self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/Red8_x4_Eth4_20240923/git_repo/tpu_app/eth4_iic_bus/tpu_eth4_iic_bus_wrapper.sv'
-self.path = File.expand_path(__FILE__)
-output - 'scl' 
-inout - 'sda' 
-output - 'mcp4728_ldac' 
-input[16] - 'pc_port' 
-port.axi_stream_inf.mirror - 'ctrl_tap_inf' 
-port.axi_stream_inf.master - 'to_ctrl_tap_in_inf' 
-port.axi_stream_inf.master - 'axis_out_inf' 
-end
-

data/lib/tdl/auto_script/tmp/tpu_mgm_inf_sdl.rb

@@ -1,28 +0,0 @@
-
-# add_to_all_file_paths('tpu_mgm_inf','/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/jlw0708/eth_with_xilinx_rgmii/tpu/compile_out/tpu_mgm_inf.sv')
-# real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/jlw0708/eth_with_xilinx_rgmii/tpu/compile_out/tpu_mgm_inf.sv'
-TdlBuild.tpu_mgm_inf do 
-self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/phase_red8_20240226/git_repo/jlw0708/eth_with_xilinx_rgmii/tpu/compile_out/tpu_mgm_inf.sv'
-self.path = File.expand_path(__FILE__)
-parameter.INIT_FILE   "/home/myw357/work/FPGA/MAMO/xmamo_20211115/git_repo/jlw0708/eth_with_xilinx_rgmii/tpu/compile_out/tpu_mgm_inf.coe"
-parameter.RAM_SIZE   12
-parameter.DSIZE   18
-output - 'mdio_out' 
-input - 'mdio_in' 
-output[1] - 'mdc' 
-output[1] - 'mdio_z' 
-output[16] - 'md_status' 
-output[16] - 'axil_rd_data' 
-input[1] - 'axil_wr_tri' 
-input[16] - 'axil_wr_addr' 
-input[16] - 'axil_wr_data' 
-input[1] - 'axil_rd_tri' 
-input[16] - 'axil_rd_addr' 
-output[1] - 'clear_axil_wr_tri' 
-output[1] - 'axil_rd_data_done' 
-input - 'update_live_enable' 
-output - 'update_live_open' 
-output - 'busy' 
-port.axi_stream_inf.slaver - 'update_ram_inf' 
-end
-

data/lib/tdl/auto_script/tmp/tpu_simple_boot_sdl.rb

@@ -1,12 +0,0 @@
-
-# add_to_all_file_paths('tpu_simple_boot','/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/wmy/tpu/RTL/tpu_simple_boot.sv')
-# real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/wmy/tpu/RTL/tpu_simple_boot.sv'
-TdlBuild.tpu_simple_boot do 
-self.real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/wmy/tpu/RTL/tpu_simple_boot.sv'
-self.path = File.expand_path(__FILE__)
-parameter.TPU_RAM_SIZE   11
-parameter.TPU_DSIZE   18
-input - 'ex_trigger' 
-port.axi_stream_inf.master - 'boot_inf' 
-end
-

data/lib/tdl/auto_script/tmp/trigger_data_inf_c_A1_sdl.rb

@@ -1,12 +0,0 @@
-
-# add_to_all_file_paths('trigger_data_inf_c_A1','/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/data_interface/data_inf_c/trigger_data_inf_c_A1.sv')
-# real_sv_path = '/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/data_interface/data_inf_c/trigger_data_inf_c_A1.sv'
-TdlBuild.trigger_data_inf_c_A1 do 
-self.real_sv_path = '/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/data_interface/data_inf_c/trigger_data_inf_c_A1.sv'
-self.path = File.expand_path(__FILE__)
-parameter.DSIZE   32
-input - 'trigger' 
-input[ param.DSIZE] - 'data' 
-port.data_inf_c.master - 'trigger_inf' 
-end
-

data/lib/tdl/auto_script/tmp/trigger_data_inf_c_sdl.rb

@@ -1,12 +0,0 @@
-
-# add_to_all_file_paths('trigger_data_inf_c','/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/data_interface/data_inf_c/trigger_data_inf_c.sv')
-# real_sv_path = '/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/data_interface/data_inf_c/trigger_data_inf_c.sv'
-TdlBuild.trigger_data_inf_c do 
-self.real_sv_path = '/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/data_interface/data_inf_c/trigger_data_inf_c.sv'
-self.path = File.expand_path(__FILE__)
-parameter.DSIZE   32
-input - 'trigger' 
-input[ param.DSIZE] - 'data' 
-port.data_inf_c.master - 'trigger_inf' 
-end
-

data/lib/tdl/auto_script/tmp/uart_hp_ddr3_tft800x480_hdmi_ext_sdl.rb

@@ -1,43 +0,0 @@
-
-# add_to_all_file_paths('uart_hp_ddr3_tft800x480_hdmi_ext','/media/kali/data/FPGA/newQQ/ch50_eth_base/coda_repo/xiaomeige/ch39/uart_hp_ddr3_tft800x480_hdmi_ext.sv')
-# real_sv_path = '/media/kali/data/FPGA/newQQ/ch50_eth_base/coda_repo/xiaomeige/ch39/uart_hp_ddr3_tft800x480_hdmi_ext.sv'
-TdlBuild.uart_hp_ddr3_tft800x480_hdmi_ext do 
-self.real_sv_path = '/media/kali/data/FPGA/newQQ/ch50_eth_base/coda_repo/xiaomeige/ch39/uart_hp_ddr3_tft800x480_hdmi_ext.sv'
-self.path = File.expand_path(__FILE__)
-input - 'reset_n' 
-output - 'led' 
-output[16] - 'TFT_rgb' 
-output - 'TFT_hs' 
-output - 'TFT_vs' 
-output - 'TFT_clk' 
-output - 'TFT_de' 
-output - 'TFT_pwm' 
-input - 'uart_rx' 
-output - 'SiI9022_sclk' 
-inout - 'SiI9022_sdat' 
-inout[32] - 'ddr3_dq' 
-inout[4] - 'ddr3_dqs_n' 
-inout[4] - 'ddr3_dqs_p' 
-output[15] - 'ddr3_addr' 
-output[3] - 'ddr3_ba' 
-output - 'ddr3_ras_n' 
-output - 'ddr3_cas_n' 
-output - 'ddr3_we_n' 
-output - 'ddr3_reset_n' 
-output[1] - 'ddr3_ck_p' 
-output[1] - 'ddr3_ck_n' 
-output[1] - 'ddr3_cke' 
-output[1] - 'ddr3_cs_n' 
-output[4] - 'ddr3_dm' 
-output[1] - 'ddr3_odt' 
-inout - 'FIXED_IO_ddr_vrn' 
-inout - 'FIXED_IO_ddr_vrp' 
-inout[54] - 'FIXED_IO_mio' 
-inout - 'FIXED_IO_ps_clk' 
-inout - 'FIXED_IO_ps_porb' 
-inout - 'FIXED_IO_ps_srstb' 
-output - 'custom_axi_aclk' 
-output - 'custom_axi_aresetn' 
-port.axi_inf.slaver - 'custom_axi_inf' 
-end
-

data/lib/tdl/auto_script/tmp/uart_hp_ddr3_tft800x480_hdmi_ext_sim_sdl.rb

@@ -1,43 +0,0 @@
-
-# add_to_all_file_paths('uart_hp_ddr3_tft800x480_hdmi_ext_sim','/media/kali/data/FPGA/newQQ/ch50_eth_base/coda_repo/xiaomeige/ch39/uart_hp_ddr3_tft800x480_hdmi_ext_sim.sv')
-# real_sv_path = '/media/kali/data/FPGA/newQQ/ch50_eth_base/coda_repo/xiaomeige/ch39/uart_hp_ddr3_tft800x480_hdmi_ext_sim.sv'
-TdlBuild.uart_hp_ddr3_tft800x480_hdmi_ext_sim do 
-self.real_sv_path = '/media/kali/data/FPGA/newQQ/ch50_eth_base/coda_repo/xiaomeige/ch39/uart_hp_ddr3_tft800x480_hdmi_ext_sim.sv'
-self.path = File.expand_path(__FILE__)
-input - 'reset_n' 
-output - 'led' 
-output[16] - 'TFT_rgb' 
-output - 'TFT_hs' 
-output - 'TFT_vs' 
-output - 'TFT_clk' 
-output - 'TFT_de' 
-output - 'TFT_pwm' 
-input - 'uart_rx' 
-output - 'SiI9022_sclk' 
-inout - 'SiI9022_sdat' 
-inout[32] - 'ddr3_dq' 
-inout[4] - 'ddr3_dqs_n' 
-inout[4] - 'ddr3_dqs_p' 
-output[15] - 'ddr3_addr' 
-output[3] - 'ddr3_ba' 
-output - 'ddr3_ras_n' 
-output - 'ddr3_cas_n' 
-output - 'ddr3_we_n' 
-output - 'ddr3_reset_n' 
-output[1] - 'ddr3_ck_p' 
-output[1] - 'ddr3_ck_n' 
-output[1] - 'ddr3_cke' 
-output[1] - 'ddr3_cs_n' 
-output[4] - 'ddr3_dm' 
-output[1] - 'ddr3_odt' 
-inout - 'FIXED_IO_ddr_vrn' 
-inout - 'FIXED_IO_ddr_vrp' 
-inout[54] - 'FIXED_IO_mio' 
-inout - 'FIXED_IO_ps_clk' 
-inout - 'FIXED_IO_ps_porb' 
-inout - 'FIXED_IO_ps_srstb' 
-output - 'custom_axi_aclk' 
-output - 'custom_axi_aresetn' 
-port.axi_inf.slaver - 'custom_axi_inf' 
-end
-

data/lib/tdl/auto_script/tmp/uart_rx_core_dma_verb_sdl.rb

@@ -1,13 +0,0 @@
-
-# add_to_all_file_paths('uart_rx_core_dma_verb','/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/uart_stream/uart_rx_core_dma_verb.sv')
-# real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/uart_stream/uart_rx_core_dma_verb.sv'
-TdlBuild.uart_rx_core_dma_verb do 
-self.real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/hardware/uart_stream/uart_rx_core_dma_verb.sv'
-self.path = File.expand_path(__FILE__)
-input - 'sys_clk' 
-input - 'rst_n' 
-input - 'rx_data_vld' 
-input[8] - 'rx_data' 
-port.axi_stream_inf.master - 'rx_out_inf' 
-end
-

data/lib/tdl/auto_script/tmp/uart_top_bypass_sdl.rb

@@ -1,21 +0,0 @@
-
-# add_to_all_file_paths('uart_top_bypass','/media/kali/DATA2/work/BK/work/FPGA/gw_ct_20050325/speci_0505/git_repo/hardware/arm_moto/src/uart_top_bypass.sv')
-# real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/gw_ct_20050325/speci_0505/git_repo/hardware/arm_moto/src/uart_top_bypass.sv'
-TdlBuild.uart_top_bypass do 
-self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/gw_ct_20050325/speci_0505/git_repo/hardware/arm_moto/src/uart_top_bypass.sv'
-self.path = File.expand_path(__FILE__)
-parameter.CLK_MODE   "INNER"
-input - 'sys_clk' 
-input - 'main_spi_cs' 
-input - 'main_spi_sclk' 
-input - 'main_spi_miso' 
-output - 'main_spi_mosi' 
-output[4] - 'spi_cs' 
-output[4] - 'spi_sclk' 
-input[4] - 'spi_miso' 
-output[4] - 'spi_mosi' 
-output - 'avdd_gw' 
-input - 'scl' 
-inout - 'sda' 
-end
-

data/lib/tdl/auto_script/tmp/uart_top_sdl.rb

@@ -1,21 +0,0 @@
-
-# add_to_all_file_paths('uart_top','/media/kali/DATA2/work/BK/work/FPGA/gw_ct_20050325/speci_0505/git_repo/hardware/arm_moto/src/uart_top.sv')
-# real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/gw_ct_20050325/speci_0505/git_repo/hardware/arm_moto/src/uart_top.sv'
-TdlBuild.uart_top do 
-self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/gw_ct_20050325/speci_0505/git_repo/hardware/arm_moto/src/uart_top.sv'
-self.path = File.expand_path(__FILE__)
-parameter.CLK_MODE   "INNER"
-input - 'sys_clk' 
-output - 'uart_tx' 
-input - 'uart_rx' 
-output[4] - 'spi_cs' 
-output[4] - 'spi_sclk' 
-input[4] - 'spi_miso' 
-output[4] - 'spi_mosi' 
-output - 'sync_gw' 
-output - 'resetn_chip_gw' 
-output - 'avdd_gw' 
-input - 'scl' 
-inout - 'sda' 
-end
-

data/lib/tdl/auto_script/tmp/udp_check_sum_sdl.rb

@@ -1,15 +0,0 @@
-
-# add_to_all_file_paths('udp_check_sum','/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/wmy/ethernet_protocol/udp/udp_check_sum.sv')
-# real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/wmy/ethernet_protocol/udp/udp_check_sum.sv'
-TdlBuild.udp_check_sum do 
-self.real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/wmy/ethernet_protocol/udp/udp_check_sum.sv'
-self.path = File.expand_path(__FILE__)
-input - 'clock' 
-input - 'rst_n' 
-input[32] - 'ip_s_addr' 
-input[32] - 'ip_d_addr' 
-input[16] - 'total_length' 
-input[32] - 'udp_frame_sum' 
-output[16] - 'sum' 
-end
-

data/lib/tdl/auto_script/tmp/udp_ctrl_set_A1_sdl.rb

@@ -1,18 +0,0 @@
-
-# add_to_all_file_paths('udp_ctrl_set_A1','/media/kali/data/FPGA/newQQ/ch50_eth_base/coda_repo/wmy/ethernet_protocol/udp/udp_ctrl_set_A1.sv')
-# real_sv_path = '/media/kali/data/FPGA/newQQ/ch50_eth_base/coda_repo/wmy/ethernet_protocol/udp/udp_ctrl_set_A1.sv'
-TdlBuild.udp_ctrl_set_A1 do 
-self.real_sv_path = '/media/kali/data/FPGA/newQQ/ch50_eth_base/coda_repo/wmy/ethernet_protocol/udp/udp_ctrl_set_A1.sv'
-self.path = File.expand_path(__FILE__)
-parameter.ENABLE_IDLE   "TRUE"
-parameter.TAP_IDLE   "16'h00FF"
-input - 'enable' 
-input[16] - 'source_port' 
-input[16] - 'distance_port' 
-input[16] - 'board_id' 
-port.axi_stream_inf.slaver - 'rx_udp_ctrl_inf' 
-port.axi_stream_inf.master - 'tx_udp_ctrl_inf' 
-port.axi_stream_inf.out_mirror - 'out_tap_inf' 
-port.axi_stream_inf.slaver - 'in_tap_inf' 
-end
-

data/lib/tdl/auto_script/tmp/udp_fpga_ports_route_sdl.rb

@@ -1,12 +0,0 @@
-
-# add_to_all_file_paths('udp_fpga_ports_route','/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/wmy/ethernet_protocol/udp/udp_fpga_ports_route.sv')
-# real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/wmy/ethernet_protocol/udp/udp_fpga_ports_route.sv'
-TdlBuild.udp_fpga_ports_route do 
-self.real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/wmy/ethernet_protocol/udp/udp_fpga_ports_route.sv'
-self.path = File.expand_path(__FILE__)
-parameter.PNUM   8
-input[ param.PNUM][16] - 'fpga_ports' 
-port.axi_stream_inf.slaver - 'udp_inf' 
-port.axi_stream_inf.master[( param.PNUM+1-0)] - 'udp_data_inf' 
-end
-

data/lib/tdl/auto_script/tmp/udp_socket_ddr_pump_64b_sdl.rb

@@ -1,16 +0,0 @@
-
-# add_to_all_file_paths('udp_socket_ddr_pump_64b','/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/wmy/ethernet_protocol/udp/udp_socket_ddr_pump_64b.sv')
-# real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/wmy/ethernet_protocol/udp/udp_socket_ddr_pump_64b.sv'
-TdlBuild.udp_socket_ddr_pump_64b do 
-self.real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/wmy/ethernet_protocol/udp/udp_socket_ddr_pump_64b.sv'
-self.path = File.expand_path(__FILE__)
-parameter.AXIS_SPLIT_LEN   1024/8
-parameter.LONG_FIFO_BYTE_DEPTH   8192*8
-input[16] - 'source_port' 
-input[8][16] - 'distance_port' 
-input[16] - 'board_id' 
-port.axi_stream_inf.master - 'udp_data_inf' 
-port.axi_inf.master_rd - 'ddr_dma_inf' 
-port.data_inf_c.slaver - 'req_data_inf' 
-end
-

data/lib/tdl/auto_script/tmp/udp_socket_ddr_pump_A3_sdl.rb

@@ -1,14 +0,0 @@
-
-# add_to_all_file_paths('udp_socket_ddr_pump_A3','/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/wmy/ethernet_protocol/udp/udp_socket_ddr_pump_A3.sv')
-# real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/wmy/ethernet_protocol/udp/udp_socket_ddr_pump_A3.sv'
-TdlBuild.udp_socket_ddr_pump_A3 do 
-self.real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/wmy/ethernet_protocol/udp/udp_socket_ddr_pump_A3.sv'
-self.path = File.expand_path(__FILE__)
-input[16] - 'source_port' 
-input[8][16] - 'distance_port' 
-input[16] - 'board_id' 
-port.axi_stream_inf.master - 'udp_data_inf' 
-port.axi_inf.master - 'ddr_dma_inf' 
-port.data_inf_c.slaver - 'req_data_inf' 
-end
-

data/lib/tdl/auto_script/tmp/udp_socket_ddr_pump_B1_sdl.rb

@@ -1,14 +0,0 @@
-
-# add_to_all_file_paths('udp_socket_ddr_pump_B1','/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/wmy/ethernet_protocol/udp/udp_socket_ddr_pump_B1.sv')
-# real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/wmy/ethernet_protocol/udp/udp_socket_ddr_pump_B1.sv'
-TdlBuild.udp_socket_ddr_pump_B1 do 
-self.real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/wmy/ethernet_protocol/udp/udp_socket_ddr_pump_B1.sv'
-self.path = File.expand_path(__FILE__)
-input[16] - 'source_port' 
-input[8][16] - 'distance_port' 
-input[16] - 'board_id' 
-port.axi_stream_inf.master - 'udp_data_inf' 
-port.axi_inf.master_rd - 'ddr_dma_inf' 
-port.data_inf_c.slaver - 'req_data_inf' 
-end
-

data/lib/tdl/auto_script/tmp/udp_socket_ddr_pump_verb_sdl.rb

@@ -1,14 +0,0 @@
-
-# add_to_all_file_paths('udp_socket_ddr_pump_verb','/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/wmy/ethernet_protocol/udp/udp_socket_ddr_pump_verb.sv')
-# real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/wmy/ethernet_protocol/udp/udp_socket_ddr_pump_verb.sv'
-TdlBuild.udp_socket_ddr_pump_verb do 
-self.real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/wmy/ethernet_protocol/udp/udp_socket_ddr_pump_verb.sv'
-self.path = File.expand_path(__FILE__)
-input[16] - 'source_port' 
-input[8][16] - 'distance_port' 
-input[16] - 'board_id' 
-port.axi_stream_inf.master - 'udp_data_inf' 
-port.axi_inf.master - 'ddr_dma_inf' 
-port.data_inf_c.slaver - 'req_data_inf' 
-end
-

data/lib/tdl/auto_script/tmp/unpack_mac_ip_udp_D1_sdl.rb

@@ -1,16 +0,0 @@
-
-# add_to_all_file_paths('unpack_mac_ip_udp_D1','/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/wmy/ethernet_protocol/ethernet_proto/unpack_mac_ip_udp_D1.sv')
-# real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/wmy/ethernet_protocol/ethernet_proto/unpack_mac_ip_udp_D1.sv'
-TdlBuild.unpack_mac_ip_udp_D1 do 
-self.real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/wmy/ethernet_protocol/ethernet_proto/unpack_mac_ip_udp_D1.sv'
-self.path = File.expand_path(__FILE__)
-parameter.PNUM   8
-input[48] - 'local_mac_addr' 
-input[ param.PNUM][16] - 'fpga_ports' 
-output[48] - 'remote_mac_addr' 
-output[32] - 'remote_ip' 
-output - 'remote_valid' 
-port.axi_stream_inf.slaver - 'rx_inf' 
-port.axi_stream_inf.master[( param.PNUM+1-0)] - 'udp_out' 
-end
-

data/lib/tdl/auto_script/tmp/unpack_mac_ip_udp_tcp_sdl.rb

@@ -1,15 +0,0 @@
-
-# add_to_all_file_paths('unpack_mac_ip_udp_tcp','/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/wmy/ethernet_protocol/ethernet_proto/unpack_mac_ip_udp_tcp.sv')
-# real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/wmy/ethernet_protocol/ethernet_proto/unpack_mac_ip_udp_tcp.sv'
-TdlBuild.unpack_mac_ip_udp_tcp do 
-self.real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/wmy/ethernet_protocol/ethernet_proto/unpack_mac_ip_udp_tcp.sv'
-self.path = File.expand_path(__FILE__)
-input[48] - 'local_mac_addr' 
-output[48] - 'remote_mac_addr' 
-output[32] - 'remote_ip' 
-output - 'remote_valid' 
-port.axi_stream_inf.slaver - 'rx_inf' 
-port.axi_stream_inf.master - 'udp_inf' 
-port.axi_stream_inf.master - 'tcp_inf' 
-end
-

data/lib/tdl/auto_script/tmp/unpack_mac_ip_udp_verd_sdl.rb

@@ -1,13 +0,0 @@
-
-# add_to_all_file_paths('unpack_mac_ip_udp_verd','/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/wmy/ethernet_protocol/ethernet_proto/unpack_mac_ip_udp_verd.sv')
-# real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/wmy/ethernet_protocol/ethernet_proto/unpack_mac_ip_udp_verd.sv'
-TdlBuild.unpack_mac_ip_udp_verd do 
-self.real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/wmy/ethernet_protocol/ethernet_proto/unpack_mac_ip_udp_verd.sv'
-self.path = File.expand_path(__FILE__)
-parameter.PNUM   8
-input[48] - 'local_mac_addr' 
-input[ param.PNUM][16] - 'fpga_ports' 
-port.axi_stream_inf.slaver - 'rx_inf' 
-port.axi_stream_inf.master[( param.PNUM+1-0)] - 'udp_out' 
-end
-

data/lib/tdl/auto_script/tmp/vio_wrapper_sdl.rb

@@ -1,11 +0,0 @@
-
-# add_to_all_file_paths('vio_wrapper','/media/kali/data/FPGA/newQQ/ch50_eth_base/coda_repo/wmy/simple_ddr_wr/vio_wrapper.sv')
-# real_sv_path = '/media/kali/data/FPGA/newQQ/ch50_eth_base/coda_repo/wmy/simple_ddr_wr/vio_wrapper.sv'
-TdlBuild.vio_wrapper do 
-self.real_sv_path = '/media/kali/data/FPGA/newQQ/ch50_eth_base/coda_repo/wmy/simple_ddr_wr/vio_wrapper.sv'
-self.path = File.expand_path(__FILE__)
-input - 'clock' 
-input - 'vio_in' 
-output - 'vio_out' 
-end
-

data/lib/tdl/auto_script/tmp/wide_axis_to_axi4_wr_sdl.rb

@@ -1,12 +0,0 @@
-
-# add_to_all_file_paths('wide_axis_to_axi4_wr','/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/AXI4/wide_axis_to_axi4_wr.sv')
-# real_sv_path = '/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/AXI4/wide_axis_to_axi4_wr.sv'
-TdlBuild.wide_axis_to_axi4_wr do 
-self.real_sv_path = '/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/AXI4/wide_axis_to_axi4_wr.sv'
-self.path = File.expand_path(__FILE__)
-input[32] - 'addr' 
-input[32] - 'max_length' 
-port.axi_stream_inf.slaver - 'axis_in' 
-port.axi_inf.master_wr - 'axi_wr' 
-end
-

data/lib/tdl/auto_script/tmp/wide_fifo_sdl.rb

@@ -1,19 +0,0 @@
-
-# add_to_all_file_paths('wide_fifo','/var/lib/gems/2.7.0/gems/axi_tdl-0.2.4/lib/axi/platform_ip/wide_fifo.sv')
-# real_sv_path = '/var/lib/gems/2.7.0/gems/axi_tdl-0.2.4/lib/axi/platform_ip/wide_fifo.sv'
-TdlBuild.wide_fifo do 
-self.real_sv_path = '/var/lib/gems/2.7.0/gems/axi_tdl-0.2.4/lib/axi/platform_ip/wide_fifo.sv'
-self.path = File.expand_path(__FILE__)
-parameter.DSIZE   1024
-input - 'wr_clk' 
-input - 'wr_rst' 
-input - 'rd_clk' 
-input - 'rd_rst' 
-input[ param.DSIZE] - 'din' 
-input - 'wr_en' 
-input - 'rd_en' 
-output[ param.DSIZE] - 'dout' 
-output - 'full' 
-output - 'empty' 
-end
-

data/lib/tdl/auto_script/tmp/width_combin_sdl.rb

@@ -1,21 +0,0 @@
-
-# add_to_all_file_paths('width_combin','/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/AXI4/width_convert/width_combin.sv')
-# real_sv_path = '/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/AXI4/width_convert/width_combin.sv'
-TdlBuild.width_combin do 
-self.real_sv_path = '/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/AXI4/width_convert/width_combin.sv'
-self.path = File.expand_path(__FILE__)
-parameter.DSIZE   1
-parameter.NSIZE   8
-input - 'clock' 
-input - 'rst_n' 
-input[ param.DSIZE] - 'wr_data' 
-input - 'wr_vld' 
-output - 'wr_ready' 
-input - 'wr_last' 
-input - 'wr_align_last' 
-output[ param.DSIZE* param.NSIZE] - 'rd_data' 
-output - 'rd_vld' 
-input - 'rd_ready' 
-output - 'rd_last' 
-end
-

data/lib/tdl/auto_script/tmp/width_convert_sdl.rb

@@ -1,21 +0,0 @@
-
-# add_to_all_file_paths('width_convert','/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/AXI4/width_convert/width_convert.sv')
-# real_sv_path = '/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/AXI4/width_convert/width_convert.sv'
-TdlBuild.width_convert do 
-self.real_sv_path = '/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/AXI4/width_convert/width_convert.sv'
-self.path = File.expand_path(__FILE__)
-parameter.ISIZE   8
-parameter.OSIZE   8
-input - 'clock' 
-input - 'rst_n' 
-input[ param.ISIZE] - 'wr_data' 
-input - 'wr_vld' 
-output - 'wr_ready' 
-input - 'wr_last' 
-input - 'wr_align_last' 
-output[ param.OSIZE] - 'rd_data' 
-output - 'rd_vld' 
-input - 'rd_ready' 
-output - 'rd_last' 
-end
-

data/lib/tdl/auto_script/tmp/xilinx_dna_capture_sdl.rb

@@ -1,12 +0,0 @@
-
-# add_to_all_file_paths('xilinx_dna_capture','/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/wmy/xilinx_7series_dna/xilinx_dna_capture.sv')
-# real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/wmy/xilinx_7series_dna/xilinx_dna_capture.sv'
-TdlBuild.xilinx_dna_capture do 
-self.real_sv_path = '/media/kali/data/FPGA/newQQ/acceRed450_20250516/git_repo/wmy/xilinx_7series_dna/xilinx_dna_capture.sv'
-self.path = File.expand_path(__FILE__)
-input - 'sys_clk' 
-input - 'dna_rdy' 
-output[57] - 'dna_data' 
-output - 'dna_valid' 
-end
-

data/lib/tdl/auto_script/tmp/xilinx_eth_clock_sdl.rb

@@ -1,13 +0,0 @@
-
-# add_to_all_file_paths('xilinx_eth_clock','/media/kali/DATA2/work/BK/work/FPGA/Red8_x4_Eth4_20240923/git_repo/hardware/multi_ethernet_1g/xilinx_eth_clock_reset/xilinx_eth_clock.sv')
-# real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/Red8_x4_Eth4_20240923/git_repo/hardware/multi_ethernet_1g/xilinx_eth_clock_reset/xilinx_eth_clock.sv'
-TdlBuild.xilinx_eth_clock do 
-self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/Red8_x4_Eth4_20240923/git_repo/hardware/multi_ethernet_1g/xilinx_eth_clock_reset/xilinx_eth_clock.sv'
-self.path = File.expand_path(__FILE__)
-input - 'clk_in1' 
-output - 'clk_out1' 
-output - 'clk_out2' 
-input - 'reset' 
-output - 'locked' 
-end
-

data/lib/tdl/auto_script/tmp/xilinx_eth_reset_sdl.rb

@@ -1,15 +0,0 @@
-
-# add_to_all_file_paths('xilinx_eth_reset','/media/kali/DATA2/work/BK/work/FPGA/Red8_x4_Eth4_20240923/git_repo/hardware/multi_ethernet_1g/xilinx_eth_clock_reset/xilinx_eth_reset.sv')
-# real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/Red8_x4_Eth4_20240923/git_repo/hardware/multi_ethernet_1g/xilinx_eth_clock_reset/xilinx_eth_reset.sv'
-TdlBuild.xilinx_eth_reset do 
-self.real_sv_path = '/media/kali/DATA2/work/BK/work/FPGA/Red8_x4_Eth4_20240923/git_repo/hardware/multi_ethernet_1g/xilinx_eth_clock_reset/xilinx_eth_reset.sv'
-self.path = File.expand_path(__FILE__)
-input - 'glbl_rstn' 
-input - 'refclk' 
-input - 'idelayctrl_ready' 
-output - 'idelayctrl_reset_out' 
-input - 'gtx_clk' 
-input - 'gtx_dcm_locked' 
-output - 'gtx_mmcm_rst_out' 
-end
-

data/lib/tdl/auto_script/tmp/xilinx_fifo_A1_sdl.rb

@@ -1,22 +0,0 @@
-
-# add_to_all_file_paths('xilinx_fifo_A1','/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/platform_ip/xilinx_fifo_A1.sv')
-# real_sv_path = '/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/platform_ip/xilinx_fifo_A1.sv'
-TdlBuild.xilinx_fifo_A1 do 
-self.real_sv_path = '/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/platform_ip/xilinx_fifo_A1.sv'
-self.path = File.expand_path(__FILE__)
-parameter.DSIZE   128
-parameter.LSIZE   "(DSIZE>= 37             )?  9 :"
-input - 'wr_clk' 
-input - 'wr_rst' 
-input - 'rd_clk' 
-input - 'rd_rst' 
-input[ param.DSIZE] - 'din' 
-input - 'wr_en' 
-input - 'rd_en' 
-output[ param.DSIZE] - 'dout' 
-output - 'full' 
-output - 'empty' 
-output[ param.LSIZE] - 'wcount' 
-output[ param.LSIZE] - 'rcount' 
-end
-

data/lib/tdl/auto_script/tmp/xilinx_fifo_sdl.rb

@@ -1,20 +0,0 @@
-
-# add_to_all_file_paths('xilinx_fifo','/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/platform_ip/xilinx_fifo.sv')
-# real_sv_path = '/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/platform_ip/xilinx_fifo.sv'
-TdlBuild.xilinx_fifo do 
-self.real_sv_path = '/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/platform_ip/xilinx_fifo.sv'
-self.path = File.expand_path(__FILE__)
-parameter.ENABLE_SIM   "FALSE"
-parameter.DSIZE   128
-input - 'wr_clk' 
-input - 'wr_rst' 
-input - 'rd_clk' 
-input - 'rd_rst' 
-input[ param.DSIZE] - 'din' 
-input - 'wr_en' 
-input - 'rd_en' 
-output[ param.DSIZE] - 'dout' 
-output - 'full' 
-output - 'empty' 
-end
-

data/lib/tdl/auto_script/tmp/xilinx_fifo_verb_sdl.rb

@@ -1,23 +0,0 @@
-
-# add_to_all_file_paths('xilinx_fifo_verb','/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/platform_ip/xilinx_fifo_verb.sv')
-# real_sv_path = '/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/platform_ip/xilinx_fifo_verb.sv'
-TdlBuild.xilinx_fifo_verb do 
-self.real_sv_path = '/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/platform_ip/xilinx_fifo_verb.sv'
-self.path = File.expand_path(__FILE__)
-parameter.DSIZE   18
-parameter.LENGTH   1024
-parameter.LSIZE   NqString.new('$clog2(LENGTH+1)')
-input - 'wr_clk' 
-input - 'wr_rst' 
-input - 'rd_clk' 
-input - 'rd_rst' 
-input[ param.DSIZE] - 'din' 
-input - 'wr_en' 
-input - 'rd_en' 
-output[ param.DSIZE] - 'dout' 
-output - 'full' 
-output - 'empty' 
-output[ param.LSIZE] - 'rdcount' 
-output[ param.LSIZE] - 'wrcount' 
-end
-

data/lib/tdl/auto_script/tmp/xilinx_fifo_verc_sdl.rb

@@ -1,21 +0,0 @@
-
-# add_to_all_file_paths('xilinx_fifo_verc','/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/platform_ip/xilinx_fifo_verc.sv')
-# real_sv_path = '/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/platform_ip/xilinx_fifo_verc.sv'
-TdlBuild.xilinx_fifo_verc do 
-self.real_sv_path = '/home/kali/.rbenv/versions/3.3.1/lib/ruby/gems/3.3.0/gems/axi_tdl-0.2.5/lib/axi/platform_ip/xilinx_fifo_verc.sv'
-self.path = File.expand_path(__FILE__)
-parameter.DEPTH   4
-parameter.DSIZE   18
-parameter.LENGTH   1024             
-input - 'wr_clk' 
-input - 'wr_rst' 
-input - 'rd_clk' 
-input - 'rd_rst' 
-input[ param.DSIZE] - 'din' 
-input - 'wr_en' 
-input - 'rd_en' 
-output[ param.DSIZE] - 'dout' 
-output - 'full' 
-output - 'empty' 
-end
-