axi_tdl 0.0.15 → 0.0.19

data/lib/tdl/exlib/itegration.rb

@@ -12,8 +12,10 @@ class StringBandItegration < String
             obj
         end
 
-        stringbanditegration.itgt.define_singleton_method(stringbanditegration.key) do
-            obj
+        if stringbanditegration.origin_str.to_s != stringbanditegration.key.to_s
+            stringbanditegration.itgt.define_singleton_method(stringbanditegration.key) do
+                obj
+            end
         end
         obj
     end
@@ -271,7 +273,17 @@ class String ## add to itegration names_pool
     def snoop(itgt=nil,sdlmodule=nil)
         itgt ||= $_implicit_curr_itgt_.last
         if sdlmodule
-            sdlmodule.signal(itgt.names_pool[self])
+            # unless sdlmodule.has_signal?(itgt.names_pool[self])
+            unless sdlmodule.respond_to?(itgt.names_pool[self])
+                if sdlmodule.is_a?(TopModule) && sdlmodule.techbench.respond_to?(itgt.names_pool[self])
+                    sdlmodule.techbench.signal(itgt.names_pool[self])
+                else 
+                    sdlmodule.signal(itgt.names_pool[self])
+                    # raise TdlError.new("Dont have `#{itgt.names_pool[self]}` in module <#{sdlmodule.module_name}>" )
+                end
+            else 
+                sdlmodule.signal(itgt.names_pool[self])
+            end
         else
             itgt.top_module.signal(itgt.names_pool[self])
         end

data/lib/tdl/exlib/logic_verify.rb

@@ -0,0 +1,88 @@
+
+module AxiTdl
+
+    module LogicVerify 
+
+        class Iteration
+
+            def initialize(length: 1024, data: [0], dsize: 8)
+                @data = data.to_a * (length / data.size + 1)
+                @length = length
+                @dsize = dsize
+            end
+
+            def to_a 
+                collect = []
+                index = 0
+                while true 
+                    
+                    collect << [ index, @data[index] ]
+                    
+                    if @length <= index + 1
+                        break 
+                    end
+                    index += 1
+                end
+
+                collect 
+            end
+
+            def context
+                collect = []
+                to_a.each do |index, data|
+                    u0 = data % (2**@dsize)
+                    collect << u0
+                end
+
+                collect.map do |e| 
+                    "%0#{(@dsize )/4  + ( ((@dsize)%4 == 0) ? 0 : 1 )}x"%e
+                end
+                # collect
+            end
+
+            def coe 
+                collect = []
+                xxx = context
+                xxx.each_index do |index|
+                    collect << "@%04x #{xxx[index]}\n"%index
+                end
+                collect.join("")
+            end
+
+        end
+    end
+end
+
+class Logic 
+
+    def to_sim_source_coe(data: (0...100).to_a, posedge: nil ,negedge: nil ,loop_coe: true)
+        raise TdlError.new(" posedge negedge both nil") unless (posedge || negedge )
+        # raise TdlError.new "file cant be empty"  unless file
+
+        file = File.join(AxiTdl::TDL_PATH,"./auto_script/tmp/","#{self.name}_#{globle_random_name_flag}.coe")
+        _len = 1000
+        ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do
+            require_hdl 'logic_sim_model.sv'
+            itr = AxiTdl::LogicVerify::Iteration.new(length: data.size, data: data )
+            File.open(file,'w') do |f|
+                f.puts itr.coe
+            end
+            _len = itr.context.size
+        end
+
+        @belong_to_module.instance_exec(self,_len, posedge || 1.b0 , negedge || 1.b0 ,file, loop_coe) do |_self,_len,next_at_posedge_of,next_at_negedge_of,file,loop_coe|
+            Instance(:logic_sim_model, "#{_self.name}_sim_model_inst") do |h|
+                h.param.LOOP                (loop_coe ? "TRUE" : "FALSE")
+                h.param.DSIZE           _self.dsize
+                h.param.RAM_DEPTH       _len
+                h.input.next_at_negedge_of  next_at_negedge_of
+                h.input.next_at_posedge_of  next_at_posedge_of
+                h.input.load_trigger        1.b0
+                h.input[32].total_length    _len
+                h.input[512*8].mem_file     File.expand_path(file)
+                h.output['DSIZE'].data      _self
+            end
+
+        end
+    end
+end

data/lib/tdl/exlib/test_point.rb

@@ -1,113 +1,115 @@
-class TdlTestPoint
-    @@name_collect = []
-    @@inst_collect = []
-
-    attr_reader :name,:descript,:target,:file,:line
-    attr_accessor :filter_block
-    def initialize(target: nil, name: 'test_point',descript: '',file: nil, line: nil)
-        @name = name.to_s 
-        if @@name_collect.include? @name 
-            raise TdlError.new "Cant redefine test point with name <#{@name}>"
-        end
-        @target = target
-        @descript = descript
-        @file = File.expand_path(file) if file 
-        @line = line
+# class TdlTestPoint
+#     # @@name_collect = []
+#     # @@inst_collect = []
 
-        unless @target.respond_to? :belong_to_module
-            raise TdlError.new "Test point<#{@name}> is not respond to belong_to_module"
-        end
+#     # attr_reader :name,:descript,:target,:file,:line
+#     # attr_accessor :filter_block
+#     # def initialize(target: nil, name: 'test_point',descript: '',file: nil, line: nil)
+#     #     @name = name.to_s 
+#     #     if @@name_collect.include? @name 
+#     #         raise TdlError.new "Cant redefine test point with name <#{@name}>"
+#     #     end
+#     #     @target = target
+#     #     @descript = descript
+#     #     @file = File.expand_path(file) if file 
+#     #     @line = line
 
-        ## when test unit in topmodule or topmodule techbench
-        if  target.belong_to_module.is_a?(TopModule) || (TopModule.current && (target.belong_to_module == TopModule.current.techbench))
-            TdlTestPoint.define_singleton_method(name) { target }
-        end
+#     #     unless @target.respond_to? :belong_to_module
+#     #         raise TdlError.new "Test point<#{@name}> is not respond to belong_to_module"
+#     #     end
+
+#     #     ## when test unit in topmodule or topmodule techbench
+#     #     if  target.belong_to_module.is_a?(TopModule) || (TopModule.current && (target.belong_to_module == TopModule.current.techbench))
+#     #         TdlTestPoint.define_singleton_method(name) { target }
+#     #     end
      
-        TdlTestPoint.define_singleton_method(target.belong_to_module.module_name ) { target.belong_to_module }
-        target.belong_to_module.define_singleton_method(name) { target }
-        _self = self
-        target.define_singleton_method('tp_instance') { _self }
+#     #     TdlTestPoint.define_singleton_method(target.belong_to_module.module_name ) { target.belong_to_module }
+#     #     target.belong_to_module.define_singleton_method(name) { target }
+#     #     _self = self
+#     #     target.define_singleton_method('tp_instance') { _self }
 
-        @@inst_collect << self
-    end
+#     #     @@inst_collect << self
+#     # end
 
-    def self.echo_list
-        ml = ['  MODULE']
-        nl = ['NAME']
-        dl = ['DESCRIPT']
-        fl = ['FILE']
-
-        mll = 8
-        nll = 4
-        dll = 8
-        @@inst_collect.each do |e|
-            unless e.target.belong_to_module.top_tb_ref?
-                next 
-            end
-            inst_cnt = e.target.belong_to_module.instance_variable_get("@instance_cnt")
-            if !inst_cnt || inst_cnt == 0
-                next
-            end
-            ml << e.target.belong_to_module.module_name
-            nl << e.name 
-            dl << e.descript
-            if e.file
-                fl << "#{e.file}:#{e.line}"
-            else
-                fl << 'Null'
-            end
+#     def self.echo_list
+#         # ml = ['  MODULE']
+#         # nl = ['NAME']
+#         # dl = ['DESCRIPT']
+#         # fl = ['FILE']
 
-            mll = e.target.belong_to_module.module_name.size if e.target.belong_to_module.module_name.size > mll
-            nll = e.name.size if e.name.size > nll
-            dll = e.descript.size if e.descript.size > dll 
-        end
+#         # mll = 8
+#         # nll = 4
+#         # dll = 8
+#         # @@inst_collect.each do |e|
+#         #     unless e.target.belong_to_module.top_tb_ref?
+#         #         next 
+#         #     end
+#         #     inst_cnt = e.target.belong_to_module.instance_variable_get("@instance_cnt")
+#         #     if !inst_cnt || inst_cnt == 0
+#         #         next
+#         #     end
+#         #     ml << e.target.belong_to_module.module_name
+#         #     nl << e.name 
+#         #     dl << e.descript
+#         #     if e.file
+#         #         fl << "#{e.file}:#{e.line}"
+#         #     else
+#         #         fl << 'Null'
+#         #     end
 
-        ccl = []
-        ml.each_index do |index|
-            # if index != 0
-                ccl << "[#{sprintf("%3d",index)}]#{ml[index]} #{' '*(mll-ml[index].size)}| #{nl[index]} #{' '*(nll-nl[index].size)}| #{dl[index]} #{' '*(dll-dl[index].size)}| #{fl[index]}"
-            # else 
-            #     ccl << "#{ml[index]} #{' '*(mll-ml[index].size)}| #{nl[index]} #{' '*(nll-nl[index].size)}| #{dl[index]} #{' '*(dll-dl[index].size)}| #{fl[index]}"
-            # end
-        end
-        ccl.join("\n")
-    end
+#         #     mll = e.target.belong_to_module.module_name.size if e.target.belong_to_module.module_name.size > mll
+#         #     nll = e.name.size if e.name.size > nll
+#         #     dll = e.descript.size if e.descript.size > dll 
+#         # end
 
-    def self.inst_collect
-        @@inst_collect
-    end
+#         # ccl = []
+#         # ml.each_index do |index|
+#         #     # if index != 0
+#         #         ccl << "[#{sprintf("%3d",index)}]#{ml[index]} #{' '*(mll-ml[index].size)}| #{nl[index]} #{' '*(nll-nl[index].size)}| #{dl[index]} #{' '*(dll-dl[index].size)}| #{fl[index]}"
+#         #     # else 
+#         #     #     ccl << "#{ml[index]} #{' '*(mll-ml[index].size)}| #{nl[index]} #{' '*(nll-nl[index].size)}| #{dl[index]} #{' '*(dll-dl[index].size)}| #{fl[index]}"
+#         #     # end
+#         # end
+#         # ccl.join("\n")
 
-end
+#         "TODO SOME"
+#     end
+
+#     # def self.inst_collect
+#     #     @@inst_collect
+#     # end
+
+# end
 
 module TdlSpace
 
-    class ExCreateTPSurge
+    # class ExCreateTPSurge
 
-        def initialize(target: nil, descript: '', file: nil, line: nil)
-            @target = target
-            @descript = descript
-            @file = file 
-            @line = line
-        end
+    #     def initialize(target: nil, descript: '', file: nil, line: nil)
+    #         @target = target
+    #         @descript = descript
+    #         @file = file 
+    #         @line = line
+    #     end
 
-        def -(name)
-            TdlTestPoint.new(target: @target, name: name, descript: @descript, file: @file, line: @line)
-        end
+    #     def -(name)
+    #         TdlTestPoint.new(target: @target, name: name, descript: @descript, file: @file, line: @line)
+    #     end
 
-        def method_missing(method,*args,&block)
-            if method.to_s !~ /[a-z]\w+/
-                raise TdlError.new "Test point name<#{method}> is illegal"
-            end
-            self - method
-        end
-    end
+    #     def method_missing(method,*args,&block)
+    #         if method.to_s !~ /[a-z]\w+/
+    #             raise TdlError.new "Test point name<#{method}> is illegal"
+    #         end
+    #         self - method
+    #     end
+    # end
 
     module ExCreateTP 
 
-        def create_tp(desc='',file=nil,line=nil)
-            # TdlTestPoint.new(target: self, name: name, descript: desc, file: file, line: line)
-            ExCreateTPSurge.new(target: self, descript: desc, file: file, line: line)
-        end
+        # def create_tp(desc='',file=nil,line=nil)
+        #     # TdlTestPoint.new(target: self, name: name, descript: desc, file: file, line: line)
+        #     ExCreateTPSurge.new(target: self, descript: desc, file: file, line: line)
+        # end
 
         ## 定义获取 信号的绝对路径
         def root_ref(&block)
@@ -149,7 +151,7 @@ class BaseElm
                         ll << rt[index].inst_name
                     end
                 end
-                ll << signal
+                ll << @name
                 new_name = ll.join('.').to_nq
                 if block_given?
                     if yield(new_name)
@@ -160,7 +162,7 @@ class BaseElm
                 end
             end
         else
-            collects = ["$root.#{@belong_to_module.module_name}.#{signal}".to_nq]
+            collects = ["$root.#{@belong_to_module.module_name}.#{@name}".to_nq]
         end
         collects
     end

data/lib/tdl/exlib/test_point.rb.bak

@@ -0,0 +1,293 @@
+class TdlTestPoint
+    @@name_collect = []
+    @@inst_collect = []
+
+    attr_reader :name,:descript,:target,:file,:line
+    attr_accessor :filter_block
+    def initialize(target: nil, name: 'test_point',descript: '',file: nil, line: nil)
+        @name = name.to_s 
+        if @@name_collect.include? @name 
+            raise TdlError.new "Cant redefine test point with name <#{@name}>"
+        end
+        @target = target
+        @descript = descript
+        @file = File.expand_path(file) if file 
+        @line = line
+
+        unless @target.respond_to? :belong_to_module
+            raise TdlError.new "Test point<#{@name}> is not respond to belong_to_module"
+        end
+
+        ## when test unit in topmodule or topmodule techbench
+        if  target.belong_to_module.is_a?(TopModule) || (TopModule.current && (target.belong_to_module == TopModule.current.techbench))
+            TdlTestPoint.define_singleton_method(name) { target }
+        end
+     
+        TdlTestPoint.define_singleton_method(target.belong_to_module.module_name ) { target.belong_to_module }
+        target.belong_to_module.define_singleton_method(name) { target }
+        _self = self
+        target.define_singleton_method('tp_instance') { _self }
+
+        @@inst_collect << self
+    end
+
+    def self.echo_list
+        ml = ['  MODULE']
+        nl = ['NAME']
+        dl = ['DESCRIPT']
+        fl = ['FILE']
+
+        mll = 8
+        nll = 4
+        dll = 8
+        @@inst_collect.each do |e|
+            unless e.target.belong_to_module.top_tb_ref?
+                next 
+            end
+            inst_cnt = e.target.belong_to_module.instance_variable_get("@instance_cnt")
+            if !inst_cnt || inst_cnt == 0
+                next
+            end
+            ml << e.target.belong_to_module.module_name
+            nl << e.name 
+            dl << e.descript
+            if e.file
+                fl << "#{e.file}:#{e.line}"
+            else
+                fl << 'Null'
+            end
+
+            mll = e.target.belong_to_module.module_name.size if e.target.belong_to_module.module_name.size > mll
+            nll = e.name.size if e.name.size > nll
+            dll = e.descript.size if e.descript.size > dll 
+        end
+
+        ccl = []
+        ml.each_index do |index|
+            # if index != 0
+                ccl << "[#{sprintf("%3d",index)}]#{ml[index]} #{' '*(mll-ml[index].size)}| #{nl[index]} #{' '*(nll-nl[index].size)}| #{dl[index]} #{' '*(dll-dl[index].size)}| #{fl[index]}"
+            # else 
+            #     ccl << "#{ml[index]} #{' '*(mll-ml[index].size)}| #{nl[index]} #{' '*(nll-nl[index].size)}| #{dl[index]} #{' '*(dll-dl[index].size)}| #{fl[index]}"
+            # end
+        end
+        ccl.join("\n")
+    end
+
+    def self.inst_collect
+        @@inst_collect
+    end
+
+end
+
+module TdlSpace
+
+    class ExCreateTPSurge
+
+        def initialize(target: nil, descript: '', file: nil, line: nil)
+            @target = target
+            @descript = descript
+            @file = file 
+            @line = line
+        end
+
+        def -(name)
+            TdlTestPoint.new(target: @target, name: name, descript: @descript, file: @file, line: @line)
+        end
+
+        def method_missing(method,*args,&block)
+            if method.to_s !~ /[a-z]\w+/
+                raise TdlError.new "Test point name<#{method}> is illegal"
+            end
+            self - method
+        end
+    end
+
+    module ExCreateTP 
+
+        # def create_tp(desc='',file=nil,line=nil)
+        #     # TdlTestPoint.new(target: self, name: name, descript: desc, file: file, line: line)
+        #     ExCreateTPSurge.new(target: self, descript: desc, file: file, line: line)
+        # end
+
+        ## 定义获取 信号的绝对路径
+        def root_ref(&block)
+            ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do 
+                rels = path_refs(&block)
+                if block_given?
+                    sst = "block given"
+                else
+                    sst = "no block"
+                end
+
+                if rels.size == 1
+                    rels[0]
+                elsif rels.size == 0
+                    raise TdlError.new "#{self} Cant find root ref {#{sst}}"
+                else
+                    raise TdlError.new "#{self} Find multi root refs {#{sst}} \n#{rels.join("\n")}\n"
+                end
+            end
+        end
+    end
+
+end
+
+class BaseElm
+    include TdlSpace::ExCreateTP
+
+    ## 获取信号的绝对路径
+    def path_refs(&block)
+        collects = []
+        if @belong_to_module != TopModule.current.techbench
+            @belong_to_module.parents_inst_tree do |tree|
+                ll = ["$root"]
+                rt = tree.reverse
+                rt.each_index do |index|
+                    if rt[index].respond_to? :module_name
+                        ll << rt[index].module_name 
+                    else 
+                        ll << rt[index].inst_name
+                    end
+                end
+                ll << @name
+                new_name = ll.join('.').to_nq
+                if block_given?
+                    if yield(new_name)
+                        collects << new_name
+                    end 
+                else
+                    collects << new_name
+                end
+            end
+        else
+            collects = ["$root.#{@belong_to_module.module_name}.#{@name}".to_nq]
+        end
+        collects
+    end
+    
+end
+
+module TdlSpace
+    class TdlBaseInterface
+        include ExCreateTP
+
+        ## 获取信号的绝对路径
+        def path_refs(&block)
+            collects = []
+            if @belong_to_module != TopModule.current.techbench
+                @belong_to_module.parents_inst_tree do |tree|
+                    ll = ["$root"]
+                    rt = tree.reverse
+                    rt.each_index do |index|
+                        if rt[index].respond_to? :module_name
+                            ll << rt[index].module_name 
+                        else 
+                            ll << rt[index].inst_name
+                        end
+                    end
+                    ll << inst_name
+                    new_name = ll.join('.').to_nq
+                    if block_given?
+                        if yield(new_name)
+                            collects << new_name
+                        end 
+                    else
+                        collects << new_name
+                    end
+                end
+            else
+                collects = ["$root.#{@belong_to_module.module_name}.#{inst_name}".to_nq]
+            end
+            collects
+        end
+    end
+end
+
+module ClassHDL
+    class EnumStruct
+        include TdlSpace::ExCreateTP
+
+        def root_ref(nstateq=true,&block)
+            ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do 
+                rels = path_refs(nstateq,&block)
+                if rels.size == 1
+                    rels[0]
+                elsif rels.size == 0
+                    raise TdlError.new "#{self} Cant find root ref"
+                else
+                    raise TdlError.new "#{self} Find multi root refs \n#{rels.join("\n")}\n"
+                end
+            end
+        end
+
+        ## 获取信号的绝对路径
+        def path_refs(nstateq=true,&block)
+            collects = []
+            @belong_to_module.parents_inst_tree do |tree|
+                ll = ["$root"]
+                rt = tree.reverse
+                rt.each_index do |index|
+                    if rt[index].respond_to? :module_name
+                        ll << rt[index].module_name 
+                    else 
+                        ll << rt[index].inst_name
+                    end
+                end
+                if nstateq
+                    ll << nstate
+                else
+                    ll << cstate
+                end
+                new_name = ll.join('.').to_nq
+                if block_given?
+                    if yield(new_name)
+                        collects << new_name
+                    end 
+                else
+                    collects << new_name
+                end
+            end
+            collects
+        end
+    end
+end
+
+# class TdlTestPoint < TdlSpace::TdlTestPoint
+
+# end
+
+module ClassHDL 
+    class StructVar
+        include TdlSpace::ExCreateTP
+
+        ## 获取信号的绝对路径
+        def path_refs(&block)
+            collects = []
+            if @belong_to_module != TopModule.current.techbench
+                @belong_to_module.parents_inst_tree do |tree|
+                    ll = ["$root"]
+                    rt = tree.reverse
+                    rt.each_index do |index|
+                        if rt[index].respond_to? :module_name
+                            ll << rt[index].module_name 
+                        else 
+                            ll << rt[index].inst_name
+                        end
+                    end
+                    ll << self.to_s.to_nq
+                    new_name = ll.join('.').to_nq
+                    if block_given?
+                        if yield(new_name)
+                            collects << new_name
+                        end 
+                    else
+                        collects << new_name
+                    end
+                end
+            else
+                collects = ["$root.#{@belong_to_module.module_name}.#{self.to_s.to_nq}".to_nq]
+            end
+            collects
+        end
+    end
+end