axi_tdl 0.0.15 → 0.0.19

data/lib/axi/data_interface/data_inf_c/data_c_sim_master_model.sv

@@ -0,0 +1,69 @@
+/**********************************************
+_______________________________________ 
+___________    Cook Darwin   __________    
+_______________________________________
+descript:
+author : Cook.Darwin
+Version: VERA.0.0
+created: xxxx.xx.xx
+madified:
+***********************************************/
+`timescale 1ns/1ps
+module data_c_sim_master_model #(
+    parameter   LOOP        = "TRUE",
+    parameter   RAM_DEPTH   = 10000
+)(
+    input               load_trigger,
+    input [31:0]        total_length,
+    input[512*8-1:0]    mem_file,
+    data_inf_c.master   out_inf
+);
+
+
+logic [out_inf.DSIZE+1-1:0] BRAM [RAM_DEPTH-1:0];
+int  total_length_lock;
+initial begin
+    #(5ns);
+    total_length_lock = RAM_DEPTH;
+    $display(" -- Load File %0s",mem_file);
+    $readmemh(mem_file, BRAM, 0, RAM_DEPTH-1);
+end
+
+always@(posedge load_trigger)begin 
+    total_length_lock = total_length;
+    $display(" -- Load File %0s",mem_file);
+    $readmemh(mem_file, BRAM, 0, RAM_DEPTH-1);
+end
+
+int     index;
+logic   disable_coe;
+initial begin
+    index = 0;
+    disable_coe = 1'b0;
+end
+
+
+always@(posedge out_inf.clock) begin 
+    if(~out_inf.rst_n) index     <= 0;
+    else begin 
+        if(out_inf.ready) begin 
+            if(index >= total_length_lock-1)begin 
+                if(LOOP == "TRUE" || LOOP == "ON")begin 
+                    index <= 0;
+                end else begin 
+                    index   <= total_length_lock-1;
+                    disable_coe <= 1'b1;
+                end 
+            end else begin 
+                index <= index + 1;
+            end 
+        end else begin 
+            index <= index;
+        end 
+    end 
+end 
+
+assign out_inf.data     = BRAM[index][out_inf.DSIZE-1:0];
+assign out_inf.valid    = BRAM[index][out_inf.DSIZE] && ~disable_coe; 
+
+endmodule

data/lib/axi/data_interface/data_inf_c/data_c_sim_slaver_model.sv

@@ -0,0 +1,58 @@
+/**********************************************
+_______________________________________ 
+___________    Cook Darwin   __________    
+_______________________________________
+descript:
+author : Cook.Darwin
+Version: VERA.0.0
+created: xxxx.xx.xx
+madified:
+***********************************************/
+`timescale 1ns/1ps
+module data_c_sim_slaver_model #(
+    parameter   RAM_DEPTH   = 10000
+)(
+    input               load_trigger,
+    input [31:0]        total_length,
+    input[512*8-1:0]    mem_file,
+    data_inf_c.slaver   in_inf
+);
+
+int  total_length_lock;
+
+logic [0:0] BRAM [RAM_DEPTH-1:0];
+
+initial begin
+    #(1ns);
+    total_length_lock = RAM_DEPTH;
+    $readmemh(mem_file, BRAM, 0, RAM_DEPTH-1);
+end
+
+always@(posedge load_trigger)begin 
+    total_length_lock   = total_length;
+    $readmemh(mem_file, BRAM, 0, RAM_DEPTH-1);
+end
+
+int  index;
+initial begin
+    index = 0;
+end
+
+always@(posedge out_inf.clock) begin 
+    if(~out_inf.rst_n) index     <= 0;
+    else begin 
+        if(out_inf.ready) begin 
+            if(index >= total_length_lock-1)begin 
+                index <= 0;
+            end else begin 
+                index <= index + 1;
+            end 
+        end else begin 
+            index <= index;
+        end 
+    end 
+end 
+
+assign out_inf.ready    = BRAM[index]; 
+
+endmodule

data/lib/axi/data_interface/data_inf_c/logic_sim_model.sv

@@ -0,0 +1,64 @@
+/**********************************************
+_______________________________________ 
+___________    Cook Darwin   __________    
+_______________________________________
+descript:
+author : Cook.Darwin
+Version: VERA.0.0
+creaded: XXXX.XX.XX
+madified:
+***********************************************/
+`timescale 1ns/1ps
+module logic_sim_model #(
+    parameter   LOOP        = "TRUE",
+    parameter   DSIZE       = 32,
+    parameter   RAM_DEPTH   = 10000
+)(
+    input               next_at_negedge_of,
+    input               next_at_posedge_of,
+    input               load_trigger,
+    input [31:0]        total_length,
+    input[512*8-1:0]    mem_file,
+    output[DSIZE-1:0]   data
+);
+
+
+logic [DSIZE+1-1:0] BRAM [RAM_DEPTH-1:0];
+int  total_length_lock;
+int  index;
+
+initial begin
+    #(1ns);
+    total_length_lock = RAM_DEPTH;
+    $readmemh(mem_file, BRAM, 0, RAM_DEPTH-1);
+end
+
+always@(posedge load_trigger)begin 
+    total_length_lock = total_length;
+    index = 0;
+    $readmemh(mem_file, BRAM, 0, RAM_DEPTH-1);
+end
+
+logic init_lock;
+initial begin
+    index = 0;
+    init_lock = 1'b0;
+    #(100ns);
+    init_lock = 1'b1;
+end
+
+always@(negedge next_at_negedge_of,posedge next_at_posedge_of) begin 
+    if(index >= total_length_lock-1)begin 
+        if(LOOP=="TRUE" || LOOP=="ON")begin 
+            index <= 0;
+        end else begin 
+            index <= total_length_lock-1;
+        end 
+    end else begin 
+        index <= index + init_lock;
+    end 
+end 
+
+assign data     = BRAM[index];
+
+endmodule

data/lib/axi/techbench/tb_axi_stream_split_channel.rb

@@ -0,0 +1,69 @@
+require 'axi_tdl'
+require_sdl 'axi_stream_split_channel.rb'
+
+TdlBuild.tb_axi_stream_split_channel(__dir__) do 
+
+    logic.clock(100)    - 'clock'
+    logic.reset('low')  - 'rst_n'
+
+    clock.to_sim_source
+    rst_n.to_sim_source(200)    # keep 200ns when initial
+
+    axi_stream_inf(clock: clock, reset: rst_n, dsize:8) - 'origin_inf'
+    origin_inf.copy(name: 'first_inf')
+    origin_inf.copy(name: 'end_inf')
+
+    axi_stream_split_channel.axis_split_channel_inst do |h|
+        h.input[16].split_len               logic[16].split_len       # 1:need 1 size ; split len must large than 2
+        h.port.axis.slaver.origin_inf       origin_inf           
+        h.port.axis.master.first_inf        first_inf            
+        h.port.axis.master.end_inf          end_inf          
+    end
+
+    origin_param = {
+        split_len:  [3,4,5,6],
+        length:     [16,32,24,50,12],
+        gap_len:    [3,0,1,0,5],
+        data:       [(0..100)],
+        vld_perc:   [50,100,30,80]
+    }
+
+    split_len.to_sim_source_coe(
+        data: origin_param[:split_len] * ( (origin_param[:length].size/ origin_param[:split_len].size + 1)), 
+        posedge: nil ,
+        negedge: origin_inf.vld_rdy_last
+    )
+
+    origin_inf.to_simple_sim_master_coe(
+        length:     origin_param[:length], 
+        gap_len:    origin_param[:gap_len], 
+        data:       origin_param[:data], 
+        vld_perc:   origin_param[:vld_perc]
+    )
+
+    first_inf.to_simple_sim_slaver([50,100,30])
+    end_inf.to_simple_sim_slaver([100,50,100])
+
+
+    ## 验证输出
+    fcollect = []
+    ecollect = []
+    origin_param[:length].each_index do |index|
+        _data = origin_param[:data][index] || origin_param[:data][0]
+        _data = _data.to_a[0,origin_param[:length][index]]
+
+        insert_seed = origin_param[:split_len][index] || origin_param[:split_len][0]
+
+        # _data.insert(insert_seed,_data[insert_seed])
+
+        fcollect += _data[0,insert_seed]
+        fcollect[fcollect.size-1] = fcollect.last + 256 
+        ecollect += _data[insert_seed, _data.size-insert_seed]
+        ecollect[ecollect.size-1] = ecollect.last + 256 
+    end
+
+
+    first_inf.simple_verify_by_coe(AxiTdl::Verification::CoeArray.new(fcollect).coe)
+    end_inf.simple_verify_by_coe(AxiTdl::Verification::CoeArray.new(ecollect).coe)
+
+end

data/lib/axi/techbench/tb_axi_stream_split_channel.sv

@@ -0,0 +1,149 @@
+/**********************************************
+_______________________________________ 
+___________    Cook Darwin   __________    
+_______________________________________
+descript:
+author : Cook.Darwin
+Version: VERA.0.0
+created: xxxx.xx.xx
+madified:
+***********************************************/
+`timescale 1ns/1ps
+
+module tb_axi_stream_split_channel ();
+//==========================================================================
+//-------- define ----------------------------------------------------------
+logic  clock;
+logic  rst_n;
+logic [16-1:0]  split_len ;
+logic [32-1:0]  first_inf_rdy_percetage_index ;
+logic [32-1:0]  first_inf_rdy_percetage[3-1:0] ;
+logic [32-1:0]  end_inf_rdy_percetage_index ;
+logic [32-1:0]  end_inf_rdy_percetage[3-1:0] ;
+axi_stream_inf #(.DSIZE(8),.USIZE(1)) origin_inf (.aclk(clock),.aresetn(rst_n),.aclken(1'b1)) ;
+axi_stream_inf #(.DSIZE(8),.USIZE(1)) first_inf (.aclk(clock),.aresetn(rst_n),.aclken(1'b1)) ;
+axi_stream_inf #(.DSIZE(8),.USIZE(1)) end_inf (.aclk(clock),.aresetn(rst_n),.aclken(1'b1)) ;
+//==========================================================================
+//-------- instance --------------------------------------------------------
+axi_stream_split_channel axis_split_channel_inst(
+/* input                 */.split_len  (split_len  ),
+/* axi_stream_inf.slaver */.origin_inf (origin_inf ),
+/* axi_stream_inf.master */.first_inf  (first_inf  ),
+/* axi_stream_inf.master */.end_inf    (end_inf    )
+);
+logic_sim_model #(
+    .LOOP      ("TRUE" ),
+    .DSIZE     (16     ),
+    .RAM_DEPTH (8      )
+)split_len_sim_model_inst(
+/* input  */.next_at_negedge_of (origin_inf.axis_tvalid && origin_inf.axis_tready && origin_inf.axis_tlast             ),
+/* input  */.next_at_posedge_of (1'b0                                                                                  ),
+/* input  */.load_trigger       (1'b0                                                                                  ),
+/* input  */.total_length       (8                                                                                     ),
+/* input  */.mem_file           ("/var/lib/gems/2.5.0/gems/axi_tdl-0.0.10/lib/tdl/auto_script/tmp/split_len_R1712.coe" ),
+/* output */.data               (split_len                                                                             )
+);
+axis_sim_master_model #(
+    .LOOP      ("TRUE" ),
+    .RAM_DEPTH (246    )
+)sim_model_inst_origin_inf(
+/* input                 */.load_trigger (1'b0                                                                                  ),
+/* input                 */.total_length (246                                                                                   ),
+/* input                 */.mem_file     ("/var/lib/gems/2.5.0/gems/axi_tdl-0.0.10/lib/tdl/auto_script/tmp/origin_inf_R560.coe" ),
+/* axi_stream_inf.master */.out_inf      (origin_inf                                                                            )
+);
+axis_sim_verify_by_coe #(
+    .RAM_DEPTH   (21    ),
+    .VERIFY_KEEP ("OFF" ),
+    .VERIFY_USER ("OFF" )
+)axis_sim_verify_by_coe_inst_first_inf(
+/* input                 */.load_trigger (1'b0                                                                                  ),
+/* input                 */.total_length (21                                                                                    ),
+/* input                 */.mem_file     ("/var/lib/gems/2.5.0/gems/axi_tdl-0.0.10/lib/tdl/auto_script/tmp/first_inf_R1297.coe" ),
+/* axi_stream_inf.mirror */.mirror_inf   (first_inf                                                                             )
+);
+axis_sim_verify_by_coe #(
+    .RAM_DEPTH   (113   ),
+    .VERIFY_KEEP ("OFF" ),
+    .VERIFY_USER ("OFF" )
+)axis_sim_verify_by_coe_inst_end_inf(
+/* input                 */.load_trigger (1'b0                                                                                ),
+/* input                 */.total_length (113                                                                                 ),
+/* input                 */.mem_file     ("/var/lib/gems/2.5.0/gems/axi_tdl-0.0.10/lib/tdl/auto_script/tmp/end_inf_R1464.coe" ),
+/* axi_stream_inf.mirror */.mirror_inf   (end_inf                                                                             )
+);
+//==========================================================================
+//-------- expression ------------------------------------------------------
+initial begin
+     clock = 1'b0;
+     #(100ns);
+     forever begin #(5.0ns);clock = ~clock;end;
+end
+
+initial begin
+     rst_n = 1'b0;
+     #(200ns);
+     rst_n = ~rst_n;
+end
+
+initial begin
+     first_inf_rdy_percetage_index = 0;
+     first_inf_rdy_percetage[0] = 50;
+     first_inf_rdy_percetage[1] = 100;
+     first_inf_rdy_percetage[2] = 30;
+end
+
+always@(posedge clock) begin 
+    if(first_inf.axis_tvalid && first_inf.axis_tready && first_inf.axis_tlast)begin
+        if( first_inf_rdy_percetage_index>=( 3-1))begin
+             first_inf_rdy_percetage_index <= 0;
+        end
+        else begin
+             first_inf_rdy_percetage_index <= ( first_inf_rdy_percetage_index+1'b1);
+        end
+    end
+    else begin
+         first_inf_rdy_percetage_index <= first_inf_rdy_percetage_index;
+    end
+end
+
+always@(posedge clock) begin 
+    if(~rst_n)begin
+         first_inf.axis_tready <= 1'b0;
+    end
+    else begin
+         first_inf.axis_tready <= ($urandom_range(0,99) <= first_inf_rdy_percetage[first_inf_rdy_percetage_index]);
+    end
+end
+
+initial begin
+     end_inf_rdy_percetage_index = 0;
+     end_inf_rdy_percetage[0] = 100;
+     end_inf_rdy_percetage[1] = 50;
+     end_inf_rdy_percetage[2] = 100;
+end
+
+always@(posedge clock) begin 
+    if(end_inf.axis_tvalid && end_inf.axis_tready && end_inf.axis_tlast)begin
+        if( end_inf_rdy_percetage_index>=( 3-1))begin
+             end_inf_rdy_percetage_index <= 0;
+        end
+        else begin
+             end_inf_rdy_percetage_index <= ( end_inf_rdy_percetage_index+1'b1);
+        end
+    end
+    else begin
+         end_inf_rdy_percetage_index <= end_inf_rdy_percetage_index;
+    end
+end
+
+always@(posedge clock) begin 
+    if(~rst_n)begin
+         end_inf.axis_tready <= 1'b0;
+    end
+    else begin
+         end_inf.axis_tready <= ($urandom_range(0,99) <= end_inf_rdy_percetage[end_inf_rdy_percetage_index]);
+    end
+end
+
+endmodule

data/lib/axi/techbench/tb_axis_split_channel_verb.rb

@@ -0,0 +1,69 @@
+require 'axi_tdl'
+require_sdl 'axis_split_channel_verb.rb'
+
+TdlBuild.tb_axis_split_channel_verb(__dir__) do 
+
+    logic.clock(100)    - 'clock'
+    logic.reset('low')  - 'rst_n'
+
+    clock.to_sim_source
+    rst_n.to_sim_source(200)    # keep 200ns when initial
+
+    axi_stream_inf(clock: clock, reset: rst_n, dsize:8) - 'origin_inf'
+    origin_inf.copy(name: 'first_inf')
+    origin_inf.copy(name: 'end_inf')
+
+    axis_split_channel_verb.axis_split_channel_verb_inst do |h|
+        h.input[16].split_len               logic[16].split_len       # 1:need 1 size ; split len must large than 2
+        h.port.axis.slaver.origin_inf       origin_inf           
+        h.port.axis.master.first_inf        first_inf            
+        h.port.axis.master.end_inf          end_inf          
+    end
+
+    origin_param = {
+        split_len:  [3,4,5,6],
+        length:     [16,32,24,50,12],
+        gap_len:    [3,0,1,0,5],
+        data:       [(0..100)],
+        vld_perc:   [50,100,30,80]
+    }
+
+    split_len.to_sim_source_coe(
+        data: origin_param[:split_len], 
+        posedge: nil ,
+        negedge: origin_inf.vld_rdy_last
+    )
+
+    origin_inf.to_simple_sim_master_coe(
+        length:     origin_param[:length], 
+        gap_len:    origin_param[:gap_len], 
+        data:       origin_param[:data], 
+        vld_perc:   origin_param[:vld_perc]
+    )
+
+    first_inf.to_simple_sim_slaver([100,50])
+    end_inf.to_simple_sim_slaver(50)
+
+
+    ## 验证输出
+    fcollect = []
+    ecollect = []
+    origin_param[:length].each_index do |index|
+        _data = origin_param[:data][index] || origin_param[:data][0]
+        _data = _data.to_a[0,origin_param[:length][index]]
+
+        insert_seed = origin_param[:split_len][index] || origin_param[:split_len][0]
+
+        # _data.insert(insert_seed,_data[insert_seed])
+
+        fcollect += _data[0,insert_seed]
+        fcollect[fcollect.size-1] = fcollect.last + 256 
+        ecollect += _data[insert_seed-1, _data.size-insert_seed+1]
+        ecollect[ecollect.size-1] = ecollect.last + 256 
+    end
+
+
+    first_inf.simple_verify_by_coe(AxiTdl::Verification::CoeArray.new(fcollect).coe)
+    end_inf.simple_verify_by_coe(AxiTdl::Verification::CoeArray.new(ecollect).coe)
+
+end