axi_tdl 0.0.15 → 0.0.19
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- checksums.yaml +4 -4
- data/.github/workflows/gem-push.yml +4 -2
- data/axi_tdl.gemspec +0 -1
- data/lib/axi/AXI4/axi4_direct_B1.sv +23 -23
- data/lib/axi/AXI4/axi4_dpram_cache.sv +33 -33
- data/lib/axi/AXI4/axis_to_axi4_wr.rb +1 -0
- data/lib/axi/AXI4/axis_to_axi4_wr.sv +20 -20
- data/lib/axi/AXI4/packet_partition/axi4_partition_rd_verb.sv +32 -32
- data/lib/axi/AXI4/packet_partition/data_inf_partition.rb +2 -0
- data/lib/axi/AXI4/packet_partition/data_inf_partition.sv +71 -71
- data/lib/axi/AXI4/wide_axis_to_axi4_wr.rb +2 -1
- data/lib/axi/AXI4/wide_axis_to_axi4_wr.sv +23 -23
- data/lib/axi/AXI_stream/axi_stream_split_channel.rb +7 -1
- data/lib/axi/AXI_stream/axis_head_cut_verb.sv +6 -2
- data/lib/axi/AXI_stream/axis_insert_copy.rb +18 -4
- data/lib/axi/AXI_stream/axis_sim_master_model.rb +28 -0
- data/lib/axi/AXI_stream/axis_sim_slaver_model.rb +26 -0
- data/lib/axi/AXI_stream/axis_sim_verify_by_coe.sv +101 -0
- data/lib/axi/AXI_stream/axis_split_channel_verb.rb +2 -0
- data/lib/axi/common/common_ram_sim_wrapper.sv +9 -9
- data/lib/axi/common/common_ram_wrapper.sv +12 -12
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.sv +26 -26
- data/lib/axi/data_interface/data_inf_c/data_c_sim_master_model.sv +69 -0
- data/lib/axi/data_interface/data_inf_c/data_c_sim_slaver_model.sv +58 -0
- data/lib/axi/data_interface/data_inf_c/logic_sim_model.sv +64 -0
- data/lib/axi/techbench/tb_axi_stream_split_channel.rb +69 -0
- data/lib/axi/techbench/tb_axi_stream_split_channel.sv +149 -0
- data/lib/axi/techbench/tb_axis_split_channel_verb.rb +69 -0
- data/lib/axi/techbench/tb_axis_split_channel_verb.sv +125 -0
- data/lib/axi_tdl.rb +1 -0
- data/lib/axi_tdl/version.rb +1 -1
- data/lib/tdl/auto_script/autogensdl.rb +16 -5
- data/lib/tdl/axi4/axi4_interconnect_verb.rb +4 -2
- data/lib/tdl/basefunc.rb +1 -0
- data/lib/tdl/class_hdl/hdl_always_comb.rb +4 -3
- data/lib/tdl/class_hdl/hdl_always_ff.rb +48 -7
- data/lib/tdl/class_hdl/hdl_assign.rb +5 -3
- data/lib/tdl/class_hdl/hdl_block_ifelse.rb +11 -9
- data/lib/tdl/class_hdl/hdl_foreach.rb +2 -2
- data/lib/tdl/class_hdl/hdl_function.rb +4 -2
- data/lib/tdl/class_hdl/hdl_generate.rb +5 -4
- data/lib/tdl/class_hdl/hdl_initial.rb +11 -10
- data/lib/tdl/class_hdl/hdl_module_def.rb +18 -1
- data/lib/tdl/class_hdl/hdl_redefine_opertor.rb +35 -14
- data/lib/tdl/class_hdl/hdl_struct.rb +1 -1
- data/lib/tdl/class_hdl/hdl_verify.rb +1 -1
- data/lib/tdl/elements/originclass.rb +6 -1
- data/lib/tdl/elements/parameter.rb +1 -1
- data/lib/tdl/examples/10_random/exp_random.sv +3 -3
- data/lib/tdl/examples/11_test_unit/dve.tcl +155 -2
- data/lib/tdl/examples/11_test_unit/exp_test_unit.rb +9 -8
- data/lib/tdl/examples/11_test_unit/exp_test_unit.sv +1 -1
- data/lib/tdl/examples/11_test_unit/modules/sub_md0.rb +6 -3
- data/lib/tdl/examples/11_test_unit/modules/sub_md0.sv +5 -5
- data/lib/tdl/examples/11_test_unit/modules/sub_md1.rb +9 -4
- data/lib/tdl/examples/11_test_unit/modules/sub_md1.sv +5 -5
- data/lib/tdl/examples/11_test_unit/tb_exp_test_unit.sv +1 -2
- data/lib/tdl/examples/11_test_unit/tu0.sv +9 -9
- data/lib/tdl/examples/11_test_unit/tu1.sv +1 -1
- data/lib/tdl/examples/1_define_module/exmple_md.sv +12 -12
- data/lib/tdl/examples/2_hdl_class/tmp/always_comb_test.sv +60 -60
- data/lib/tdl/examples/2_hdl_class/tmp/always_ff_test.sv +2 -2
- data/lib/tdl/examples/2_hdl_class/tmp/case_test.sv +17 -17
- data/lib/tdl/examples/2_hdl_class/tmp/head_pkg_module.sv +9 -9
- data/lib/tdl/examples/2_hdl_class/tmp/simple_assign_test.sv +1 -1
- data/lib/tdl/examples/2_hdl_class/tmp/state_case_test.sv +10 -10
- data/lib/tdl/examples/2_hdl_class/tmp/test_foreach.sv +3 -3
- data/lib/tdl/examples/2_hdl_class/tmp/test_function.sv +7 -7
- data/lib/tdl/examples/2_hdl_class/tmp/test_initial_assert.sv +3 -3
- data/lib/tdl/examples/2_hdl_class/tmp/test_module.sv +2 -2
- data/lib/tdl/examples/2_hdl_class/tmp/test_module_var.sv +2 -2
- data/lib/tdl/examples/2_hdl_class/tmp/test_package.sv +4 -5
- data/lib/tdl/examples/2_hdl_class/tmp/test_package2.sv +4 -4
- data/lib/tdl/examples/2_hdl_class/tmp/test_struct_function.sv +2 -2
- data/lib/tdl/examples/2_hdl_class/tmp/test_vcs_string.sv +1 -1
- data/lib/tdl/examples/2_hdl_class/tmp/text_generate.sv +7 -7
- data/lib/tdl/examples/4_generate/test_generate.sv +11 -11
- data/lib/tdl/examples/5_logic_combin/test_logic_combin.sv +3 -3
- data/lib/tdl/examples/7_module_with_package/body_package.sv +3 -4
- data/lib/tdl/examples/7_module_with_package/example_pkg.sv +4 -4
- data/lib/tdl/examples/7_module_with_package/head_package.sv +3 -4
- data/lib/tdl/examples/8_top_module/tb_test_top.sv +1 -1
- data/lib/tdl/examples/9_itegration/tb_test_tttop.sv +2 -4
- data/lib/tdl/examples/9_itegration/test_tttop.sv +3 -3
- data/lib/tdl/exlib/axis_eth_ex.rb +95 -0
- data/lib/tdl/exlib/axis_verify.rb +264 -0
- data/lib/tdl/exlib/clock_reset_verify.rb +29 -0
- data/lib/tdl/exlib/dve_tcl.rb +30 -11
- data/lib/tdl/exlib/itegration.rb +15 -3
- data/lib/tdl/exlib/logic_verify.rb +88 -0
- data/lib/tdl/exlib/test_point.rb +96 -94
- data/lib/tdl/exlib/test_point.rb.bak +293 -0
- data/lib/tdl/rebuild_ele/ele_base.rb +1 -1
- data/lib/tdl/sdlmodule/sdlmodlule_path_db.rb +34 -0
- data/lib/tdl/sdlmodule/sdlmodule.rb +18 -14
- data/lib/tdl/sdlmodule/sdlmodule_draw.rb +81 -16
- data/lib/tdl/sdlmodule/test_unit_module.rb +272 -33
- data/lib/tdl/sdlmodule/test_unit_module.rb.bak +143 -0
- data/lib/tdl/sdlmodule/top_module.rb +53 -48
- data/lib/tdl/sdlmodule/top_module.rb.bak +547 -0
- data/lib/tdl/tdl.rb +18 -3
- metadata +21 -111
- data/lib/axi/AXI_stream/axi_stream_split_channel.sv +0 -149
- data/lib/axi/AXI_stream/axis_head_cut_verc.sv +0 -242
- data/lib/axi/AXI_stream/axis_insert_copy.sv +0 -66
- data/lib/axi/AXI_stream/axis_pipe_sync_seam.sv +0 -48
- data/lib/axi/AXI_stream/axis_rom_contect_sim.sv +0 -113
- data/lib/axi/AXI_stream/axis_split_channel_verb.sv +0 -62
data/lib/tdl/tdl.rb
CHANGED
@@ -81,6 +81,9 @@ require_relative "./rebuild_ele/data_inf_c.rb"
|
|
81
81
|
require_relative "./rebuild_ele/axi_lite.rb"
|
82
82
|
require_relative "./rebuild_ele/cm_ram_inf_define.rb"
|
83
83
|
|
84
|
+
## 添加axis 流slice功能
|
85
|
+
require_relative "./exlib/axis_eth_ex.rb"
|
86
|
+
|
84
87
|
require_relative "./bfm/axi_stream/axi_stream_bfm.rb"
|
85
88
|
|
86
89
|
require_relative "./exlib/constraints"
|
@@ -118,6 +121,12 @@ require_relative "./sdlmodule/test_unit_module.rb"
|
|
118
121
|
## 添加 DVE TCL 支持
|
119
122
|
require_relative "./exlib/dve_tcl.rb"
|
120
123
|
|
124
|
+
## 添加 verify
|
125
|
+
require_relative "./exlib/axis_verify.rb"
|
126
|
+
require_relative "./exlib/clock_reset_verify.rb"
|
127
|
+
require_relative "./exlib/logic_verify.rb"
|
128
|
+
|
129
|
+
|
121
130
|
## --- INIT BLOCK Methods -----
|
122
131
|
# AutoGenSdl.add_inf_parse TrackInf.method(:parse_ports)
|
123
132
|
# SdlInst.add_inst_t0_method TrackInf.method(:sdlinst_t0)
|
@@ -175,6 +184,7 @@ class Tdl # add file paths
|
|
175
184
|
else
|
176
185
|
@@all_file_paths[a] = b
|
177
186
|
end
|
187
|
+
|
178
188
|
end
|
179
189
|
|
180
190
|
def self.all_file_paths
|
@@ -250,12 +260,14 @@ class Tdl
|
|
250
260
|
self.log_array("LOG FOR GEN SDLMOUDLE",@@build_sdlmodule_collect)
|
251
261
|
self.log_array("LOG OF WARNING",@@warning_collect)
|
252
262
|
# puts(page(tag: "SUMMARY" ,body: "RUN @ TIME : #{Time.now}"))
|
253
|
-
puts(pagination("TEST POINT"))
|
254
|
-
puts TdlTestPoint.echo_list
|
263
|
+
puts(pagination("TEST POINT")) if TopModule.current
|
264
|
+
# puts TdlTestPoint.echo_list
|
255
265
|
# puts(pagination("SIM TEST"))
|
256
266
|
# puts TdlSimTest::TdlBaseTestUnit.echo_prj_test_list
|
267
|
+
puts SdlModule.echo_tracked_by_dve if TopModule.current && TopModule.sim
|
257
268
|
puts(pagination("TEST UNIT")) if TopModule.current
|
258
|
-
puts TopModule.current.test_unit.echo_units if TopModule.current
|
269
|
+
# puts TopModule.current.test_unit.echo_units if TopModule.current
|
270
|
+
puts TestUnitModule.echo_be_instanced_by_sim if TopModule.current
|
259
271
|
puts(pagination("SUMMARY"))
|
260
272
|
puts "#{TopModule.sim ? 'SIM' : 'SYNTH'} RUN SPEND #{Time.now - $__start_time__} sec @ TIME : #{Time.now}"
|
261
273
|
|
@@ -266,6 +278,9 @@ class Tdl
|
|
266
278
|
# end
|
267
279
|
# end
|
268
280
|
## ===========
|
281
|
+
# File.open("/home/myw357/work/FPGA/mammo_tcp_20210315/tmp.tcl", "w") do |f|
|
282
|
+
# f.puts SdlModule.call_module('test_mac_1g_verb').gen_dev_wave_tcl
|
283
|
+
# end
|
269
284
|
end
|
270
285
|
|
271
286
|
end
|
metadata
CHANGED
@@ -1,14 +1,14 @@
|
|
1
1
|
--- !ruby/object:Gem::Specification
|
2
2
|
name: axi_tdl
|
3
3
|
version: !ruby/object:Gem::Version
|
4
|
-
version: 0.0.
|
4
|
+
version: 0.0.19
|
5
5
|
platform: ruby
|
6
6
|
authors:
|
7
7
|
- Cook.Darwin
|
8
8
|
autorequire:
|
9
9
|
bindir: exe
|
10
10
|
cert_chain: []
|
11
|
-
date: 2021-03-
|
11
|
+
date: 2021-03-20 00:00:00.000000000 Z
|
12
12
|
dependencies:
|
13
13
|
- !ruby/object:Gem::Dependency
|
14
14
|
name: rake
|
@@ -209,7 +209,6 @@ files:
|
|
209
209
|
- lib/axi/AXI_stream/axi_stream_partition_A1.sv
|
210
210
|
- lib/axi/AXI_stream/axi_stream_planer.sv
|
211
211
|
- lib/axi/AXI_stream/axi_stream_split_channel.rb
|
212
|
-
- lib/axi/AXI_stream/axi_stream_split_channel.sv
|
213
212
|
- lib/axi/AXI_stream/axi_streams_combin.sv
|
214
213
|
- lib/axi/AXI_stream/axi_streams_combin_A1.sv
|
215
214
|
- lib/axi/AXI_stream/axi_streams_scaler.sv
|
@@ -231,10 +230,8 @@ files:
|
|
231
230
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- lib/axi/AXI_stream/axis_head_cut.sv
|
232
231
|
- lib/axi/AXI_stream/axis_head_cut_verb.sv
|
233
232
|
- lib/axi/AXI_stream/axis_head_cut_verc.rb
|
234
|
-
- lib/axi/AXI_stream/axis_head_cut_verc.sv
|
235
233
|
- lib/axi/AXI_stream/axis_inct_s2m_with_flag.sv
|
236
234
|
- lib/axi/AXI_stream/axis_insert_copy.rb
|
237
|
-
- lib/axi/AXI_stream/axis_insert_copy.sv
|
238
235
|
- lib/axi/AXI_stream/axis_intc_M2S_with_addr_inf.sv
|
239
236
|
- lib/axi/AXI_stream/axis_intc_S2M_with_addr_inf.sv
|
240
237
|
- lib/axi/AXI_stream/axis_interconnect_S2M_pipe.sv
|
@@ -250,18 +247,18 @@ files:
|
|
250
247
|
- lib/axi/AXI_stream/axis_mirrors.sv
|
251
248
|
- lib/axi/AXI_stream/axis_orthogonal.sv
|
252
249
|
- lib/axi/AXI_stream/axis_pipe_sync_seam.rb
|
253
|
-
- lib/axi/AXI_stream/axis_pipe_sync_seam.sv
|
254
250
|
- lib/axi/AXI_stream/axis_ram_buffer.sv
|
255
251
|
- lib/axi/AXI_stream/axis_rom_contect.rb
|
256
252
|
- lib/axi/AXI_stream/axis_rom_contect.sv
|
257
253
|
- lib/axi/AXI_stream/axis_rom_contect_sim.rb
|
258
|
-
- lib/axi/AXI_stream/
|
254
|
+
- lib/axi/AXI_stream/axis_sim_master_model.rb
|
255
|
+
- lib/axi/AXI_stream/axis_sim_slaver_model.rb
|
256
|
+
- lib/axi/AXI_stream/axis_sim_verify_by_coe.sv
|
259
257
|
- lib/axi/AXI_stream/axis_slaver_empty.sv
|
260
258
|
- lib/axi/AXI_stream/axis_slaver_pipe.sv
|
261
259
|
- lib/axi/AXI_stream/axis_slaver_pipe_A1.sv
|
262
260
|
- lib/axi/AXI_stream/axis_slaver_vector_empty.sv
|
263
261
|
- lib/axi/AXI_stream/axis_split_channel_verb.rb
|
264
|
-
- lib/axi/AXI_stream/axis_split_channel_verb.sv
|
265
262
|
- lib/axi/AXI_stream/axis_to_axi4_or_lite.rb
|
266
263
|
- lib/axi/AXI_stream/axis_to_axi4_or_lite.sv
|
267
264
|
- lib/axi/AXI_stream/axis_to_data_inf.sv
|
@@ -397,6 +394,8 @@ files:
|
|
397
394
|
- lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.sv
|
398
395
|
- lib/axi/data_interface/data_inf_c/data_c_scaler.sv
|
399
396
|
- lib/axi/data_interface/data_inf_c/data_c_scaler_A1.sv
|
397
|
+
- lib/axi/data_interface/data_inf_c/data_c_sim_master_model.sv
|
398
|
+
- lib/axi/data_interface/data_inf_c/data_c_sim_slaver_model.sv
|
400
399
|
- lib/axi/data_interface/data_inf_c/data_c_tmp_cache.sv
|
401
400
|
- lib/axi/data_interface/data_inf_c/data_condition_mirror.sv
|
402
401
|
- lib/axi/data_interface/data_inf_c/data_condition_valve.sv
|
@@ -415,6 +414,7 @@ files:
|
|
415
414
|
- lib/axi/data_interface/data_inf_c/data_mirrors_verb.sv.bak
|
416
415
|
- lib/axi/data_interface/data_inf_c/data_uncompress.sv
|
417
416
|
- lib/axi/data_interface/data_inf_c/data_valve.sv
|
417
|
+
- lib/axi/data_interface/data_inf_c/logic_sim_model.sv
|
418
418
|
- lib/axi/data_interface/data_inf_c/next_prio.sv
|
419
419
|
- lib/axi/data_interface/data_inf_c/trigger_data_inf_c.sv
|
420
420
|
- lib/axi/data_interface/data_inf_c/trigger_data_inf_c_A1.sv
|
@@ -514,6 +514,10 @@ files:
|
|
514
514
|
- lib/axi/platform_ip/xilinx_fifo_verb.sv
|
515
515
|
- lib/axi/platform_ip/xilinx_fifo_verc.sv
|
516
516
|
- lib/axi/platform_ip/xilinx_stream_packet_fifo_ip.sv
|
517
|
+
- lib/axi/techbench/tb_axi_stream_split_channel.rb
|
518
|
+
- lib/axi/techbench/tb_axi_stream_split_channel.sv
|
519
|
+
- lib/axi/techbench/tb_axis_split_channel_verb.rb
|
520
|
+
- lib/axi/techbench/tb_axis_split_channel_verb.sv
|
517
521
|
- lib/axi/top/axi4_data_convert_2_20_tb.sv
|
518
522
|
- lib/axi/top/axi4_data_convert_5_24_tb.sv
|
519
523
|
- lib/axi/top/axi4_interconnnect_2_24_tb.sv
|
@@ -818,108 +822,6 @@ files:
|
|
818
822
|
- lib/tdl/auto_script/import_sdl.rb
|
819
823
|
- lib/tdl/auto_script/test_autogensdl.rb
|
820
824
|
- lib/tdl/auto_script/tmp.rb
|
821
|
-
- lib/tdl/auto_script/tmp/TPU_reprogram_wrapper_verb_sdl.rb
|
822
|
-
- lib/tdl/auto_script/tmp/acce_iic_bus_upgrade_sdl.rb
|
823
|
-
- lib/tdl/auto_script/tmp/arp_tpu_wrapper_sdl.rb
|
824
|
-
- lib/tdl/auto_script/tmp/axi4_direct_verc_sdl.rb
|
825
|
-
- lib/tdl/auto_script/tmp/axi4_rd_mix_interconnect_M2S_A2_sdl.rb
|
826
|
-
- lib/tdl/auto_script/tmp/axi4_wr_auxiliary_gen_without_resp_sdl.rb
|
827
|
-
- lib/tdl/auto_script/tmp/axi4_wr_pipe_sdl.rb
|
828
|
-
- lib/tdl/auto_script/tmp/axi_stream_cache_35bit_sdl.rb
|
829
|
-
- lib/tdl/auto_script/tmp/axi_stream_cache_A1_sdl.rb
|
830
|
-
- lib/tdl/auto_script/tmp/axi_stream_cache_sdl.rb
|
831
|
-
- lib/tdl/auto_script/tmp/axi_stream_interconnect_M2S_A1_sdl.rb
|
832
|
-
- lib/tdl/auto_script/tmp/axi_stream_interconnect_M2S_bind_tuser_sdl.rb
|
833
|
-
- lib/tdl/auto_script/tmp/axi_stream_interconnect_S2M_sdl.rb
|
834
|
-
- lib/tdl/auto_script/tmp/axi_stream_latency_sdl.rb
|
835
|
-
- lib/tdl/auto_script/tmp/axi_stream_long_fifo_sdl.rb
|
836
|
-
- lib/tdl/auto_script/tmp/axi_stream_long_fifo_verb_sdl.rb
|
837
|
-
- lib/tdl/auto_script/tmp/axi_stream_packet_fifo_sdl.rb
|
838
|
-
- lib/tdl/auto_script/tmp/axi_stream_packet_long_fifo_sdl.rb
|
839
|
-
- lib/tdl/auto_script/tmp/axi_stream_planer_sdl.rb
|
840
|
-
- lib/tdl/auto_script/tmp/axi_streams_scaler_A1_sdl.rb
|
841
|
-
- lib/tdl/auto_script/tmp/axis_append_A1_sdl.rb
|
842
|
-
- lib/tdl/auto_script/tmp/axis_connect_pipe_right_shift_sdl.rb
|
843
|
-
- lib/tdl/auto_script/tmp/axis_connect_pipe_right_shift_verb_sdl.rb
|
844
|
-
- lib/tdl/auto_script/tmp/axis_connect_pipe_sdl.rb
|
845
|
-
- lib/tdl/auto_script/tmp/axis_connect_pipe_with_info_sdl.rb
|
846
|
-
- lib/tdl/auto_script/tmp/axis_direct_sdl.rb
|
847
|
-
- lib/tdl/auto_script/tmp/axis_head_cut_sdl.rb
|
848
|
-
- lib/tdl/auto_script/tmp/axis_head_cut_verb_sdl.rb
|
849
|
-
- lib/tdl/auto_script/tmp/axis_intc_S2M_with_addr_inf_sdl.rb
|
850
|
-
- lib/tdl/auto_script/tmp/axis_length_cut_sdl.rb
|
851
|
-
- lib/tdl/auto_script/tmp/axis_length_split_with_addr_sdl.rb
|
852
|
-
- lib/tdl/auto_script/tmp/axis_length_split_with_user_sdl.rb
|
853
|
-
- lib/tdl/auto_script/tmp/axis_master_empty_sdl.rb
|
854
|
-
- lib/tdl/auto_script/tmp/axis_mirror_to_master_sdl.rb
|
855
|
-
- lib/tdl/auto_script/tmp/axis_pkt_fifo_filter_keep_A1_sdl.rb
|
856
|
-
- lib/tdl/auto_script/tmp/axis_pkt_fifo_filter_keep_sdl.rb
|
857
|
-
- lib/tdl/auto_script/tmp/axis_slaver_empty_sdl.rb
|
858
|
-
- lib/tdl/auto_script/tmp/axis_uncompress_A1_sdl.rb
|
859
|
-
- lib/tdl/auto_script/tmp/axis_valve_sdl.rb
|
860
|
-
- lib/tdl/auto_script/tmp/axis_valve_with_pipe_sdl.rb
|
861
|
-
- lib/tdl/auto_script/tmp/axis_vector_slaver_empty_sdl.rb
|
862
|
-
- lib/tdl/auto_script/tmp/axis_width_combin_A1_sdl.rb
|
863
|
-
- lib/tdl/auto_script/tmp/axis_width_convert_sdl.rb
|
864
|
-
- lib/tdl/auto_script/tmp/axis_width_destruct_sdl.rb
|
865
|
-
- lib/tdl/auto_script/tmp/bits_decode_nc_verb_sdl.rb
|
866
|
-
- lib/tdl/auto_script/tmp/bits_decode_verb_sdl.rb
|
867
|
-
- lib/tdl/auto_script/tmp/clock_rst_verb_sdl.rb
|
868
|
-
- lib/tdl/auto_script/tmp/clock_rst_verc_sdl.rb
|
869
|
-
- lib/tdl/auto_script/tmp/common_fifo_sdl.rb
|
870
|
-
- lib/tdl/auto_script/tmp/data_c_cache_sdl.rb
|
871
|
-
- lib/tdl/auto_script/tmp/data_c_pipe_force_vld_bind_data_sdl.rb
|
872
|
-
- lib/tdl/auto_script/tmp/data_c_pipe_sync_sdl.rb
|
873
|
-
- lib/tdl/auto_script/tmp/data_inf_c_intc_S2M_sdl.rb
|
874
|
-
- lib/tdl/auto_script/tmp/data_inf_c_planer_A1_sdl.rb
|
875
|
-
- lib/tdl/auto_script/tmp/data_mirrors_sdl.rb
|
876
|
-
- lib/tdl/auto_script/tmp/data_valve_sdl.rb
|
877
|
-
- lib/tdl/auto_script/tmp/ethernet_wrapper_sdl.rb
|
878
|
-
- lib/tdl/auto_script/tmp/full_axi4_to_axis_partition_wr_rd_sdl.rb
|
879
|
-
- lib/tdl/auto_script/tmp/full_axi4_to_axis_sdl.rb
|
880
|
-
- lib/tdl/auto_script/tmp/gen_big_field_table_sdl.rb
|
881
|
-
- lib/tdl/auto_script/tmp/gen_common_frame_table_sdl.rb
|
882
|
-
- lib/tdl/auto_script/tmp/general_tap_ack_A3_sdl.rb
|
883
|
-
- lib/tdl/auto_script/tmp/general_tap_ack_sdl.rb
|
884
|
-
- lib/tdl/auto_script/tmp/general_tap_no_ack_sdl.rb
|
885
|
-
- lib/tdl/auto_script/tmp/gvi_k7_ddr3_ip_wrapper_sdl.rb
|
886
|
-
- lib/tdl/auto_script/tmp/hdl_test_sdl.rb
|
887
|
-
- lib/tdl/auto_script/tmp/independent_clock_fifo_sdl.rb
|
888
|
-
- lib/tdl/auto_script/tmp/inf_time_delay_ctrl_verb_sdl.rb
|
889
|
-
- lib/tdl/auto_script/tmp/init_mac_sdl.rb
|
890
|
-
- lib/tdl/auto_script/tmp/ip_check_sum_sdl.rb
|
891
|
-
- lib/tdl/auto_script/tmp/k7_ethernet_10g_api_mask_shift_sdl.rb
|
892
|
-
- lib/tdl/auto_script/tmp/k7_ethernet_10g_api_sdl.rb
|
893
|
-
- lib/tdl/auto_script/tmp/mac_to_file_64b_sdl.rb
|
894
|
-
- lib/tdl/auto_script/tmp/mac_to_file_sdl.rb
|
895
|
-
- lib/tdl/auto_script/tmp/mdio_model_sdl.rb
|
896
|
-
- lib/tdl/auto_script/tmp/odata_pool_axi4_A2_sdl.rb
|
897
|
-
- lib/tdl/auto_script/tmp/odata_pool_axi4_A3_sdl.rb
|
898
|
-
- lib/tdl/auto_script/tmp/pack_ip_mac_B1_sdl.rb
|
899
|
-
- lib/tdl/auto_script/tmp/pack_ip_mac_verb_sdl.rb
|
900
|
-
- lib/tdl/auto_script/tmp/parse_big_field_table_A2_sdl.rb
|
901
|
-
- lib/tdl/auto_script/tmp/parse_big_field_table_sdl.rb
|
902
|
-
- lib/tdl/auto_script/tmp/parse_common_frame_table_A1_sdl.rb
|
903
|
-
- lib/tdl/auto_script/tmp/sensor_array_ddr_lvds_wrapper_sdl.rb
|
904
|
-
- lib/tdl/auto_script/tmp/sim_arp_tpu_sdl.rb
|
905
|
-
- lib/tdl/auto_script/tmp/sim_tpu_update_file_sdl.rb
|
906
|
-
- lib/tdl/auto_script/tmp/tcp_check_sum_sdl.rb
|
907
|
-
- lib/tdl/auto_script/tmp/tcp_option_split_sdl.rb
|
908
|
-
- lib/tdl/auto_script/tmp/time_step_module_A1_sdl.rb
|
909
|
-
- lib/tdl/auto_script/tmp/tpu_simple_boot_sdl.rb
|
910
|
-
- lib/tdl/auto_script/tmp/trigger_data_inf_c_sdl.rb
|
911
|
-
- lib/tdl/auto_script/tmp/udp_check_sum_sdl.rb
|
912
|
-
- lib/tdl/auto_script/tmp/udp_ctrl_set_A1_sdl.rb
|
913
|
-
- lib/tdl/auto_script/tmp/udp_fpga_ports_route_sdl.rb
|
914
|
-
- lib/tdl/auto_script/tmp/udp_socket_ddr_pump_A3_sdl.rb
|
915
|
-
- lib/tdl/auto_script/tmp/udp_socket_ddr_pump_verb_sdl.rb
|
916
|
-
- lib/tdl/auto_script/tmp/unpack_mac_ip_udp_D1_sdl.rb
|
917
|
-
- lib/tdl/auto_script/tmp/unpack_mac_ip_udp_tcp_sdl.rb
|
918
|
-
- lib/tdl/auto_script/tmp/unpack_mac_ip_udp_verd_sdl.rb
|
919
|
-
- lib/tdl/auto_script/tmp/wide_axis_to_axi4_wr_sdl.rb
|
920
|
-
- lib/tdl/auto_script/tmp/width_convert_verb_sdl.rb
|
921
|
-
- lib/tdl/auto_script/tmp/xilinx_hdl_dpram_sdl.rb
|
922
|
-
- lib/tdl/auto_script/tmp/xilinx_hdl_dpram_sim_sdl.rb
|
923
825
|
- lib/tdl/axi4/axi4_combin_wr_rd_batch_auto.rb
|
924
826
|
- lib/tdl/axi4/axi4_direct.rb
|
925
827
|
- lib/tdl/axi4/axi4_direct_A1_auto.rb
|
@@ -1312,6 +1214,9 @@ files:
|
|
1312
1214
|
- lib/tdl/examples/9_itegration/test_tttop_constraints.xdc
|
1313
1215
|
- lib/tdl/examples/9_itegration/top.rb
|
1314
1216
|
- lib/tdl/examples/readme.md
|
1217
|
+
- lib/tdl/exlib/axis_eth_ex.rb
|
1218
|
+
- lib/tdl/exlib/axis_verify.rb
|
1219
|
+
- lib/tdl/exlib/clock_reset_verify.rb
|
1315
1220
|
- lib/tdl/exlib/common_cfg_reg_inf.rb
|
1316
1221
|
- lib/tdl/exlib/constraints.rb
|
1317
1222
|
- lib/tdl/exlib/constraints_verb.rb
|
@@ -1326,9 +1231,11 @@ files:
|
|
1326
1231
|
- lib/tdl/exlib/integral_test/simple_logic_itest.rb
|
1327
1232
|
- lib/tdl/exlib/itegration.rb
|
1328
1233
|
- lib/tdl/exlib/itegration_verb.rb
|
1234
|
+
- lib/tdl/exlib/logic_verify.rb
|
1329
1235
|
- lib/tdl/exlib/parse_argv.rb
|
1330
1236
|
- lib/tdl/exlib/sdlmodule_sim.bak.rb
|
1331
1237
|
- lib/tdl/exlib/test_point.rb
|
1238
|
+
- lib/tdl/exlib/test_point.rb.bak
|
1332
1239
|
- lib/tdl/global_scan.rb
|
1333
1240
|
- lib/tdl/rebuild_ele/axi4.rb
|
1334
1241
|
- lib/tdl/rebuild_ele/axi_lite.rb
|
@@ -1345,6 +1252,7 @@ files:
|
|
1345
1252
|
- lib/tdl/sdlimplement/test.rb
|
1346
1253
|
- lib/tdl/sdlmodule/bak/sdlmodule_varible_ex.rb
|
1347
1254
|
- lib/tdl/sdlmodule/generator_block_module.rb
|
1255
|
+
- lib/tdl/sdlmodule/sdlmodlule_path_db.rb
|
1348
1256
|
- lib/tdl/sdlmodule/sdlmodule.rb
|
1349
1257
|
- lib/tdl/sdlmodule/sdlmodule_arraychain.rb
|
1350
1258
|
- lib/tdl/sdlmodule/sdlmodule_draw.rb
|
@@ -1355,7 +1263,9 @@ files:
|
|
1355
1263
|
- lib/tdl/sdlmodule/sdlmodule_vcs_comptable.rb
|
1356
1264
|
- lib/tdl/sdlmodule/techbench_module.rb
|
1357
1265
|
- lib/tdl/sdlmodule/test_unit_module.rb
|
1266
|
+
- lib/tdl/sdlmodule/test_unit_module.rb.bak
|
1358
1267
|
- lib/tdl/sdlmodule/top_module.rb
|
1268
|
+
- lib/tdl/sdlmodule/top_module.rb.bak
|
1359
1269
|
- lib/tdl/tdl.rb
|
1360
1270
|
- lib/tdl/tdlerror/tdlerror.rb
|
1361
1271
|
- lib/tdl/testunit/test_all.rb
|
@@ -1380,7 +1290,7 @@ required_rubygems_version: !ruby/object:Gem::Requirement
|
|
1380
1290
|
- !ruby/object:Gem::Version
|
1381
1291
|
version: '0'
|
1382
1292
|
requirements: []
|
1383
|
-
rubygems_version: 3.0.
|
1293
|
+
rubygems_version: 3.0.3
|
1384
1294
|
signing_key:
|
1385
1295
|
specification_version: 4
|
1386
1296
|
summary: Axi 是一个轻量级的AXI4库. Tdl 是一种硬件构造语言
|
@@ -1,149 +0,0 @@
|
|
1
|
-
/**********************************************
|
2
|
-
_______________________________________
|
3
|
-
___________ Cook Darwin __________
|
4
|
-
_______________________________________
|
5
|
-
descript:
|
6
|
-
author : Cook.Darwin
|
7
|
-
Version: VERA.0.0
|
8
|
-
created: xxxx.xx.xx
|
9
|
-
madified:
|
10
|
-
***********************************************/
|
11
|
-
`timescale 1ns/1ps
|
12
|
-
|
13
|
-
module axi_stream_split_channel (
|
14
|
-
input [15:0] split_len,
|
15
|
-
axi_stream_inf.slaver origin_inf,
|
16
|
-
axi_stream_inf.master first_inf,
|
17
|
-
axi_stream_inf.master end_inf
|
18
|
-
);
|
19
|
-
|
20
|
-
//==========================================================================
|
21
|
-
//-------- define ----------------------------------------------------------
|
22
|
-
logic clock;
|
23
|
-
logic rst_n;
|
24
|
-
logic addr;
|
25
|
-
logic new_last;
|
26
|
-
axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.USIZE(1)) origin_inf_add_last (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
|
27
|
-
axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.USIZE(1)) sub_origin_inf [1:0] (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
|
28
|
-
//==========================================================================
|
29
|
-
//-------- instance --------------------------------------------------------
|
30
|
-
axi_stream_interconnect_S2M #(
|
31
|
-
.NUM (2 )
|
32
|
-
)axi_stream_interconnect_S2M_inst(
|
33
|
-
/* input */.addr (addr ),
|
34
|
-
/* axi_stream_inf.slaver */.s00 (origin_inf_add_last ),
|
35
|
-
/* axi_stream_inf.master */.m00 (sub_origin_inf )
|
36
|
-
);
|
37
|
-
//==========================================================================
|
38
|
-
//-------- expression ------------------------------------------------------
|
39
|
-
|
40
|
-
axi_stream_inf #(.DSIZE(first_inf.DSIZE)) sub_first_inf[1-1:0](.aclk(first_inf.aclk),.aresetn(first_inf.aresetn),.aclken(1'b1));
|
41
|
-
|
42
|
-
|
43
|
-
axis_direct axis_direct_first_inf_inst0 (
|
44
|
-
/* axi_stream_inf.slaver*/ .slaver (sub_origin_inf[0]),
|
45
|
-
/* axi_stream_inf.master*/ .master (sub_first_inf[0])
|
46
|
-
);
|
47
|
-
|
48
|
-
|
49
|
-
axi_stream_inf #(.DSIZE(end_inf.DSIZE)) sub_end_inf[1-1:0](.aclk(end_inf.aclk),.aresetn(end_inf.aresetn),.aclken(1'b1));
|
50
|
-
|
51
|
-
|
52
|
-
axis_direct axis_direct_end_inf_inst0 (
|
53
|
-
/* axi_stream_inf.slaver*/ .slaver (sub_origin_inf[1]),
|
54
|
-
/* axi_stream_inf.master*/ .master (sub_end_inf[0])
|
55
|
-
);
|
56
|
-
//-------- CLOCKs Total 3 ----------------------
|
57
|
-
//--->> CheckClock <<----------------
|
58
|
-
logic cc_done_8,cc_same_8;
|
59
|
-
integer cc_afreq_8,cc_bfreq_8;
|
60
|
-
ClockSameDomain CheckPClock_inst_8(
|
61
|
-
/* input */ .aclk (origin_inf.aclk ),
|
62
|
-
/* input */ .bclk (first_inf.aclk ),
|
63
|
-
/* output logic */ .done (cc_done_8),
|
64
|
-
/* output logic */ .same (cc_same_8),
|
65
|
-
/* output integer */ .aFreqK (cc_afreq_8),
|
66
|
-
/* output integer */ .bFreqK (cc_bfreq_8)
|
67
|
-
);
|
68
|
-
|
69
|
-
initial begin
|
70
|
-
wait(cc_done_8);
|
71
|
-
assert(cc_same_8)
|
72
|
-
else begin
|
73
|
-
$error("--- Error : `axi_stream_split_channel` clock is not same, origin_inf.aclk< %0f M> != first_inf.aclk<%0f M>",1000000.0/cc_afreq_8, 1000000.0/cc_bfreq_8);
|
74
|
-
repeat(10)begin
|
75
|
-
@(posedge origin_inf.aclk);
|
76
|
-
end
|
77
|
-
$stop;
|
78
|
-
end
|
79
|
-
end
|
80
|
-
//---<< CheckClock >>----------------
|
81
|
-
|
82
|
-
//--->> CheckClock <<----------------
|
83
|
-
logic cc_done_9,cc_same_9;
|
84
|
-
integer cc_afreq_9,cc_bfreq_9;
|
85
|
-
ClockSameDomain CheckPClock_inst_9(
|
86
|
-
/* input */ .aclk (origin_inf.aclk ),
|
87
|
-
/* input */ .bclk (end_inf.aclk ),
|
88
|
-
/* output logic */ .done (cc_done_9),
|
89
|
-
/* output logic */ .same (cc_same_9),
|
90
|
-
/* output integer */ .aFreqK (cc_afreq_9),
|
91
|
-
/* output integer */ .bFreqK (cc_bfreq_9)
|
92
|
-
);
|
93
|
-
|
94
|
-
initial begin
|
95
|
-
wait(cc_done_9);
|
96
|
-
assert(cc_same_9)
|
97
|
-
else begin
|
98
|
-
$error("--- Error : `axi_stream_split_channel` clock is not same, origin_inf.aclk< %0f M> != end_inf.aclk<%0f M>",1000000.0/cc_afreq_9, 1000000.0/cc_bfreq_9);
|
99
|
-
repeat(10)begin
|
100
|
-
@(posedge origin_inf.aclk);
|
101
|
-
end
|
102
|
-
$stop;
|
103
|
-
end
|
104
|
-
end
|
105
|
-
//---<< CheckClock >>----------------
|
106
|
-
|
107
|
-
//======== CLOCKs Total 3 ======================
|
108
|
-
assign clock = origin_inf.aclk;
|
109
|
-
assign rst_n = origin_inf.aresetn;
|
110
|
-
|
111
|
-
always_ff@(posedge clock,negedge rst_n) begin
|
112
|
-
if(~rst_n)begin
|
113
|
-
addr <= 1'b0;
|
114
|
-
new_last <= 1'b0;
|
115
|
-
end
|
116
|
-
else begin
|
117
|
-
new_last <= ( origin_inf.axis_tcnt==( split_len-2)&& origin_inf.axis_tvalid && origin_inf.axis_tready);
|
118
|
-
if(origin_inf.axis_tvalid && origin_inf.axis_tready && origin_inf.axis_tlast)begin
|
119
|
-
addr <= 1'b0;
|
120
|
-
end
|
121
|
-
else if( origin_inf.axis_tcnt==( split_len-1)&& origin_inf.axis_tvalid && origin_inf.axis_tready)begin
|
122
|
-
addr <= 1'b1;
|
123
|
-
end
|
124
|
-
else begin
|
125
|
-
addr <= addr;
|
126
|
-
end
|
127
|
-
end
|
128
|
-
end
|
129
|
-
|
130
|
-
assign origin_inf_add_last.axis_tdata = origin_inf.axis_tdata;
|
131
|
-
assign origin_inf_add_last.axis_tvalid = origin_inf.axis_tvalid;
|
132
|
-
assign origin_inf_add_last.axis_tuser = origin_inf.axis_tuser;
|
133
|
-
assign origin_inf_add_last.axis_tkeep = origin_inf.axis_tkeep;
|
134
|
-
assign origin_inf_add_last.axis_tlast = ( origin_inf.axis_tlast|new_last);
|
135
|
-
assign origin_inf.axis_tready = origin_inf_add_last.axis_tready;
|
136
|
-
|
137
|
-
|
138
|
-
axis_direct axis_direct_first_inf_instMM (
|
139
|
-
/* axi_stream_inf.slaver*/ .slaver (sub_first_inf[0]),
|
140
|
-
/* axi_stream_inf.master*/ .master (first_inf)
|
141
|
-
);
|
142
|
-
|
143
|
-
|
144
|
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axis_direct axis_direct_end_inf_instMM (
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/* axi_stream_inf.slaver*/ .slaver (sub_end_inf[0]),
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/* axi_stream_inf.master*/ .master (end_inf)
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);
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endmodule
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/**********************************************
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_______________________________________
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___________ Cook Darwin __________
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_______________________________________
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descript:
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author : Cook.Darwin
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Version: VERA.0.0
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created: xxxx.xx.xx
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madified:
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***********************************************/
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`timescale 1ns/1ps
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module axis_head_cut_verc #(
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parameter BYTE_BITS = 8,
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parameter DX = origin_inf.DSIZE/BYTE_BITS
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)(
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input [9:0] bytes,
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axi_stream_inf.slaver origin_inf,
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axi_stream_inf.master out_inf
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);
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//==========================================================================
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//-------- define ----------------------------------------------------------
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logic clock;
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logic rst_n;
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logic [18-1:0] origin_sync_info[3-1:0] ;
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logic [18-1:0] origin_sync_info_out[3-1:0] ;
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logic [10-1:0] bytes_Q ;
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logic [10-1:0] bytes_QQ ;
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logic [4-1:0] bytes_x ;
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logic [4-1:0] bytes_x_Q ;
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logic [4-1:0] bytes_x_tmp ;
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logic [4-1:0] bytes_x_sub_nDx ;
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logic [4-1:0] bytes_x_sub_nDx_tmp ;
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logic [2-1:0] route_addr ;
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logic [2-1:0] route_addr_tmp ;
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logic fifo_wr_en;
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logic [4-1:0] int_cut_len ;
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logic [4-1:0] shift_sel_pre ;
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logic fifo_wr_en_lat;
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logic [4-1:0] shift_sel ;
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axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.USIZE(1)) origin_inf_post (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
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axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.USIZE(1)) sub_origin_inf [2:0] (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
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axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.USIZE(1)) origin_inf_ss (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
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axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.USIZE(1)) origin_inf_cut_mix (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
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axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.USIZE(1)) origin_inf_ss_E0 (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
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axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.USIZE(1)) origin_inf_ss_E0_CH (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
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axi_stream_inf #(.DSIZE(out_inf.DSIZE),.USIZE(1)) out_inf_branchR671 (.aclk(out_inf.aclk),.aresetn(out_inf.aresetn),.aclken(1'b1)) ;
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//==========================================================================
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//-------- instance --------------------------------------------------------
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axis_pipe_sync_seam #(
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.LAT (3 ),
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.DSIZE (18 )
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)axis_pipe_sync_seam_inst(
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/* input */.in_datas (origin_sync_info ),
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/* output */.out_datas (origin_sync_info_out ),
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/* axi_stream_inf.slaver */.in_inf (origin_inf ),
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/* axi_stream_inf.master */.out_inf (origin_inf_post )
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);
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axi_stream_interconnect_S2M #(
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.NUM (3 )
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)axi_stream_interconnect_S2M_inst(
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/* input */.addr (route_addr ),
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/* axi_stream_inf.slaver */.s00 (origin_inf_post ),
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/* axi_stream_inf.master */.m00 (sub_origin_inf )
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);
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common_fifo #(
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.DEPTH (4 ),
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.DSIZE (4 )
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)common_fifo_head_bytesx_inst(
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/* input */.clock (clock ),
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/* input */.rst_n (rst_n ),
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/* input */.wdata (bytes_x ),
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/* input */.wr_en (fifo_wr_en && (bytes_x!= '0) ),
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/* output */.rdata (int_cut_len ),
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/* input */.rd_en ((sub_origin_inf[1].axis_tvalid && sub_origin_inf[1].axis_tready && sub_origin_inf[1].axis_tlast) ),
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/* output */.count (/*unused */ ),
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/* output */.empty (/*unused */ ),
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/* output */.full (/*unused */ )
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);
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axis_head_cut_verb axis_head_cut_verb_inst(
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/* input */.length ({12'd0,int_cut_len} ),
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/* axi_stream_inf.slaver */.axis_in (sub_origin_inf[1] ),
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/* axi_stream_inf.master */.axis_out (origin_inf_ss )
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);
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axis_append_A1 #(
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.MODE ("END" ),
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.DSIZE (out_inf.DSIZE ),
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.HEAD_FIELD_LEN (1 ),
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.HEAD_FIELD_NAME ("HEAD Filed" ),
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.END_FIELD_LEN (1 ),
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.END_FIELD_NAME ("END Filed" )
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)axis_append_A1_inst(
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/* input */.enable (1'b1 ),
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/* input */.head_value (/*unused */ ),
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/* input */.end_value ('0 ),
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/* axi_stream_inf.slaver */.origin_in (origin_inf_cut_mix ),
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/* axi_stream_inf.master */.append_out (origin_inf_ss_E0 )
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);
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common_fifo #(
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.DEPTH (4 ),
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.DSIZE (4 )
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)common_fifo_head_nDx_inst(
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/* input */.clock (clock ),
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/* input */.rst_n (rst_n ),
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/* input */.wdata (shift_sel_pre ),
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/* input */.wr_en (fifo_wr_en_lat ),
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/* output */.rdata (shift_sel ),
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/* input */.rd_en (origin_inf_ss_E0.axis_tvalid && origin_inf_ss_E0.axis_tready && origin_inf_ss_E0.axis_tlast ),
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/* output */.count (/*unused */ ),
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/* output */.empty (/*unused */ ),
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/* output */.full (/*unused */ )
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);
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axis_connect_pipe_right_shift_verb #(
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.SHIFT_BYTE_BIT (BYTE_BITS ),
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.SNUM (DX )
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)axis_connect_pipe_right_shift_verb_inst(
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/* input */.shift_sel (shift_sel ),
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/* axi_stream_inf.slaver */.axis_in (origin_inf_ss_E0 ),
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/* axi_stream_inf.master */.axis_out (origin_inf_ss_E0_CH )
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);
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axis_head_cut_verb last_cut_inst(
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/* input */.length (16'd1 ),
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/* axi_stream_inf.slaver */.axis_in (origin_inf_ss_E0_CH ),
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/* axi_stream_inf.master */.axis_out (out_inf_branchR671 )
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);
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//==========================================================================
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//-------- expression ------------------------------------------------------
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axi_stream_inf #(.DSIZE(out_inf.DSIZE)) sub_out_inf[2-1:0](.aclk(out_inf.aclk),.aresetn(out_inf.aresetn),.aclken(1'b1));
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axis_direct axis_direct_out_inf_inst0 (
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/* axi_stream_inf.slaver*/ .slaver (sub_origin_inf[0]),
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/* axi_stream_inf.master*/ .master (sub_out_inf[0])
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);
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axis_direct axis_direct_out_inf_inst1 (
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/* axi_stream_inf.slaver*/ .slaver (out_inf_branchR671),
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/* axi_stream_inf.master*/ .master (sub_out_inf[1])
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);
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axi_stream_inf #(.DSIZE(origin_inf_cut_mix.DSIZE)) sub_origin_inf_cut_mix[2-1:0](.aclk(origin_inf_cut_mix.aclk),.aresetn(origin_inf_cut_mix.aresetn),.aclken(1'b1));
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axis_direct axis_direct_origin_inf_cut_mix_inst0 (
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/* axi_stream_inf.slaver*/ .slaver (origin_inf_ss),
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/* axi_stream_inf.master*/ .master (sub_origin_inf_cut_mix[0])
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);
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axis_direct axis_direct_origin_inf_cut_mix_inst1 (
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/* axi_stream_inf.slaver*/ .slaver (sub_origin_inf[2]),
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/* axi_stream_inf.master*/ .master (sub_origin_inf_cut_mix[1])
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);
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initial begin
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assert( DX<17)else begin
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$error("param.DX<%0d> !< 17",DX);
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$stop;
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end
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end
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assign clock = origin_inf.aclk;
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assign rst_n = origin_inf.aresetn;
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165
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always_comb begin
|
167
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bytes_x_tmp = '0;
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168
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for(integer gvar_cc_1=0;gvar_cc_1<10;gvar_cc_1=gvar_cc_1+1)begin
|
169
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if( bytes<DX*(10-gvar_cc_1))begin
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170
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bytes_x_tmp = ( ( 10-1)-gvar_cc_1);
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end
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172
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end
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173
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end
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174
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|
175
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assign origin_sync_info[0] = {bytes_x_tmp,bytes_x_tmp,bytes};
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assign {bytes_x,bytes_Q} = {origin_sync_info_out[0][13:10],origin_sync_info_out[0][9:0]};
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assign bytes_x_sub_nDx_tmp = ( bytes_Q-( bytes_x*DX));
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assign origin_sync_info[1] = {bytes_x_sub_nDx_tmp,bytes_x,bytes_Q};
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assign {bytes_x_sub_nDx,bytes_x_Q,bytes_QQ} = {origin_sync_info_out[1][17:14],origin_sync_info_out[1][13:10],origin_sync_info_out[1][9:0]};
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assign origin_sync_info[2] = {10'd0,route_addr_tmp};
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181
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assign route_addr = origin_sync_info_out[2][1:0];
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182
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always_comb begin
|
184
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if( bytes_QQ=='0)begin
|
185
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route_addr_tmp = 2'd0;
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186
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-
end
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187
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else if( bytes_x_Q=='0)begin
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188
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route_addr_tmp = 2'd2;
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end
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else if( bytes_x_sub_nDx=='0)begin
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route_addr_tmp = 2'd1;
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192
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end
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else begin
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route_addr_tmp = 2'd1;
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195
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end
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end
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197
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always_ff@(posedge clock,negedge rst_n) begin
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199
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if(~rst_n)begin
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fifo_wr_en <= 1'b0;
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end
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else begin
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fifo_wr_en <= ( origin_inf.axis_tcnt=='0&& origin_inf.axis_tvalid && origin_inf.axis_tready);
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end
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end
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assign shift_sel_pre = ( DX-bytes_x_sub_nDx);
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208
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209
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//----->> fifo_wr_en LAST DELAY <<------------------
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211
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latency #(
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.LAT (2),
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.DSIZE (1)
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)fifo_wr_en_lat2_inst(
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clock,
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rst_n,
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fifo_wr_en,
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fifo_wr_en_lat
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);
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//-----<< fifo_wr_en LAST DELAY >>------------------
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axi_stream_interconnect_M2S_A1 #(
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//axi_stream_interconnect_M2S_noaddr #(
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.NUM (2)
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// .DSIZE (out_inf.DSIZE)
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)out_inf_M2S_noaddr_inst(
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/* axi_stream_inf.slaver */ .s00 (sub_out_inf ), //[NUM-1:0],
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/* axi_stream_inf.master */ .m00 (out_inf) //
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);
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axi_stream_interconnect_M2S_A1 #(
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234
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//axi_stream_interconnect_M2S_noaddr #(
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.NUM (2)
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// .DSIZE (origin_inf.DSIZE)
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)origin_inf_cut_mix_M2S_noaddr_inst(
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/* axi_stream_inf.slaver */ .s00 (sub_origin_inf_cut_mix ), //[NUM-1:0],
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/* axi_stream_inf.master */ .m00 (origin_inf_cut_mix) //
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);
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241
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-
|
242
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-
endmodule
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