axi_tdl 0.0.15 → 0.0.19

data/lib/axi/AXI4/wide_axis_to_axi4_wr.rb

@@ -1,5 +1,6 @@
 # require_relative "../prj_lib"
-require_hdl File.join(__dir__,"../AXI_stream/axis_length_split_with_addr.sv")
+require_hdl "axis_length_split_with_addr.sv"
+require_hdl 'axi_stream_wide_fifo.sv'
 new_m = SdlModule.new(name:File.basename(__FILE__,".rb"),out_sv_path:__dir__)
 new_m.target_class = AxiStream
 

data/lib/axi/AXI4/wide_axis_to_axi4_wr.sv

@@ -56,7 +56,7 @@ logic stream_en;
 axi_stream_inf #(.DSIZE(axis_in.DSIZE),.USIZE(1)) split_out (.aclk(axis_in.aclk),.aresetn(axis_in.aresetn),.aclken(1'b1)) ;
 axi_stream_inf #(.DSIZE(axis_in.DSIZE),.USIZE(1)) fifo_axis (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
 axi_stream_inf #(.DSIZE(axi_wr.IDSIZE + axi_wr.ASIZE + axi_wr.LSIZE),.USIZE(1)) id_add_len_in (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
-axi_inf #(.DSIZE(axi_wr.DSIZE),.IDSIZE(axi_wr.IDSIZE),.ASIZE(axi_wr.ASIZE),.LSIZE(axi_wr.LSIZE),.MODE(axi_wr.MODE),.ADDR_STEP(axi_wr.ADDR_STEP)) axi_wr_vcs_cp_R1842 (.axi_aclk(axi_wr.axi_aclk),.axi_aresetn(axi_wr.axi_aresetn)) ;
+axi_inf #(.DSIZE(axi_wr.DSIZE),.IDSIZE(axi_wr.IDSIZE),.ASIZE(axi_wr.ASIZE),.LSIZE(axi_wr.LSIZE),.MODE(axi_wr.MODE),.ADDR_STEP(axi_wr.ADDR_STEP)) axi_wr_vcs_cp_R236 (.axi_aclk(axi_wr.axi_aclk),.axi_aresetn(axi_wr.axi_aresetn)) ;
 axi_stream_inf #(.DSIZE(axis_in.DSIZE),.USIZE(1)) pipe_axis (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
 //==========================================================================
 //-------- instance --------------------------------------------------------
@@ -91,16 +91,16 @@ independent_clock_fifo #(
 /* output */.full     (fifo_full                                                                )
 );
 axi4_wr_auxiliary_gen_without_resp axi4_wr_auxiliary_gen_without_resp_inst(
-/* output                        */.stream_en     (stream_en           ),
-/* axi_stream_inf.slaver         */.id_add_len_in (id_add_len_in       ),
-/* axi_inf.master_wr_aux_no_resp */.axi_wr_aux    (axi_wr_vcs_cp_R1842 )
+/* output                        */.stream_en     (stream_en          ),
+/* axi_stream_inf.slaver         */.id_add_len_in (id_add_len_in      ),
+/* axi_inf.master_wr_aux_no_resp */.axi_wr_aux    (axi_wr_vcs_cp_R236 )
 );
 vcs_axi4_comptable #(
     .ORIGIN ("master_wr_aux_no_resp" ),
     .TO     ("master_wr"             )
-)vcs_axi4_comptable_axi_wr_aux_R1910_axi_wr_inst(
-/* input  */.origin (axi_wr_vcs_cp_R1842 ),
-/* output */.to     (axi_wr              )
+)vcs_axi4_comptable_axi_wr_aux_R372_axi_wr_inst(
+/* input  */.origin (axi_wr_vcs_cp_R236 ),
+/* output */.to     (axi_wr             )
 );
 axis_valve_with_pipe #(
     .MODE ("OUT" )
@@ -111,30 +111,30 @@ axis_valve_with_pipe #(
 );
 //==========================================================================
 //-------- expression ------------------------------------------------------
-always_ff@(posedge axis_in.aclk,negedge axis_in.aresetn) begin 
+always@(posedge axis_in.aclk,negedge axis_in.aresetn) begin 
     if(~axis_in.aresetn)begin
-         id <= 0;
+        id <= 0;
     end
     else if(split_out.axis_tvalid && split_out.axis_tready && split_out.axis_tlast)begin
-         id <= ( id+1);
+        id <= (id+1);
     end
     else begin
-         id <= id;
+        id <= id;
     end
 end
 
-assign  addr_s = addr_cur;
-assign  len_s = split_out.axis_tcnt;
-assign  id_add_len_in.axis_tvalid = ~fifo_empty;
-assign  id_add_len_in.axis_tdata = fifo_rdata;
-assign  id_add_len_in.axis_tlast = "1'b1";
-assign  fifo_rd_en = id_add_len_in.axis_tready;
+assign addr_s = addr_cur;
+assign len_s = split_out.axis_tcnt;
+assign id_add_len_in.axis_tvalid = ~fifo_empty;
+assign id_add_len_in.axis_tdata = fifo_rdata;
+assign id_add_len_in.axis_tlast = "1'b1";
+assign fifo_rd_en = id_add_len_in.axis_tready;
 
-assign  axi_wr.axi_wdata = pipe_axis.axis_tdata;
-assign  axi_wr.axi_wstrb = ~pipe_axis.axis_tkeep;
-assign  axi_wr.axi_wvalid = pipe_axis.axis_tvalid;
-assign  axi_wr.axi_wlast = pipe_axis.axis_tlast;
-assign  pipe_axis.axis_tready = axi_wr.axi_wready;
-assign  axi_wr.axi_bready = 1'b1;
+assign axi_wr.axi_wdata = pipe_axis.axis_tdata;
+assign axi_wr.axi_wstrb = ~pipe_axis.axis_tkeep;
+assign axi_wr.axi_wvalid = pipe_axis.axis_tvalid;
+assign axi_wr.axi_wlast = pipe_axis.axis_tlast;
+assign pipe_axis.axis_tready = axi_wr.axi_wready;
+assign axi_wr.axi_bready = 1'b1;
 
 endmodule

data/lib/axi/AXI_stream/axi_stream_split_channel.rb

@@ -20,7 +20,13 @@ TdlBuild.axi_stream_split_channel(__dir__) do
             new_last    <= 1.b0
         end
         ELSE do 
-            new_last    <= (origin_inf.axis_tcnt == (split_len - 2)).and(origin_inf.vld_rdy)
+            IF origin_inf.vld_rdy do 
+                new_last    <= (origin_inf.axis_tcnt == (split_len - 2))
+            end
+            ELSE do 
+                new_last    <= new_last
+            end
+            # new_last    <= (origin_inf.axis_tcnt == (split_len - 2)).and(origin_inf.vld_rdy)
 
             IF origin_inf.vld_rdy_last do 
                 addr    <= 1.b0 

data/lib/axi/AXI_stream/axis_head_cut_verb.sv

@@ -34,11 +34,15 @@ always_ff@(posedge axis_in.aclk, negedge axis_in.aresetn)
         if(axis_in.axis_tvalid && axis_in.axis_tready)begin 
             if(axis_in.axis_tlast)
                     ex_viliad   <= 1'b0;
+            else if(length == 16'd0)
+                    ex_viliad   <= 1'b1;
             else if(axis_in.axis_tcnt >= length - 1'b1)
                     ex_viliad   <= 1'b1;
             else    ex_viliad   <= ex_viliad;
-        end else begin 
-            ex_viliad   <= ex_viliad;
+        end else begin
+            if(axis_in.axis_tcnt == '0 && length == 16'd0)
+                    ex_viliad   <= 1'b1;
+            else    ex_viliad   <= ex_viliad;
         end
     end
 

data/lib/axi/AXI_stream/axis_insert_copy.rb

@@ -1,4 +1,4 @@
-
+require_hdl 'axis_connect_pipe.sv'
 
 TdlBuild.axis_insert_copy(__dir__) do 
     input[16]               - 'insert_seed'     ## 0 need first
@@ -37,15 +37,29 @@ TdlBuild.axis_insert_copy(__dir__) do
                 IF in_inf.vld_rdy_last do 
                     insert_tri  <= 1.b1 
                 end
-                ELSIF in_inf.vld_rdy do 
-                    insert_tri  <= (in_inf_valve.axis_tcnt >= insert_len - 1.b1 )
+                ELSIF in_inf_valve.vld_rdy do 
+                    insert_tri  <= (in_inf_valve.axis_tcnt < insert_len - 1.b1 )
+                end
+                ELSIF (in_inf_valve.axis_tcnt == 0.A).and( "~(#{in_inf.vld_rdy})".to_nq ) do 
+                    insert_tri  <= 1.b1 
                 end
                 ELSE do 
                     insert_tri  <= insert_tri
                 end
             end
             ELSE do 
-                insert_tri <= (in_inf_valve.axis_tcnt >= insert_seed - 1.b1 ).and(in_inf_valve.vld_rdy).and(in_inf_valve.axis_tcnt < insert_seed + insert_len - 1.b1).and( ~in_inf.axis_tlast)
+                IF in_inf_valve.vld_rdy do 
+                    IF (in_inf_valve.axis_tcnt >= insert_seed - 1.b1 ).and(in_inf_valve.axis_tcnt < insert_seed + insert_len - 1.b1).and( ~in_inf.axis_tlast) do 
+                        insert_tri  <= 1.b1 
+                    end
+                    ELSE do 
+                        insert_tri  <= 1.b0 
+                    end
+                end
+                ELSE do 
+                    insert_tri  <= insert_tri
+                end
+                # insert_tri <= (in_inf_valve.axis_tcnt >= insert_seed - 1.b1 ).and(in_inf_valve.vld_rdy).and(in_inf_valve.axis_tcnt < insert_seed + insert_len - 1.b1).and( ~in_inf.axis_tlast)
             end
         end
     end

data/lib/axi/AXI_stream/axis_sim_master_model.rb

@@ -0,0 +1,28 @@
+require_hdl 'data_c_sim_master_model.sv'
+
+TdlBuild.axis_sim_master_model(__dir__) do 
+    parameter.LOOP       "TRUE"
+    parameter.RAM_DEPTH  10000
+    input               - 'load_trigger'
+    input[32]           - 'total_length'
+    input[512*8]        - 'mem_file' # {axis_tvalid, axis_tuser, axis_tkeep, axis_tlast, axis_tdata}
+    port.axis.master    - 'out_inf'
+
+    data_inf_c(clock: out_inf.aclk, reset: out_inf.aresetn, dsize: "out_inf.DSIZE + out_inf.KSIZE + out_inf.USIZE + 1".to_nq) - 'out_inf_dc'
+
+    data_c_sim_master_model.data_c_sim_master_model_inst do |h| #(
+        h.param.LOOP        param.LOOP
+        h.param.RAM_DEPTH   param.RAM_DEPTH
+        h.input.load_trigger        load_trigger
+        h.input[32].total_length    total_length
+        h.input[512*8].mem_file     mem_file
+        h.port.data_inf_c.master.out_inf    out_inf_dc
+    end
+
+    Assign do 
+        out_inf.axis_tvalid <= out_inf_dc.valid 
+        out_inf_dc.ready    <= out_inf.axis_tready 
+
+        self.>>(out_inf.axis_tuser, out_inf.axis_tkeep, out_inf.axis_tlast, out_inf.axis_tdata) <= out_inf_dc.data
+    end 
+end

data/lib/axi/AXI_stream/axis_sim_slaver_model.rb

@@ -0,0 +1,26 @@
+require_hdl 'data_c_sim_slaver_model.sv'
+TdlBuild.axis_sim_slaver_model(__dir__) do 
+    parameter.RAM_DEPTH  10000
+    input               - 'load_trigger'
+    input[32]           - 'total_length'
+    input[512*8]        - 'mem_file' # 
+    port.axis.slaver    - 'in_inf'
+
+    data_inf_c(clock: in_inf.aclk, reset: in_inf.aresetn, dsize: "in_inf.DSIZE + in_inf.KSIZE + in_inf.USIZE + 1 + 1".to_nq) - 'in_inf_dc'
+
+    data_c_sim_slaver_model.data_c_sim_slaver_model_inst do |h|
+        h.param.RAM_DEPTH       param.RAM_DEPTH
+        h.input.load_trigger        load_trigger
+        h.input[32].total_length    total_length
+        h.input[512*8].mem_file     mem_file
+        h.port.data_inf_c.slaver.in_inf     in_inf_dc
+    end 
+
+    Assign do 
+        in_inf.axis_tready  <= in_inf_dc.ready
+        in_inf_dc.valid     <= in_inf.axis_tvalid
+
+        in_inf_dc.data  <+ self.>>(in_inf.axis_tuser, in_inf.axis_tkeep, in_inf.axis_tlast, in_inf.axis_tdata)
+    end
+
+end

data/lib/axi/AXI_stream/axis_sim_verify_by_coe.sv

@@ -0,0 +1,101 @@
+/**********************************************
+_______________________________________ 
+___________    Cook Darwin   __________    
+_______________________________________
+descript:
+author : Cook.Darwin
+Version: VERA.0.0
+created: xxxx.xx.xx
+madified:
+***********************************************/
+`timescale 1ns/1ps
+module axis_sim_verify_by_coe #(
+    parameter  RAM_DEPTH    = 10000,
+    parameter  VERIFY_KEEP  = "OFF",
+    parameter  VERIFY_USER  = "OFF"
+)(
+    input                   load_trigger,
+    input [31:0]            total_length,
+    input [4095:0]          mem_file,
+    axi_stream_inf.mirror   mirror_inf
+);
+
+
+
+logic [mirror_inf.DSIZE+mirror_inf.USIZE+mirror_inf.KSIZE+1-1:0] BRAM [RAM_DEPTH-1:0];
+int  total_length_lock;
+initial begin
+    #(1ns);
+    total_length_lock = RAM_DEPTH;
+    $readmemh(mem_file, BRAM, 0, RAM_DEPTH-1);
+end
+
+always@(posedge load_trigger)begin 
+    total_length_lock = total_length;
+    $readmemh(mem_file, BRAM, 0, RAM_DEPTH-1);
+end
+
+int     index;
+initial begin
+    index = 0;
+end
+
+always@(posedge mirror_inf.aclk) begin 
+    if(~mirror_inf.aresetn) index     <= 0;
+    else begin 
+        if(mirror_inf.axis_tready && mirror_inf.axis_tvalid) begin 
+            if(index >= total_length_lock-1)begin 
+                // index <= 0;
+                index <= total_length_lock;
+                if(index != total_length_lock)
+                    $display(" COE READ VERIFY DONE. \n %0s\n",mem_file);
+            end else begin 
+                index <= index + 1;
+            end 
+        end else begin 
+            index <= index;
+        end 
+    end 
+end 
+
+logic[mirror_inf.DSIZE-1:0]     axis_tdata;
+logic[mirror_inf.KSIZE-1:0]     axis_tkeep;
+logic[mirror_inf.USIZE-1:0]     axis_tuser;
+logic                           axis_tlast;
+
+assign {axis_tuser,axis_tkeep,axis_tlast,axis_tdata}    = BRAM[index];
+// assign mirror_inf.data     = BRAM[index][mirror_inf.DSIZE-1:0];
+// assign mirror_inf.valid    = BRAM[index][mirror_inf.DSIZE]; 
+
+always@(negedge mirror_inf.aclk)begin 
+    if(mirror_inf.axis_tvalid && mirror_inf.axis_tready && index < total_length_lock)begin 
+        assert(axis_tdata == mirror_inf.axis_tdata)
+        else begin 
+            $error("coe axis_tdata<%0h> != mirror_inf.axis_tdata<%0h>",axis_tdata, mirror_inf.axis_tdata);
+            $stop();
+        end
+
+        assert(axis_tlast == mirror_inf.axis_tlast)
+        else begin 
+            $error("coe axis_tlast<%0h> != mirror_inf.axis_tlast<%0h>",axis_tlast, mirror_inf.axis_tlast);
+            $stop();
+        end
+
+        if(VERIFY_KEEP=="ON" || VERIFY_KEEP=="TRUE")begin 
+            assert(axis_tkeep == mirror_inf.axis_tkeep)
+            else begin 
+                $error("coe axis_tkeep<%0h> != mirror_inf.axis_tkeep<%0h>",axis_tkeep, mirror_inf.axis_tkeep);
+                $stop();
+            end
+        end
+
+        if(VERIFY_USER=="ON" || VERIFY_USER=="TRUE")begin 
+            assert(axis_tuser == mirror_inf.axis_tuser)
+            else begin 
+                $error("coe axis_tuser<%0h> != mirror_inf.axis_tuser<%0h>",axis_tuser, mirror_inf.axis_tuser);
+            end
+        end 
+    end 
+end 
+
+endmodule

data/lib/axi/AXI_stream/axis_split_channel_verb.rb

@@ -1,6 +1,8 @@
 ## VERB
 ## - insert copy first
 require_sdl 'axis_insert_copy.rb'
+require_hdl 'common_fifo.sv'
+require_sdl 'axi_stream_split_channel.rb'
 TdlBuild.axis_split_channel_verb(__dir__) do 
     input[16]               - 'split_len'       # 1:need 1 size ; split len must large than 2
     port.axis.slaver        - 'origin_inf'

data/lib/axi/common/common_ram_sim_wrapper.sv

@@ -13,7 +13,7 @@ madified:
 module common_ram_sim_wrapper #(
     parameter  FNUM = 8
 )(
-    input [ FNUM-1:0]   load_files,
+    input [FNUM-1:0]    load_files,
     input [4095:0]      init_files [FNUM-1:0],
     cm_ram_inf.slaver   ram_inf
 );
@@ -59,17 +59,17 @@ xilinx_hdl_dpram_sim #(
 );
 //==========================================================================
 //-------- expression ------------------------------------------------------
-assign  addra = ram_inf.addra;
-assign  dina = ram_inf.dia;
-assign  addrb = ram_inf.addrb;
-assign  dinb = ram_inf.dib;
+assign addra = ram_inf.addra;
+assign dina = ram_inf.dia;
+assign addrb = ram_inf.addrb;
+assign dinb = ram_inf.dib;
 
-always_ff@(posedge ram_inf.clka) begin 
-     ram_inf.doa <= douta[ ram_inf.DSIZE-1:0];
+always@(posedge ram_inf.clka) begin 
+    ram_inf.doa <= douta[ram_inf.DSIZE-1:0];
 end
 
-always_ff@(posedge ram_inf.clkb) begin 
-     ram_inf.dob <= doutb[ ram_inf.DSIZE-1:0];
+always@(posedge ram_inf.clkb) begin 
+    ram_inf.dob <= doutb[ram_inf.DSIZE-1:0];
 end
 
 endmodule

data/lib/axi/common/common_ram_wrapper.sv

@@ -56,26 +56,26 @@ xilinx_hdl_dpram #(
 );
 //==========================================================================
 //-------- expression ------------------------------------------------------
-assign  addra = ram_inf.addra;
-assign  dina = ram_inf.dia;
-assign  addrb = ram_inf.addrb;
-assign  dinb = ram_inf.dib;
+assign addra = ram_inf.addra;
+assign dina = ram_inf.dia;
+assign addrb = ram_inf.addrb;
+assign dinb = ram_inf.dib;
 
-always_ff@(posedge ram_inf.clka) begin 
-    if( ram_inf.DSIZE<34)begin
-         ram_inf.doa <= douta[32:0];
+always@(posedge ram_inf.clka) begin 
+    if(ram_inf.DSIZE<34)begin
+        ram_inf.doa <= douta[32:0];
     end
     else begin
-         ram_inf.doa <= douta;
+        ram_inf.doa <= douta;
     end
 end
 
-always_ff@(posedge ram_inf.clkb) begin 
-    if( ram_inf.DSIZE<34)begin
-         ram_inf.dob <= doutb[32:0];
+always@(posedge ram_inf.clkb) begin 
+    if(ram_inf.DSIZE<34)begin
+        ram_inf.dob <= doutb[32:0];
     end
     else begin
-         ram_inf.dob <= doutb;
+        ram_inf.dob <= doutb;
     end
 end
 

data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.sv

@@ -14,8 +14,8 @@ module data_c_pipe_sync_seam #(
     parameter  LAT   = 4,
     parameter  DSIZE = 32
 )(
-    input [ DSIZE-1:0]  in_datas  [LAT-1:0],
-    output [ DSIZE-1:0] out_datas [LAT-1:0],
+    input [DSIZE-1:0]   in_datas  [LAT-1:0],
+    output [DSIZE-1:0]  out_datas [LAT-1:0],
     data_inf_c.slaver   in_inf,
     data_inf_c.master   out_inf
 );
@@ -35,35 +35,35 @@ for(genvar KK0=0;KK0 < LAT;KK0++)begin
     data_c_pipe_sync #(
         .DSIZE (DSIZE )
     )data_c_pipe_sync_inst(
-    /* input             */.in_data  (in_datas[ KK0]      ),
-    /* output            */.out_data (out_datas[ KK0]     ),
-    /* data_inf_c.slaver */.in_inf   (in_inf_array[ KK0]  ),
-    /* data_inf_c.master */.out_inf  (out_inf_array[ KK0] )
+    /* input             */.in_data  (in_datas[KK0]      ),
+    /* output            */.out_data (out_datas[KK0]     ),
+    /* data_inf_c.slaver */.in_inf   (in_inf_array[KK0]  ),
+    /* data_inf_c.master */.out_inf  (out_inf_array[KK0] )
     );
-    if( KK0!=0)begin
-        assign  in_inf_array[ KK0].valid = out_inf_array[ KK0-1].valid;
-        assign  in_inf_array[ KK0].data = out_inf_array[ KK0-1].data;
-        assign  out_inf_array[ KK0-1].ready = in_inf_array[ KK0].ready;
+    if(KK0!=0)begin
+        assign in_inf_array[KK0].valid = out_inf_array[KK0-1].valid;
+        assign in_inf_array[KK0].data = out_inf_array[KK0-1].data;
+        assign out_inf_array[KK0-1].ready = in_inf_array[KK0].ready;
     end end
 endgenerate
 //-------- CLOCKs Total 2 ----------------------
 //--->> CheckClock <<----------------
-logic cc_done_10,cc_same_10;
-integer cc_afreq_10,cc_bfreq_10;
-ClockSameDomain CheckPClock_inst_10(
+logic cc_done_7,cc_same_7;
+integer cc_afreq_7,cc_bfreq_7;
+ClockSameDomain CheckPClock_inst_7(
 /*  input         */      .aclk     (in_inf.clock           ),
 /*  input         */      .bclk     (out_inf.clock          ),
-/*  output logic  */      .done     (cc_done_10),
-/*  output logic  */      .same     (cc_same_10),
-/*  output integer */     .aFreqK   (cc_afreq_10),
-/*  output integer */     .bFreqK   (cc_bfreq_10)
+/*  output logic  */      .done     (cc_done_7),
+/*  output logic  */      .same     (cc_same_7),
+/*  output integer */     .aFreqK   (cc_afreq_7),
+/*  output integer */     .bFreqK   (cc_bfreq_7)
 );
 
 initial begin
-    wait(cc_done_10);
-    assert(cc_same_10)
+    wait(cc_done_7);
+    assert(cc_same_7)
     else begin
-        $error("--- Error : `data_c_pipe_sync_seam` clock is not same, in_inf.clock< %0f M> != out_inf.clock<%0f M>",1000000.0/cc_afreq_10, 1000000.0/cc_bfreq_10);
+        $error("--- Error : `data_c_pipe_sync_seam` clock is not same, in_inf.clock< %0f M> != out_inf.clock<%0f M>",1000000.0/cc_afreq_7, 1000000.0/cc_bfreq_7);
         repeat(10)begin 
             @(posedge in_inf.clock);
         end
@@ -73,12 +73,12 @@ end
 //---<< CheckClock >>----------------
 
 //======== CLOCKs Total 2 ======================
-assign  in_inf_array[0].valid = in_inf.valid;
-assign  in_inf_array[0].data = in_inf.data;
-assign  in_inf.ready = in_inf_array[0].ready;
+assign in_inf_array[0].valid = in_inf.valid;
+assign in_inf_array[0].data = in_inf.data;
+assign in_inf.ready = in_inf_array[0].ready;
 
-assign  out_inf.data = out_inf_array[ LAT-1].data;
-assign  out_inf.valid = out_inf_array[ LAT-1].valid;
-assign  out_inf_array[ LAT-1].ready = out_inf.ready;
+assign out_inf.data = out_inf_array[LAT-1].data;
+assign out_inf.valid = out_inf_array[LAT-1].valid;
+assign out_inf_array[LAT-1].ready = out_inf.ready;
 
 endmodule