axi_tdl 0.0.15 → 0.0.19
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- checksums.yaml +4 -4
- data/.github/workflows/gem-push.yml +4 -2
- data/axi_tdl.gemspec +0 -1
- data/lib/axi/AXI4/axi4_direct_B1.sv +23 -23
- data/lib/axi/AXI4/axi4_dpram_cache.sv +33 -33
- data/lib/axi/AXI4/axis_to_axi4_wr.rb +1 -0
- data/lib/axi/AXI4/axis_to_axi4_wr.sv +20 -20
- data/lib/axi/AXI4/packet_partition/axi4_partition_rd_verb.sv +32 -32
- data/lib/axi/AXI4/packet_partition/data_inf_partition.rb +2 -0
- data/lib/axi/AXI4/packet_partition/data_inf_partition.sv +71 -71
- data/lib/axi/AXI4/wide_axis_to_axi4_wr.rb +2 -1
- data/lib/axi/AXI4/wide_axis_to_axi4_wr.sv +23 -23
- data/lib/axi/AXI_stream/axi_stream_split_channel.rb +7 -1
- data/lib/axi/AXI_stream/axis_head_cut_verb.sv +6 -2
- data/lib/axi/AXI_stream/axis_insert_copy.rb +18 -4
- data/lib/axi/AXI_stream/axis_sim_master_model.rb +28 -0
- data/lib/axi/AXI_stream/axis_sim_slaver_model.rb +26 -0
- data/lib/axi/AXI_stream/axis_sim_verify_by_coe.sv +101 -0
- data/lib/axi/AXI_stream/axis_split_channel_verb.rb +2 -0
- data/lib/axi/common/common_ram_sim_wrapper.sv +9 -9
- data/lib/axi/common/common_ram_wrapper.sv +12 -12
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.sv +26 -26
- data/lib/axi/data_interface/data_inf_c/data_c_sim_master_model.sv +69 -0
- data/lib/axi/data_interface/data_inf_c/data_c_sim_slaver_model.sv +58 -0
- data/lib/axi/data_interface/data_inf_c/logic_sim_model.sv +64 -0
- data/lib/axi/techbench/tb_axi_stream_split_channel.rb +69 -0
- data/lib/axi/techbench/tb_axi_stream_split_channel.sv +149 -0
- data/lib/axi/techbench/tb_axis_split_channel_verb.rb +69 -0
- data/lib/axi/techbench/tb_axis_split_channel_verb.sv +125 -0
- data/lib/axi_tdl.rb +1 -0
- data/lib/axi_tdl/version.rb +1 -1
- data/lib/tdl/auto_script/autogensdl.rb +16 -5
- data/lib/tdl/axi4/axi4_interconnect_verb.rb +4 -2
- data/lib/tdl/basefunc.rb +1 -0
- data/lib/tdl/class_hdl/hdl_always_comb.rb +4 -3
- data/lib/tdl/class_hdl/hdl_always_ff.rb +48 -7
- data/lib/tdl/class_hdl/hdl_assign.rb +5 -3
- data/lib/tdl/class_hdl/hdl_block_ifelse.rb +11 -9
- data/lib/tdl/class_hdl/hdl_foreach.rb +2 -2
- data/lib/tdl/class_hdl/hdl_function.rb +4 -2
- data/lib/tdl/class_hdl/hdl_generate.rb +5 -4
- data/lib/tdl/class_hdl/hdl_initial.rb +11 -10
- data/lib/tdl/class_hdl/hdl_module_def.rb +18 -1
- data/lib/tdl/class_hdl/hdl_redefine_opertor.rb +35 -14
- data/lib/tdl/class_hdl/hdl_struct.rb +1 -1
- data/lib/tdl/class_hdl/hdl_verify.rb +1 -1
- data/lib/tdl/elements/originclass.rb +6 -1
- data/lib/tdl/elements/parameter.rb +1 -1
- data/lib/tdl/examples/10_random/exp_random.sv +3 -3
- data/lib/tdl/examples/11_test_unit/dve.tcl +155 -2
- data/lib/tdl/examples/11_test_unit/exp_test_unit.rb +9 -8
- data/lib/tdl/examples/11_test_unit/exp_test_unit.sv +1 -1
- data/lib/tdl/examples/11_test_unit/modules/sub_md0.rb +6 -3
- data/lib/tdl/examples/11_test_unit/modules/sub_md0.sv +5 -5
- data/lib/tdl/examples/11_test_unit/modules/sub_md1.rb +9 -4
- data/lib/tdl/examples/11_test_unit/modules/sub_md1.sv +5 -5
- data/lib/tdl/examples/11_test_unit/tb_exp_test_unit.sv +1 -2
- data/lib/tdl/examples/11_test_unit/tu0.sv +9 -9
- data/lib/tdl/examples/11_test_unit/tu1.sv +1 -1
- data/lib/tdl/examples/1_define_module/exmple_md.sv +12 -12
- data/lib/tdl/examples/2_hdl_class/tmp/always_comb_test.sv +60 -60
- data/lib/tdl/examples/2_hdl_class/tmp/always_ff_test.sv +2 -2
- data/lib/tdl/examples/2_hdl_class/tmp/case_test.sv +17 -17
- data/lib/tdl/examples/2_hdl_class/tmp/head_pkg_module.sv +9 -9
- data/lib/tdl/examples/2_hdl_class/tmp/simple_assign_test.sv +1 -1
- data/lib/tdl/examples/2_hdl_class/tmp/state_case_test.sv +10 -10
- data/lib/tdl/examples/2_hdl_class/tmp/test_foreach.sv +3 -3
- data/lib/tdl/examples/2_hdl_class/tmp/test_function.sv +7 -7
- data/lib/tdl/examples/2_hdl_class/tmp/test_initial_assert.sv +3 -3
- data/lib/tdl/examples/2_hdl_class/tmp/test_module.sv +2 -2
- data/lib/tdl/examples/2_hdl_class/tmp/test_module_var.sv +2 -2
- data/lib/tdl/examples/2_hdl_class/tmp/test_package.sv +4 -5
- data/lib/tdl/examples/2_hdl_class/tmp/test_package2.sv +4 -4
- data/lib/tdl/examples/2_hdl_class/tmp/test_struct_function.sv +2 -2
- data/lib/tdl/examples/2_hdl_class/tmp/test_vcs_string.sv +1 -1
- data/lib/tdl/examples/2_hdl_class/tmp/text_generate.sv +7 -7
- data/lib/tdl/examples/4_generate/test_generate.sv +11 -11
- data/lib/tdl/examples/5_logic_combin/test_logic_combin.sv +3 -3
- data/lib/tdl/examples/7_module_with_package/body_package.sv +3 -4
- data/lib/tdl/examples/7_module_with_package/example_pkg.sv +4 -4
- data/lib/tdl/examples/7_module_with_package/head_package.sv +3 -4
- data/lib/tdl/examples/8_top_module/tb_test_top.sv +1 -1
- data/lib/tdl/examples/9_itegration/tb_test_tttop.sv +2 -4
- data/lib/tdl/examples/9_itegration/test_tttop.sv +3 -3
- data/lib/tdl/exlib/axis_eth_ex.rb +95 -0
- data/lib/tdl/exlib/axis_verify.rb +264 -0
- data/lib/tdl/exlib/clock_reset_verify.rb +29 -0
- data/lib/tdl/exlib/dve_tcl.rb +30 -11
- data/lib/tdl/exlib/itegration.rb +15 -3
- data/lib/tdl/exlib/logic_verify.rb +88 -0
- data/lib/tdl/exlib/test_point.rb +96 -94
- data/lib/tdl/exlib/test_point.rb.bak +293 -0
- data/lib/tdl/rebuild_ele/ele_base.rb +1 -1
- data/lib/tdl/sdlmodule/sdlmodlule_path_db.rb +34 -0
- data/lib/tdl/sdlmodule/sdlmodule.rb +18 -14
- data/lib/tdl/sdlmodule/sdlmodule_draw.rb +81 -16
- data/lib/tdl/sdlmodule/test_unit_module.rb +272 -33
- data/lib/tdl/sdlmodule/test_unit_module.rb.bak +143 -0
- data/lib/tdl/sdlmodule/top_module.rb +53 -48
- data/lib/tdl/sdlmodule/top_module.rb.bak +547 -0
- data/lib/tdl/tdl.rb +18 -3
- metadata +21 -111
- data/lib/axi/AXI_stream/axi_stream_split_channel.sv +0 -149
- data/lib/axi/AXI_stream/axis_head_cut_verc.sv +0 -242
- data/lib/axi/AXI_stream/axis_insert_copy.sv +0 -66
- data/lib/axi/AXI_stream/axis_pipe_sync_seam.sv +0 -48
- data/lib/axi/AXI_stream/axis_rom_contect_sim.sv +0 -113
- data/lib/axi/AXI_stream/axis_split_channel_verb.sv +0 -62
@@ -1,66 +0,0 @@
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/**********************************************
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_______________________________________
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___________ Cook Darwin __________
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_______________________________________
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descript:
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author : Cook.Darwin
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Version: VERA.0.0
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created: xxxx.xx.xx
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madified:
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***********************************************/
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`timescale 1ns/1ps
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module axis_insert_copy (
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input [15:0] insert_seed,
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input [7:0] insert_len,
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axi_stream_inf.slaver in_inf,
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axi_stream_inf.master out_inf
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);
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//==========================================================================
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//-------- define ----------------------------------------------------------
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logic clock;
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logic rst_n;
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logic insert_tri;
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axi_stream_inf #(.DSIZE(in_inf.DSIZE),.USIZE(1)) in_inf_valve (.aclk(in_inf.aclk),.aresetn(in_inf.aresetn),.aclken(1'b1)) ;
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//==========================================================================
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//-------- instance --------------------------------------------------------
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axis_connect_pipe axis_connect_pipe_inst(
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/* axi_stream_inf.slaver */.axis_in (in_inf_valve ),
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/* axi_stream_inf.master */.axis_out (out_inf )
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);
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//==========================================================================
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//-------- expression ------------------------------------------------------
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assign clock = in_inf.aclk;
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assign rst_n = in_inf.aresetn;
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assign in_inf_valve.axis_tdata = in_inf.axis_tdata;
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assign in_inf_valve.axis_tvalid = ( in_inf.axis_tvalid|insert_tri);
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assign in_inf_valve.axis_tuser = in_inf.axis_tuser;
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assign in_inf_valve.axis_tkeep = in_inf.axis_tkeep;
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assign in_inf.axis_tready = ( in_inf_valve.axis_tready&~insert_tri);
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assign in_inf_valve.axis_tlast = ( in_inf.axis_tlast&~insert_tri);
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always_ff@(posedge clock,negedge rst_n) begin
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if(~rst_n)begin
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insert_tri <= 1'b0;
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end
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else begin
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if( insert_seed=='0)begin
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if(in_inf.axis_tvalid && in_inf.axis_tready && in_inf.axis_tlast)begin
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insert_tri <= 1'b1;
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end
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else if(in_inf.axis_tvalid && in_inf.axis_tready)begin
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insert_tri <= ( in_inf_valve.axis_tcnt>=( insert_len-1'b1));
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end
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else begin
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insert_tri <= insert_tri;
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end
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end
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else begin
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insert_tri <= ( in_inf_valve.axis_tcnt>=( insert_seed-1'b1)&& in_inf_valve.axis_tvalid && in_inf_valve.axis_tready && ( in_inf_valve.axis_tcnt<( ( insert_seed+insert_len)-1'b1))&& ~in_inf.axis_tlast);
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end
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end
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end
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endmodule
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/**********************************************
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_______________________________________
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___________ Cook Darwin __________
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_______________________________________
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descript:
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author : Cook.Darwin
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Version: VERA.0.0
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created: xxxx.xx.xx
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madified:
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***********************************************/
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`timescale 1ns/1ps
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module axis_pipe_sync_seam #(
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parameter LAT = 4,
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parameter DSIZE = 32
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)(
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input [ DSIZE-1:0] in_datas [LAT-1:0],
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output [ DSIZE-1:0] out_datas [LAT-1:0],
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axi_stream_inf.slaver in_inf,
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axi_stream_inf.master out_inf
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);
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//==========================================================================
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//-------- define ----------------------------------------------------------
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data_inf_c #(.DSIZE(in_inf.DSIZE+in_inf.KSIZE+1+in_inf.USIZE)) data_in_inf (.clock(in_inf.aclk),.rst_n(in_inf.aresetn)) ;
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data_inf_c #(.DSIZE(in_inf.DSIZE+in_inf.KSIZE+1+in_inf.USIZE)) data_out_inf (.clock(in_inf.aclk),.rst_n(in_inf.aresetn)) ;
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//==========================================================================
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//-------- instance --------------------------------------------------------
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data_c_pipe_sync_seam #(
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.LAT (LAT ),
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.DSIZE (DSIZE )
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)data_c_pipe_sync_seam_inst(
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/* input */.in_datas (in_datas ),
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/* output */.out_datas (out_datas ),
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/* data_inf_c.slaver */.in_inf (data_in_inf ),
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/* data_inf_c.master */.out_inf (data_out_inf )
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);
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//==========================================================================
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//-------- expression ------------------------------------------------------
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assign data_in_inf.data = {>>{in_inf.axis_tuser,in_inf.axis_tkeep,in_inf.axis_tlast,in_inf.axis_tdata}};
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assign data_in_inf.valid = in_inf.axis_tvalid;
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assign in_inf.axis_tready = data_in_inf.ready;
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assign {out_inf.axis_tuser,out_inf.axis_tkeep,out_inf.axis_tlast,out_inf.axis_tdata} = data_out_inf.data;
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assign out_inf.axis_tvalid = data_out_inf.valid;
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assign data_out_inf.ready = out_inf.axis_tready;
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endmodule
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/**********************************************
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_______________________________________
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___________ Cook Darwin __________
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_______________________________________
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descript:
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author : Cook.Darwin
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Version: VERA.0.0
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created: xxxx.xx.xx
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madified:
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***********************************************/
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`timescale 1ns/1ps
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module axis_rom_contect_sim #(
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parameter FNUM = 8,
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parameter STEP = 1
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)(
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input [ FNUM-1:0] load_files,
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input [4095:0] init_files [FNUM-1:0],
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axi_stream_inf.slaver a_axis_zip,
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axi_stream_inf.slaver b_axis_zip,
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axi_stream_inf.master a_rom_contect_inf,
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axi_stream_inf.master b_rom_contect_inf
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);
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//==========================================================================
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//-------- define ----------------------------------------------------------
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axi_stream_inf #(.DSIZE( a_axis_zip.DSIZE/2),.USIZE(1)) a_axis_unzip (.aclk(a_axis_zip.aclk),.aresetn(a_axis_zip.aresetn),.aclken(1'b1)) ;
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axi_stream_inf #(.DSIZE( b_axis_zip.DSIZE/2),.USIZE(1)) b_axis_unzip (.aclk(b_axis_zip.aclk),.aresetn(b_axis_zip.aresetn),.aclken(1'b1)) ;
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cm_ram_inf #(.DSIZE(a_rom_contect_inf.DSIZE),.RSIZE(a_axis_zip.DSIZE),.MSIZE(1)) xram_inf();
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axi_stream_inf #(.DSIZE(a_rom_contect_inf.DSIZE+ a_axis_zip.DSIZE/2),.USIZE(1)) a_rom_contect_inf_pre (.aclk(a_rom_contect_inf.aclk),.aresetn(a_rom_contect_inf.aresetn),.aclken(1'b1)) ;
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axi_stream_inf #(.DSIZE(b_rom_contect_inf.DSIZE+ b_axis_zip.DSIZE/2),.USIZE(1)) b_rom_contect_inf_pre (.aclk(b_rom_contect_inf.aclk),.aresetn(b_rom_contect_inf.aresetn),.aclken(1'b1)) ;
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//==========================================================================
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//-------- instance --------------------------------------------------------
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axis_uncompress_A1 #(
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.ASIZE ( a_axis_zip.DSIZE/2 ),
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.LSIZE ( a_axis_zip.DSIZE/2 ),
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.STEP (STEP )
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)axis_uncompress_A1_ainst(
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/* axi_stream_inf.slaver */.axis_zip (a_axis_zip ),
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/* axi_stream_inf.master */.axis_unzip (a_axis_unzip )
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);
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axis_uncompress_A1 #(
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.ASIZE ( a_axis_zip.DSIZE/2 ),
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.LSIZE ( a_axis_zip.DSIZE/2 ),
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.STEP (STEP )
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)axis_uncompress_A1_binst(
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/* axi_stream_inf.slaver */.axis_zip (b_axis_zip ),
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/* axi_stream_inf.master */.axis_unzip (b_axis_unzip )
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);
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common_ram_sim_wrapper #(
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.FNUM (FNUM )
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)common_ram_wrapper_sim_inst(
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/* input */.load_files (load_files ),
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/* input */.init_files (init_files ),
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/* cm_ram_inf.slaver */.ram_inf (xram_inf )
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);
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axi_stream_planer #(
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.LAT (3 ),
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.DSIZE (a_rom_contect_inf.DSIZE ),
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.HEAD ("FALSE" )
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)axi_stream_planer_ainst(
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/* input */.reset (~a_axis_zip.aresetn ),
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/* input */.pack_data (xram_inf.doa ),
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/* axi_stream_inf.slaver */.axis_in (a_axis_unzip ),
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/* axi_stream_inf.master */.axis_out (a_rom_contect_inf_pre )
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);
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axi_stream_planer #(
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.LAT (3 ),
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.DSIZE (b_rom_contect_inf.DSIZE ),
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.HEAD ("FALSE" )
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)axi_stream_planer_binst(
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/* input */.reset (~b_axis_zip.aresetn ),
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/* input */.pack_data (xram_inf.dob ),
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/* axi_stream_inf.slaver */.axis_in (b_axis_unzip ),
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/* axi_stream_inf.master */.axis_out (b_rom_contect_inf_pre )
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);
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//==========================================================================
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//-------- expression ------------------------------------------------------
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initial begin
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assert( a_axis_zip.DSIZE==b_axis_zip.DSIZE)else begin
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$error("a_axis_zip.DSIZE<%0d> must equal b_axis_zip.DSIZE<%0d>",a_axis_zip.DSIZE,b_axis_zip.DSIZE);
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$stop;
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84
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-
end
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85
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-
assert( a_rom_contect_inf.DSIZE==b_rom_contect_inf.DSIZE)else begin
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86
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$error("a_rom_contect_inf.DSIZE<%0d>==b_rom_contect_inf.DSIZE<%0d>",a_rom_contect_inf.DSIZE,b_rom_contect_inf.DSIZE);
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87
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$stop;
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88
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-
end
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89
|
-
end
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90
|
-
|
91
|
-
assign xram_inf.addra = a_axis_unzip.axis_tdata;
|
92
|
-
assign xram_inf.dia = '0;
|
93
|
-
assign xram_inf.wea = '0;
|
94
|
-
assign xram_inf.ena = 1'b1;
|
95
|
-
assign xram_inf.clka = a_axis_zip.aclk;
|
96
|
-
assign xram_inf.rsta = ~a_axis_zip.aresetn;
|
97
|
-
assign xram_inf.addrb = b_axis_unzip.axis_tdata;
|
98
|
-
assign xram_inf.dib = '0;
|
99
|
-
assign xram_inf.web = '0;
|
100
|
-
assign xram_inf.enb = 1'b1;
|
101
|
-
assign xram_inf.clkb = b_axis_zip.aclk;
|
102
|
-
assign xram_inf.rstb = ~b_axis_zip.aresetn;
|
103
|
-
|
104
|
-
assign a_rom_contect_inf.axis_tdata = a_rom_contect_inf_pre.axis_tdata[ a_rom_contect_inf.DSIZE-1:0];
|
105
|
-
assign a_rom_contect_inf.axis_tvalid = a_rom_contect_inf_pre.axis_tvalid;
|
106
|
-
assign a_rom_contect_inf.axis_tlast = a_rom_contect_inf_pre.axis_tlast;
|
107
|
-
assign a_rom_contect_inf_pre.axis_tready = a_rom_contect_inf.axis_tready;
|
108
|
-
assign b_rom_contect_inf.axis_tdata = b_rom_contect_inf_pre.axis_tdata[ b_rom_contect_inf.DSIZE-1:0];
|
109
|
-
assign b_rom_contect_inf.axis_tvalid = b_rom_contect_inf_pre.axis_tvalid;
|
110
|
-
assign b_rom_contect_inf.axis_tlast = b_rom_contect_inf_pre.axis_tlast;
|
111
|
-
assign b_rom_contect_inf_pre.axis_tready = b_rom_contect_inf.axis_tready;
|
112
|
-
|
113
|
-
endmodule
|
@@ -1,62 +0,0 @@
|
|
1
|
-
/**********************************************
|
2
|
-
_______________________________________
|
3
|
-
___________ Cook Darwin __________
|
4
|
-
_______________________________________
|
5
|
-
descript:
|
6
|
-
author : Cook.Darwin
|
7
|
-
Version: VERA.0.0
|
8
|
-
created: xxxx.xx.xx
|
9
|
-
madified:
|
10
|
-
***********************************************/
|
11
|
-
`timescale 1ns/1ps
|
12
|
-
|
13
|
-
module axis_split_channel_verb (
|
14
|
-
input [15:0] split_len,
|
15
|
-
axi_stream_inf.slaver origin_inf,
|
16
|
-
axi_stream_inf.master first_inf,
|
17
|
-
axi_stream_inf.master end_inf
|
18
|
-
);
|
19
|
-
|
20
|
-
//==========================================================================
|
21
|
-
//-------- define ----------------------------------------------------------
|
22
|
-
logic clock;
|
23
|
-
logic rst_n;
|
24
|
-
logic [16-1:0] insert_seed ;
|
25
|
-
logic [16-1:0] next_split_len ;
|
26
|
-
axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.USIZE(1)) origin_inf_insert (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
|
27
|
-
//==========================================================================
|
28
|
-
//-------- instance --------------------------------------------------------
|
29
|
-
axis_insert_copy axis_insert_copy_inst(
|
30
|
-
/* input */.insert_seed (insert_seed ),
|
31
|
-
/* input */.insert_len (8'd1 ),
|
32
|
-
/* axi_stream_inf.slaver */.in_inf (origin_inf ),
|
33
|
-
/* axi_stream_inf.master */.out_inf (origin_inf_insert )
|
34
|
-
);
|
35
|
-
common_fifo #(
|
36
|
-
.DEPTH (4 ),
|
37
|
-
.DSIZE (16 )
|
38
|
-
)common_fifo_head_bytesx_inst(
|
39
|
-
/* input */.clock (clock ),
|
40
|
-
/* input */.rst_n (rst_n ),
|
41
|
-
/* input */.wdata (split_len ),
|
42
|
-
/* input */.wr_en ((origin_inf.axis_tcnt == '0) && origin_inf.axis_tvalid && origin_inf.axis_tready ),
|
43
|
-
/* output */.rdata (next_split_len ),
|
44
|
-
/* input */.rd_en (origin_inf_insert.axis_tvalid && origin_inf_insert.axis_tready && origin_inf_insert.axis_tlast ),
|
45
|
-
/* output */.count (/*unused */ ),
|
46
|
-
/* output */.empty (/*unused */ ),
|
47
|
-
/* output */.full (/*unused */ )
|
48
|
-
);
|
49
|
-
axi_stream_split_channel axi_stream_split_channel_inst(
|
50
|
-
/* input */.split_len (next_split_len ),
|
51
|
-
/* axi_stream_inf.slaver */.origin_inf (origin_inf_insert ),
|
52
|
-
/* axi_stream_inf.master */.first_inf (first_inf ),
|
53
|
-
/* axi_stream_inf.master */.end_inf (end_inf )
|
54
|
-
);
|
55
|
-
//==========================================================================
|
56
|
-
//-------- expression ------------------------------------------------------
|
57
|
-
assign clock = origin_inf.aclk;
|
58
|
-
assign rst_n = origin_inf.aresetn;
|
59
|
-
|
60
|
-
assign insert_seed = ( split_len-1'b1);
|
61
|
-
|
62
|
-
endmodule
|