axi_tdl 0.0.15 → 0.0.19

data/lib/tdl/examples/11_test_unit/exp_test_unit.rb

@@ -22,17 +22,18 @@ TopModule.exp_test_unit(__dir__) do
     end
 
     ## CREATE TEST POINT
-    axis_data_inf.create_tp(' top test point',__FILE__,__LINE__)    - 'axis_data_inf'
+    # axis_data_inf.create_tp(' top test point',__FILE__,__LINE__)    - 'axis_data_inf'
+    axis_data_inf.tracked_by_dve
 
     TdlTestUnit.tu0(__dir__) do 
-        add_to_dve_wave TdlTestPoint.sub_md1.enable_tp
-        add_to_dve_wave(TdlTestPoint.sub_md0.tp_axis_in)
-        add_to_dve_wave(TdlTestPoint.sub_md1.tp_inter_tf)
+        # add_to_dve_wave TdlTestPoint.sub_md1.enable_tp
+        # add_to_dve_wave(TdlTestPoint.sub_md0.tp_axis_in)
+        # add_to_dve_wave(TdlTestPoint.sub_md1.tp_inter_tf)
     
         test_unit_init do 
-            TdlTestPoint.sub_md1.enable_tp.root_ref   <= 1.b1 
+            sub_md1.enable   <= 1.b1 
             initial_exec("#(1us)")
-            TdlTestPoint.sub_md1.enable_tp.root_ref   <= 1.b0 
+            sub_md1.enable   <= 1.b0 
             initial_exec("#(500us)")
         end
     
@@ -40,8 +41,8 @@ TopModule.exp_test_unit(__dir__) do
     
     TdlTestUnit.tu1(__dir__) do 
         # puts TdlTestPoint.sub_md0.tp_cnt.path_refs
-        add_to_dve_wave(TdlTestPoint.sub_md0.tp_cnt)
-        add_to_dve_wave(TdlTestPoint.sub_md1.tp_cnt)
+        # add_to_dve_wave(TdlTestPoint.sub_md0.tp_cnt)
+        # add_to_dve_wave(TdlTestPoint.sub_md1.tp_cnt)
     end
 
     add_test_unit('tu0','tu1')

data/lib/tdl/examples/11_test_unit/exp_test_unit.sv

@@ -5,7 +5,7 @@ _______________________________________
 descript:
 author : Cook.Darwin
 Version: VERA.0.0
-created: xxxx.xx.xx
+created: 2021-03-20 12:08:01 +0800
 madified:
 ***********************************************/
 `timescale 1ns/1ps

data/lib/tdl/examples/11_test_unit/modules/sub_md0.rb

@@ -17,7 +17,10 @@ TdlBuild.sub_md0(__dir__) do
     end
 
     ## CREATE TEST POINT
-    cnt.create_tp('count test point')   - 'tp_cnt'
-    axis_in.create_tp('test point of axis_in',__FILE__,__LINE__)    - 'tp_axis_in'
-    inter_tf.create_tp('inner test point',__FILE__,__LINE__)        - 'tp_inter_tf'
+    # cnt.create_tp('count test point')   - 'tp_cnt'
+    # axis_in.create_tp('test point of axis_in',__FILE__,__LINE__)    - 'tp_axis_in'
+    # inter_tf.create_tp('inner test point',__FILE__,__LINE__)        - 'tp_inter_tf'
+    cnt.tracked_by_dve(:logic)
+    axis_in.tracked_by_dve(:interface)
+    inter_tf.tracked_by_dve
 end

data/lib/tdl/examples/11_test_unit/modules/sub_md0.sv

@@ -5,7 +5,7 @@ _______________________________________
 descript:
 author : Cook.Darwin
 Version: VERA.0.0
-created: xxxx.xx.xx
+created: 2021-03-20 12:08:00 +0800
 madified:
 ***********************************************/
 `timescale 1ns/1ps
@@ -26,15 +26,15 @@ data_inf_c #(.DSIZE(8)) inter_tf (.clock(clock),.rst_n(rst_n)) ;
 
 //==========================================================================
 //-------- expression ------------------------------------------------------
-assign  clock = axis_in.aclk;
-assign  rst_n = axis_in.aresetn;
+assign clock = axis_in.aclk;
+assign rst_n = axis_in.aresetn;
 
 always_ff@(posedge clock,negedge rst_n) begin 
     if(~rst_n)begin
-         cnt <= '0;
+        cnt <= '0;
     end
     else begin
-         cnt <= ( cnt+1'b1);
+        cnt <= (cnt+1'b1);
     end
 end
 

data/lib/tdl/examples/11_test_unit/modules/sub_md1.rb

@@ -17,9 +17,14 @@ TdlBuild.sub_md1(__dir__) do
     end
 
     ## CREATE TEST POINT
-    cnt.create_tp('count test point',__FILE__,__LINE__)   - 'tp_cnt'
-    axis_out.create_tp('test point of axis_out',__FILE__,__LINE__)    - 'tp_axis_out'
-    inter_tf.create_tp('inner test point',__FILE__,__LINE__)        - 'tp_inter_tf'
-    enable.create_tp('enable driver',__FILE__,__LINE__) - 'enable_tp'
+    # cnt.create_tp('count test point',__FILE__,__LINE__)   - 'tp_cnt'
+    # axis_out.create_tp('test point of axis_out',__FILE__,__LINE__)    - 'tp_axis_out'
+    # inter_tf.create_tp('inner test point',__FILE__,__LINE__)        - 'tp_inter_tf'
+    # enable.create_tp('enable driver',__FILE__,__LINE__) - 'enable_tp'
+
+    cnt.tracked_by_dve
+    axis_out.tracked_by_dve
+    inter_tf.tracked_by_dve(:inner)
+    enable.tracked_by_dve
 
 end

data/lib/tdl/examples/11_test_unit/modules/sub_md1.sv

@@ -5,7 +5,7 @@ _______________________________________
 descript:
 author : Cook.Darwin
 Version: VERA.0.0
-created: xxxx.xx.xx
+created: 2021-03-20 12:08:00 +0800
 madified:
 ***********************************************/
 `timescale 1ns/1ps
@@ -26,15 +26,15 @@ data_inf_c #(.DSIZE(8)) inter_tf (.clock(clock),.rst_n(rst_n)) ;
 
 //==========================================================================
 //-------- expression ------------------------------------------------------
-assign  clock = axis_out.aclk;
-assign  rst_n = axis_out.aresetn;
+assign clock = axis_out.aclk;
+assign rst_n = axis_out.aresetn;
 
 always_ff@(posedge clock,negedge rst_n) begin 
     if(~rst_n)begin
-         cnt <= '0;
+        cnt <= '0;
     end
     else begin
-         cnt <= ( cnt+1'b1);
+        cnt <= (cnt+1'b1);
     end
 end
 

data/lib/tdl/examples/11_test_unit/tb_exp_test_unit.sv

@@ -5,11 +5,10 @@ _______________________________________
 descript:
 author : Cook.Darwin
 Version: VERA.0.0
-created: xxxx.xx.xx
+created: 2021-03-20 12:08:01 +0800
 madified:
 ***********************************************/
 `timescale 1ns/1ps
-`timescale 1ns/1ps
 
 module tb_exp_test_unit();
 //==========================================================================

data/lib/tdl/examples/11_test_unit/tu0.sv

@@ -5,7 +5,7 @@ _______________________________________
 descript:
 author : Cook.Darwin
 Version: VERA.0.0
-created: xxxx.xx.xx
+created: 2021-03-20 12:08:00 +0800
 madified:
 ***********************************************/
 `timescale 1ns/1ps
@@ -25,14 +25,14 @@ module tu0 (
 //==========================================================================
 //-------- expression ------------------------------------------------------
 initial begin
-     to_down_pass = 1'b0;
-     wait(from_up_pass);
-     $root.tb_exp_test_unit.test_unit_region = "tu0";
-     $root.tb_exp_test_unit.rtl_top.sub_md1_inst.enable = 1'b1;
-     #(1us);
-     $root.tb_exp_test_unit.rtl_top.sub_md1_inst.enable = 1'b0;
-     #(500us);
-     to_down_pass = 1'b1;
+    to_down_pass = 1'b0;
+    wait(from_up_pass);
+    $root.tb_exp_test_unit.test_unit_region = "tu0";
+    $root.tb_exp_test_unit.rtl_top.sub_md1_inst.enable = 1'b1;
+    #(1us);
+    $root.tb_exp_test_unit.rtl_top.sub_md1_inst.enable = 1'b0;
+    #(500us);
+    to_down_pass = 1'b1;
 end
 
 endmodule

data/lib/tdl/examples/11_test_unit/tu1.sv

@@ -5,7 +5,7 @@ _______________________________________
 descript:
 author : Cook.Darwin
 Version: VERA.0.0
-created: xxxx.xx.xx
+created: 2021-03-20 12:08:00 +0800
 madified:
 ***********************************************/
 `timescale 1ns/1ps

data/lib/tdl/examples/1_define_module/exmple_md.sv

@@ -14,13 +14,13 @@ module exmple_md #(
     parameter  DSIZE  = 8,
     parameter real MK = 1.1
 )(
-    input                    insdata,
-    output                   outsdata,
-    input [7:0]              inpdata,
-    output [15:0]            outpdata,
-    output logic[ DSIZE-1:0] ldata,
-    input                    clock,
-    input                    rst_n
+    input                   insdata,
+    output                  outsdata,
+    input [7:0]             inpdata,
+    output [15:0]           outpdata,
+    output logic[DSIZE-1:0] ldata,
+    input                   clock,
+    input                   rst_n
 );
 
 //==========================================================================
@@ -32,18 +32,18 @@ logic [6-1:0]  tmp_data[9-1:0][7-1:0] ;
 
 //==========================================================================
 //-------- expression ------------------------------------------------------
-assign  outsdata = insdata;
+assign outsdata = insdata;
 
 always_comb begin 
-     outpdata[8:0] = inpdata;
+    outpdata[8:0] = inpdata;
 end
 
-always_ff@(posedge clock,negedge rst_n) begin 
+always@(posedge clock,negedge rst_n) begin 
     if(~rst_n)begin
-         ldata <= '0;
+        ldata <= '0;
     end
     else begin
-         ldata[ DSIZE-1:0] <= ( outpdata[7:0]+insdata);
+        ldata[DSIZE-1:0] <= (outpdata[7:0]+insdata);
     end
 end
 

data/lib/tdl/examples/2_hdl_class/tmp/always_comb_test.sv

@@ -23,85 +23,85 @@ data_inf_c #(.DSIZE(18)) c_inf [2:0][6:0][7:0] (.clock(dclk),.rst_n(drstn)) ;
 //==========================================================================
 //-------- expression ------------------------------------------------------
 always_comb begin 
-     tmp1 = a_inf.data[ 6-1];
-     a_inf.valid = 1;
+    tmp1 = a_inf.data[6-1];
+    a_inf.valid = 1;
     if(0)begin
-         tmp1 = 90;
-         tmp1 = a_inf.data[ 6-1];
-         a_inf.valid = 1;
-         a_inf.data[6:3] = ( 12+( a_inf.data[6:0]+tmp1));
-         a_inf.data[6:3] = ( 12+( tmp1+a_inf.data[6:0]));
-         a_inf.data = ( 12+12);
-         "90"+"0";
+        tmp1 = 90;
+        tmp1 = a_inf.data[6-1];
+        a_inf.valid = 1;
+        a_inf.data[6:3] = 12+(a_inf.data[6:0]+tmp1);
+        a_inf.data[6:3] = 12+(tmp1+a_inf.data[6:0]);
+        a_inf.data = 12+12;
+        "90"+"0";
     end
     else if(1)begin
-         c_inf[0][0][1].valid = 1;
-         c_inf[0][0][1].data = 0;
-         c_inf[0][0][1].data[0] = 3;
-         c_inf[0][0][1].data[0] = 3<= 7;
-         c_inf.data[0][0][0] = 0;
+        c_inf[0][0][1].valid = 1;
+        c_inf[0][0][1].data = 0;
+        c_inf[0][0][1].data[0] = 3;
+        c_inf[0][0][1].data[0] = 3<=7;
+        c_inf.data[0][0][0] = 0;
     end
     else begin
-         c_inf[0][0][1].valid = 1;
-         c_inf[0][0][1].data = 0;
-         c_inf[0][0][1].data[0] = 3;
-         c_inf[0][0][1].data[0] = 3<= 7;
-         c_inf.data[0][0][0] = 0;
+        c_inf[0][0][1].valid = 1;
+        c_inf[0][0][1].data = 0;
+        c_inf[0][0][1].data[0] = 3;
+        c_inf[0][0][1].data[0] = 3<=7;
+        c_inf.data[0][0][0] = 0;
     end
 end
 
 always_comb begin 
-     tmp1 = a_inf.data[ 6-1];
-     a_inf.valid = 1;
+    tmp1 = a_inf.data[6-1];
+    a_inf.valid = 1;
     if(tmp1)begin
-         tmp1 = 90;
-         tmp1 = a_inf.data[ 6-1];
-         a_inf.valid = 1;
-         a_inf.data[6:3] = ( 12+( a_inf.data[6:0]+tmp1));
-         a_inf.data[6:3] = ( 12+( tmp1+a_inf.data[6:0]));
-         a_inf.data = ( 12+12);
-         "90"+"0";
+        tmp1 = 90;
+        tmp1 = a_inf.data[6-1];
+        a_inf.valid = 1;
+        a_inf.data[6:3] = 12+(a_inf.data[6:0]+tmp1);
+        a_inf.data[6:3] = 12+(tmp1+a_inf.data[6:0]);
+        a_inf.data = 12+12;
+        "90"+"0";
         if(9999)begin
-             a_inf.valid = 1;
-             a_inf.data[6:3] = ( 12+( a_inf.data[6:0]+tmp1));
-             a_inf.data[6:3] = ( 12+( tmp1+a_inf.data[6:0]));
-             a_inf.data = ( 12+12);
+            a_inf.valid = 1;
+            a_inf.data[6:3] = 12+(a_inf.data[6:0]+tmp1);
+            a_inf.data[6:3] = 12+(tmp1+a_inf.data[6:0]);
+            a_inf.data = 12+12;
         end
     end
-    else if( tmp1>1)begin
-         c_inf[0][0][1].valid = 1;
-         c_inf[0][0][1].data = 0;
-         c_inf[0][0][1].data[0] = 3;
-         c_inf[0][0][1].data[0] = 3<= 7;
-         c_inf.data[0][0][0] = 0;
+    else if(tmp1>1)begin
+        c_inf[0][0][1].valid = 1;
+        c_inf[0][0][1].data = 0;
+        c_inf[0][0][1].data[0] = 3;
+        c_inf[0][0][1].data[0] = 3<=7;
+        c_inf.data[0][0][0] = 0;
     end
     else if(~tmp1)begin
-         c_inf[0][0][1].valid = 1;
-         c_inf[0][0][1].data = 0;
-         c_inf[0][0][1].data[0] = 3;
-         c_inf[0][0][1].data[0] = 3<= 7;
-         c_inf.data[0][0][0] = 0;
+        c_inf[0][0][1].valid = 1;
+        c_inf[0][0][1].data = 0;
+        c_inf[0][0][1].data[0] = 3;
+        c_inf[0][0][1].data[0] = 3<=7;
+        c_inf.data[0][0][0] = 0;
     end
-    else if( tmp1>c_inf[0][0][1].data)begin
-         c_inf[0][0][1].valid = 1;
-         c_inf[0][0][1].data = 0;
-         c_inf[0][0][1].data[0] = 3;
-         c_inf[0][0][1].data[0] = 3<= 7;
-         c_inf.data[0][0][0] = 0;
+    else if(tmp1>c_inf[0][0][1].data)begin
+        c_inf[0][0][1].valid = 1;
+        c_inf[0][0][1].data = 0;
+        c_inf[0][0][1].data[0] = 3;
+        c_inf[0][0][1].data[0] = 3<=7;
+        c_inf.data[0][0][0] = 0;
     end
-    else if( c_inf[0][0][1].data+tmp0[0][0][0])begin
-         c_inf[0][0][1].valid = 1;
-         c_inf[0][0][1].data = 0;
-         c_inf[0][0][1].data[0] = 3;
-         c_inf[0][0][1].data[0] = 3<= 7;
-         c_inf.data[0][0][0] = 0;
+    else if(c_inf[0][0][1].data+tmp0[0][0][0])begin
+        c_inf[0][0][1].valid = 1;
+        c_inf[0][0][1].data = 0;
+        c_inf[0][0][1].data[0] = 3;
+        c_inf[0][0][1].data[0] = 3<=7;
+        c_inf.data[0][0][0] = 0;
     end
     else begin
-         c_inf[0][0][1].valid = 1;
-         c_inf[0][0][1].data = 0;
-         c_inf[0][0][1].data[0] = 3;
-         c_inf[0][0][1].data[0] = 3<= 7;
-         c_inf.data[0][0][0] = 0;
+        c_inf[0][0][1].valid = 1;
+        c_inf[0][0][1].data = 0;
+        c_inf[0][0][1].data[0] = 3;
+        c_inf[0][0][1].data[0] = 3<=7;
+        c_inf.data[0][0][0] = 0;
     end
 end
 

data/lib/tdl/examples/2_hdl_class/tmp/always_ff_test.sv

@@ -28,8 +28,8 @@ data_inf_c #(.DSIZE(8)) c_inf [2:0][6:0][7:0] (.clock(dclk),.rst_n(drstn)) ;
 
 //==========================================================================
 //-------- expression ------------------------------------------------------
-always_ff@(posedge clock,negedge rst_n) begin 
-     ( 32*2- 5)-6;
+always@(posedge clock,negedge rst_n) begin 
+    (32*2-5)-6;
 end
 
 endmodule

data/lib/tdl/examples/2_hdl_class/tmp/case_test.sv

@@ -28,38 +28,38 @@ data_inf_c #(.DSIZE(8)) c_inf [2:0][6:0][7:0] (.clock(dclk),.rst_n(drstn)) ;
 
 //==========================================================================
 //-------- expression ------------------------------------------------------
-always_ff@(posedge clock) begin 
+always@(posedge clock) begin 
     case(tmp0) 
         a_inf.data:begin 
             if(90)begin
-                 tmp1 <= 0;
+                tmp1 <= 0;
             end
             else begin
-                 tmp1 <= 1;
+                tmp1 <= 1;
             end
         end
         1,2:begin 
             if(90)begin
-                 tmp1 <= 0;
+                tmp1 <= 0;
             end
             else begin
-                 tmp1 <= 1;
+                tmp1 <= 1;
             end
         end
         c_inf[0][1][2].data,2:begin 
             if(c_inf[0][1][2].valid)begin
-                 tmp1 <= 0;
+                tmp1 <= 0;
             end
             else begin
-                 tmp1 <= 1;
+                tmp1 <= 1;
             end
         end
         default:begin 
             if(909)begin
-                 tmp1 <= 0;
+                tmp1 <= 0;
             end
             else begin
-                 tmp1 <= 1;
+                tmp1 <= 1;
             end
         end
     endcase
@@ -69,34 +69,34 @@ always_comb begin
     case(tmp0) 
         a_inf.data:begin 
             if(90)begin
-                 tmp1 = 0;
+                tmp1 = 0;
             end
             else begin
-                 tmp1 = 1;
+                tmp1 = 1;
             end
         end
         1,2:begin 
             if(90)begin
-                 tmp1 = 0;
+                tmp1 = 0;
             end
             else begin
-                 tmp1 = 1;
+                tmp1 = 1;
             end
         end
         c_inf[0][1][2].data,2:begin 
             if(c_inf[0][1][2].valid)begin
-                 tmp1 = 0;
+                tmp1 = 0;
             end
             else begin
-                 tmp1 = 1;
+                tmp1 = 1;
             end
         end
         default:begin 
             if(909)begin
-                 tmp1 = 0;
+                tmp1 = 0;
             end
             else begin
-                 tmp1 = 1;
+                tmp1 = 1;
             end
         end
     endcase