axi_tdl 0.0.15 → 0.0.19

data/lib/tdl/examples/2_hdl_class/tmp/head_pkg_module.sv

@@ -21,22 +21,22 @@ module head_pkg_module import test_package::*;(
 //-------- define ----------------------------------------------------------
 z_ing y0;
 z_ing curr_y0;
-logic [ $clog2( NUM*8)-1:0]  clog2_data ;
+logic [$clog2(NUM*8)-1:0]  clog2_data ;
 
 //==========================================================================
 //-------- instance --------------------------------------------------------
 
 //==========================================================================
 //-------- expression ------------------------------------------------------
-assign  out = NUM;
-assign  out = data;
-assign  struct_z_l[8].op[0] = 0;
+assign out = NUM;
+assign out = data;
+assign struct_z_l[8].op[0] = 0;
 
-assign  y0.op = 1'b0;
-assign  y0.op[0] = 1'd0;
-assign  y0.op[1] = struct_z.op[1];
-assign  y0.op[y0.op[3:1]] = struct_z.op;
+assign y0.op = 1'b0;
+assign y0.op[0] = 1'd0;
+assign y0.op[1] = struct_z.op[1];
+assign y0.op[y0.op[3:1]] = struct_z.op;
 
-assign  curr_y0 = struct_z;
+assign curr_y0 = struct_z;
 
 endmodule

data/lib/tdl/examples/2_hdl_class/tmp/simple_assign_test.sv

@@ -22,6 +22,6 @@ data_inf_c #(.DSIZE(8)) c_inf [2:0][6:0][7:0] (.clock(dclk),.rst_n(drstn)) ;
 
 //==========================================================================
 //-------- expression ------------------------------------------------------
-assign  tmp1 = ( tmp0[0]&"FALSE" && ( c_inf.data==3 ||  a_inf.valid|1'b0));
+assign tmp1 = tmp0[0]&"FALSE" &&(c_inf.data==3 ||a_inf.valid|1'b0);
 
 endmodule

data/lib/tdl/examples/2_hdl_class/tmp/state_case_test.sv

@@ -37,39 +37,39 @@ SE_STATE_ctrl_state CSTATE_ctrl_state,NSTATE_ctrl_state;
 always_comb begin 
     case(CSTATE_ctrl_state) 
         IDLE:begin 
-             NSTATE_ctrl_state = EXEC;
+            NSTATE_ctrl_state = EXEC;
         end
         EXEC:begin 
             if(90)begin
-                 NSTATE_ctrl_state = DONE;
+                NSTATE_ctrl_state = DONE;
             end
             else begin
-                 NSTATE_ctrl_state = EXEC;
+                NSTATE_ctrl_state = EXEC;
             end
         end
         DONE:begin 
-             NSTATE_ctrl_state = IDLE;
+            NSTATE_ctrl_state = IDLE;
         end
         default:begin 
-             NSTATE_ctrl_state = IDLE;
+            NSTATE_ctrl_state = IDLE;
         end
     endcase
 end
 
-always_ff@(posedge clock,negedge rst_n) begin 
+always@(posedge clock,negedge rst_n) begin 
     if(~rst_n)begin
-         a_inf.data <= '0;
+        a_inf.data <= '0;
     end
     else begin
         case(NSTATE_ctrl_state) 
             IDLE:begin 
-                 a_inf.data <= 8'd9;
+                a_inf.data <= 8'd9;
             end
             EXEC:begin 
-                 a_inf.data <= 8'h12;
+                a_inf.data <= 8'h12;
             end
             default:begin 
-                 a_inf.data <= ~('0);
+                a_inf.data <= ~('0);
             end
         endcase
     end

data/lib/tdl/examples/2_hdl_class/tmp/test_foreach.sv

@@ -24,9 +24,9 @@ logic [32-1:0]  data[32-1:0] ;
 //-------- expression ------------------------------------------------------
 always_comb begin 
     foreach(data[i1])begin
-         4-i1;
-        if( i1==( NUM* 4-i1))begin
-             data[i1] = '0;
+        4-i1;
+        if(i1==(NUM*4-i1))begin
+            data[i1] = '0;
         end
     end
 end

data/lib/tdl/examples/2_hdl_class/tmp/test_function.sv

@@ -30,23 +30,23 @@ typedef enum {
 SE_STATE_ctrl CSTATE_ctrl,NSTATE_ctrl;
 function status(input [7:0] code,output logic [15:0] pl); 
     if(89)begin
-         gp = code;
+        gp = code;
     end
 endfunction:status
 
 function logic status_xp(input [7:0] code,output logic [15:0] pl); 
-     status_xp = ( ( inm!=0)|( inm!=1));
+    status_xp = (inm!=0)|(inm!=1);
 endfunction:status_xp
 
 function SE_STATE_ctrl pre_status(input [7:0] code,output logic [15:0] pl,input SE_STATE_ctrl ll); 
     if(89)begin
-         gp = code;
-         pre_status = 0;
+        gp = code;
+        pre_status = 0;
     end
 endfunction:pre_status
 
-assign  gp = status(67, gp+1,opop);
-assign  gp = pre_status();
-assign  gp = ( ( inm!=0)|( inm!=1));
+assign gp = status(67,gp+1,opop);
+assign gp = pre_status();
+assign gp = (inm!=0)|(inm!=1);
 
 endmodule

data/lib/tdl/examples/2_hdl_class/tmp/test_initial_assert.sv

@@ -22,10 +22,10 @@ logic ppx;
 //-------- expression ------------------------------------------------------
 initial begin
     assert(9)else begin
-         $error("iiiiiiiiiiiii");
-         $stop;
+        $error("iiiiiiiiiiiii");
+        $stop;
     end
-     ppx = 1'b0;
+    ppx = 1'b0;
 end
 
 endmodule

data/lib/tdl/examples/2_hdl_class/tmp/test_module.sv

@@ -21,9 +21,9 @@ module test_module (
 //==========================================================================
 //-------- define ----------------------------------------------------------
 logic [axi_wr_inf.ASIZE-1:0]  addr ;
-logic [ axi_wr_inf.IDSIZE-4-1:0]  id ;
+logic [axi_wr_inf.IDSIZE-4-1:0]  id ;
 logic [24-1:0]  length ;
-axi_inf #(.DSIZE(axi_wr_inf.DSIZE),.IDSIZE( axi_wr_inf.IDSIZE-4),.ASIZE(axi_wr_inf.ASIZE),.LSIZE(24),.MODE("ONLY_WRITE"),.ADDR_STEP(8192)) pre_axi_wr_inf (.axi_aclk(axi_wr_inf.axi_aclk),.axi_aresetn(axi_wr_inf.axi_aresetn)) ;
+axi_inf #(.DSIZE(axi_wr_inf.DSIZE),.IDSIZE(axi_wr_inf.IDSIZE-4),.ASIZE(axi_wr_inf.ASIZE),.LSIZE(24),.MODE("ONLY_WRITE"),.ADDR_STEP(8192)) pre_axi_wr_inf (.axi_aclk(axi_wr_inf.axi_aclk),.axi_aresetn(axi_wr_inf.axi_aresetn)) ;
 //==========================================================================
 //-------- instance --------------------------------------------------------
 axi_stream_cache_35bit cache_inst(

data/lib/tdl/examples/2_hdl_class/tmp/test_module_var.sv

@@ -5,7 +5,7 @@ _______________________________________
 descript:
 author : Cook.Darwin
 Version: VERA.0.0
-created: xxxx.xx.xx
+created: 2021-03-20 13:20:54 +0800
 madified:
 ***********************************************/
 `timescale 1ns/1ps
@@ -19,7 +19,7 @@ module test_module_var #(
 
 //==========================================================================
 //-------- define ----------------------------------------------------------
-localparam  ASIZE  = 20;
+localparam  ASIZE  = 20   ;
 axi_stream_inf #(.DSIZE(8),.USIZE(1)) tmp_axis_inf (.aclk(clock),.aresetn(rst_n),.aclken(1'b1)) ;
 axi_stream_inf #(.DSIZE(8),.USIZE(1)) tmp_axis0_inf (.aclk(clock),.aresetn(rst_n),.aclken(1'b1)) ;
 axi_inf #(.DSIZE(32),.IDSIZE(2),.ASIZE(8),.LSIZE(9),.MODE("BOTH"),.ADDR_STEP(4294967295)) tmp_axi4_inf (.axi_aclk(clock),.axi_aresetn(rst_n)) ;

data/lib/tdl/examples/2_hdl_class/tmp/test_package.sv

@@ -5,13 +5,12 @@ _______________________________________
 descript:
 author : Cook.Darwin
 Version: VERA.0.0
-created: xxxx.xx.xx
+created: 2021-03-20 12:10:27 +0800
 madified:
 ***********************************************/
 
 
-package test_package;
-parameter  NUM = 6;
+module test_packageparameter  NUM = 6;();
 //==========================================================================
 //-------- define ----------------------------------------------------------
 typedef struct {
@@ -33,6 +32,6 @@ s_ing s_ing_v1;
 
 //==========================================================================
 //-------- expression ------------------------------------------------------
-assign  zing_v0.op[9] = 0;
+assign zing_v0.op[9] = 0;
 
-endpackage:test_package
+endmodule

data/lib/tdl/examples/2_hdl_class/tmp/test_package2.sv

@@ -27,10 +27,10 @@ z_ing y0;
 
 //==========================================================================
 //-------- expression ------------------------------------------------------
-assign  out = NUM;
-assign  out = data;
+assign out = NUM;
+assign out = data;
 
-assign  y0.op = 0;
-assign  y0.op[0] = 0;
+assign y0.op = 0;
+assign y0.op[0] = 0;
 
 endmodule

data/lib/tdl/examples/2_hdl_class/tmp/test_struct_function.sv

@@ -37,8 +37,8 @@ s_map s_map_a1;
 //==========================================================================
 //-------- expression ------------------------------------------------------
 function s_map f_g(input s_map fin); 
-     f_g = fin.op;
-     f_g.yp = 1;
+    f_g = fin.op;
+    f_g.yp = 1;
 endfunction:f_g
 
 endmodule

data/lib/tdl/examples/2_hdl_class/tmp/test_vcs_string.sv

@@ -5,7 +5,7 @@ _______________________________________
 descript:
 author : Cook.Darwin
 Version: VERA.0.0
-created: xxxx.xx.xx
+created: 2021-03-20 13:24:07 +0800
 madified:
 ***********************************************/
 `timescale 1ns/1ps

data/lib/tdl/examples/2_hdl_class/tmp/text_generate.sv

@@ -15,10 +15,10 @@ module text_generate #(
     parameter  BOARD_TOTAL = 4,
     parameter  WW          = "OFF"
 )(
-    input [ NUM-1:0]        ip_s_addr          [32-1:0],
-    input [ NUM-1:0]        ip_d_addr          [32-1:0],
-    input [ NUM-1:0]        mac_s_addr         [48-1:0],
-    input [ NUM-1:0]        mac_d_addr         [48-1:0],
+    input [NUM-1:0]         ip_s_addr          [32-1:0],
+    input [NUM-1:0]         ip_d_addr          [32-1:0],
+    input [NUM-1:0]         mac_s_addr         [48-1:0],
+    input [NUM-1:0]         mac_d_addr         [48-1:0],
     input [15:0]            fpga_udp_ctrl_port,
     input [15:0]            fpga_udp_data_port,
     input [15:0]            fpga_udp_dire_port,
@@ -43,12 +43,12 @@ for(genvar KK0=0;KK0 < NUM;KK0++)begin
     for(genvar KK1=0;KK1 < 7;KK1++)begin
         for(genvar KK2=0;KK2 < 6;KK2++)begin
 
-            if( KK0==2)begin
-                assign  rx_udp_data_8bit[ 8*1][ 1*2] = "90909";
+            if(KK0==2)begin
+                assign rx_udp_data_8bit[8*1][1*2] = "90909";
             end end
     end
 end
 endgenerate
-assign  mac_s_addr[0][0] = mac_d_addr[0][0];
+assign mac_s_addr[0][0] = mac_d_addr[0][0];
 
 endmodule

data/lib/tdl/examples/4_generate/test_generate.sv

@@ -13,12 +13,12 @@ madified:
 module test_generate #(
     parameter  NUM = 8
 )(
-    input [7:0]       ain,
-    output [7:0]      bout,
-    input [5:0]       cin  [NUM-1:0],
-    output [ NUM-1:0] dout [6-1:0],
-    input [ NUM-1:0]  ein,
-    output [ NUM-1:0] fout
+    input [7:0]      ain,
+    output [7:0]     bout,
+    input [5:0]      cin  [NUM-1:0],
+    output [NUM-1:0] dout [6-1:0],
+    input [NUM-1:0]  ein,
+    output [NUM-1:0] fout
 );
 
 //==========================================================================
@@ -32,18 +32,18 @@ module test_generate #(
 //-------- expression ------------------------------------------------------
 generate
 for(genvar KK0=0;KK0 < 8;KK0++)begin
-    assign  bout[ KK0] = ain[ 7-( KK0)];
+    assign bout[KK0] = ain[7-(KK0)];
 end
 endgenerate
 
 generate
 for(genvar KK0=0;KK0 < NUM;KK0++)begin
 
-    if( KK0<4)begin
-        assign  dout[ KK0] = cin[ KK0];
+    if(KK0<4)begin
+        assign dout[KK0] = cin[KK0];
     end 
     else begin
-        assign  dout[ KK0] = ( cin[ KK0]+( KK0));
+        assign dout[KK0] = cin[KK0]+(KK0);
     end
 end
 endgenerate
@@ -51,7 +51,7 @@ endgenerate
 generate
 for(genvar KK0=0;KK0 < NUM;KK0++)begin
     for(genvar KK1=0;KK1 < 6;KK1++)begin
-        assign  fout[ KK0][ KK1] = ein[ KK1][ KK0];
+        assign fout[KK0][KK1] = ein[KK1][KK0];
     end
 end
 endgenerate

data/lib/tdl/examples/5_logic_combin/test_logic_combin.sv

@@ -29,8 +29,8 @@ logic [16-1:0]  cc[2-1:0] ;
 
 //==========================================================================
 //-------- expression ------------------------------------------------------
-assign  ca = {a0,a1,a2};
-assign  cb = {>>{b1,b0}};
-assign  cc = {<<{c0,c1}};
+assign ca = {a0,a1,a2};
+assign cb = {>>{b1,b0}};
+assign cc = {<<{c0,c1}};
 
 endmodule

data/lib/tdl/examples/7_module_with_package/body_package.sv

@@ -5,13 +5,12 @@ _______________________________________
 descript:
 author : Cook.Darwin
 Version: VERA.0.0
-created: xxxx.xx.xx
+created: 2021-03-20 12:10:27 +0800
 madified:
 ***********************************************/
 
 
-package body_package;
-parameter  BDSIZE = 10;
+module body_packageparameter  BDSIZE = 10;();
 //==========================================================================
 //-------- define ----------------------------------------------------------
 
@@ -22,4 +21,4 @@ parameter  BDSIZE = 10;
 //==========================================================================
 //-------- expression ------------------------------------------------------
 
-endpackage:body_package
+endmodule

data/lib/tdl/examples/7_module_with_package/example_pkg.sv

@@ -11,8 +11,8 @@ madified:
 `timescale 1ns/1ps
 
 module example_pkg import head_package::*;(
-    input [ HDSIZE-1:0] indata,
-    output logic[31:0]  odata
+    input [HDSIZE-1:0] indata,
+    output logic[31:0] odata
 );
 
 //------>> EX CODE <<-------------------
@@ -29,7 +29,7 @@ s_head ss_head;
 
 //==========================================================================
 //-------- expression ------------------------------------------------------
-assign  ss_head.idata = 4;
-assign  ss_head.valid = 1'b1;
+assign ss_head.idata = 4;
+assign ss_head.valid = 1'b1;
 
 endmodule

data/lib/tdl/examples/7_module_with_package/head_package.sv

@@ -5,13 +5,12 @@ _______________________________________
 descript:
 author : Cook.Darwin
 Version: VERA.0.0
-created: xxxx.xx.xx
+created: 2021-03-20 12:10:27 +0800
 madified:
 ***********************************************/
 
 
-package head_package;
-parameter  HDSIZE = 8;
+module head_packageparameter  HDSIZE = 8;();
 //==========================================================================
 //-------- define ----------------------------------------------------------
 typedef struct {
@@ -26,4 +25,4 @@ logic valid;
 //==========================================================================
 //-------- expression ------------------------------------------------------
 
-endpackage:head_package
+endmodule

data/lib/tdl/examples/8_top_module/tb_test_top.sv

@@ -5,7 +5,7 @@ _______________________________________
 descript:
 author : Cook.Darwin
 Version: VERA.0.0
-created: xxxx.xx.xx
+created: 2021-03-20 12:10:27 +0800
 madified:
 ***********************************************/
 `timescale 1ns/1ps

data/lib/tdl/examples/9_itegration/tb_test_tttop.sv

@@ -5,12 +5,10 @@ _______________________________________
 descript:
 author : Cook.Darwin
 Version: VERA.0.0
-created: xxxx.xx.xx
+created: 2021-03-20 12:10:28 +0800
 madified:
 ***********************************************/
 `timescale 1ns/1ps
-`timescale 1ns/1ps
-`timescale 1ns/1ps
 
 module tb_test_tttop();
 //==========================================================================
@@ -25,7 +23,7 @@ test_tttop rtl_top(
 //==========================================================================
 //-------- expression ------------------------------------------------------
 initial begin
-     forever begin #(33ns);gl_clk = ~gl_clk;end;
+    forever begin #(33ns);gl_clk = ~gl_clk;end;
 end
 
 endmodule

data/lib/tdl/examples/9_itegration/test_tttop.sv

@@ -33,8 +33,8 @@ a_test_md a_test_md_inst(
 );
 //==========================================================================
 //-------- expression ------------------------------------------------------
-assign  x_origin_inf.axis_tvalid = 1'b0;
-assign  x_origin_inf.axis_tdata = '0;
-assign  x_origin_inf.axis_tlast = 1'b0;
+assign x_origin_inf.axis_tvalid = 1'b0;
+assign x_origin_inf.axis_tdata = '0;
+assign x_origin_inf.axis_tlast = 1'b0;
 
 endmodule