axi_tdl 0.0.15 → 0.0.19

data/lib/tdl/rebuild_ele/ele_base.rb

@@ -537,7 +537,7 @@ module TdlSpace
 end
 
 module TdlSpace
-    class TdlBaseInterface
+    class TdlBaseInterface < AxiTdl::SdlModuleActiveBaseElm
         extend VarElemenAttr
         include VarElemenCore
 

data/lib/tdl/sdlmodule/sdlmodlule_path_db.rb

@@ -0,0 +1,34 @@
+require 'sqlite3'
+module AxiTdl
+
+    module SdlmodulePathDB 
+        DB_PATH = File.join(__dir__, "../auto_script/tmp/sdlmodule_path_map.db" )
+        TARGET = SQLite3::Database.new DB_PATH
+
+        def self.ceate_sdlmoule_path_table
+
+            tabel = nil
+            TARGET.execute("SELECT count(*) FROM sqlite_master WHERE type='table' AND name='sdlmoule_mtime_path';") do |row|
+                tabel_exist = row 
+                break
+            end
+
+            # Create a table
+            unless table 
+                rows = TARGET.execute <<-SQL
+                    create table sdlmoule_mtime_path (
+                        name varchar(128),
+                        path varchar(1024),
+                        grade varchar(5),
+                        blog varchar(50)
+                    );
+                SQL
+            end
+
+            
+        end
+
+
+    end
+
+end

data/lib/tdl/sdlmodule/sdlmodule.rb

@@ -116,6 +116,7 @@ class SdlModule
     attr_accessor :dont_gen_sv,:target_class
     ## 模块头部添加package引入
     attr_accessor :head_import_packages
+    attr_accessor :instanced_and_parent_module
 
     def initialize(name: "tdlmodule",out_sv_path: nil)
         # $new_m = self
@@ -341,23 +342,26 @@ class SdlModule
     ## 例化模块
 
     def method_missing(method,*args,&block)
+        rel = nil
+        ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do 
+            @@_method_missing_sub_methds ||= []
+
+            @@_method_missing_sub_methds.each do |me|
+                rel = self.send(me,method,*args,&block)
+                if rel 
+                    rel 
+                end
+            end
 
-        @@_method_missing_sub_methds ||= []
-
-        @@_method_missing_sub_methds.each do |me|
-            rel = self.send(me,method,*args,&block)
+            ## 最后才调用阴性例化模块
+            rel = implicit_inst_module_method_missing(method,*args,&block)
             if rel 
-                return rel 
+                rel
+            else
+                super
             end
         end
-
-        ## 最后才调用阴性例化模块
-        rel = implicit_inst_module_method_missing(method,*args,&block)
-        if rel 
-            return rel
-        else
-            super
-        end
+        return rel
     end
 end
 
@@ -468,4 +472,4 @@ class SdlModule
             puts (fstr % [_indexs[xi], _names[xi], _paths[xi]])
         end
     end
-end
+end

data/lib/tdl/sdlmodule/sdlmodule_draw.rb

@@ -51,28 +51,34 @@ class SdlModule
         return if (@origin_sv || @dont_gen_sv)
         pre_inst_stack_call
         @out_sv_path ||= '..\..\tdl\test_sdlmodule'
-        # unless GlobalParam.sim
+        if File.exist?(File.join(@out_sv_path,"#{module_name}.sv")) 
+            old_str = File.open(File.join(@out_sv_path,"#{module_name}.sv")).read.gsub(/\/\*.*?\*\//m,"").gsub(/\/\/.*/,"").sub(/^`timescale .*/,"").strip
+        
+
+            head_str,body_str = build_module_verb(ex_param:ex_param,ex_port:ex_port,ex_up_code:ex_up_code,ex_down_code:ex_down_code)
+            new_str = head_str+body_str
+            if body_str.gsub(/\/\*.*?\*\//m,"").gsub(/\/\/.*/,"").strip != old_str
+                File.open(File.join(@out_sv_path,"#{module_name}.sv"),"w") do |f|
+                    f.print new_str
+                end
+            end 
+        else
             File.open(File.join(@out_sv_path,"#{module_name}.sv"),"w") do |f|
-                f.puts build_module(ex_param:ex_param,ex_port:ex_port,ex_up_code:ex_up_code,ex_down_code:ex_down_code)
+                f.print build_module(ex_param:ex_param,ex_port:ex_port,ex_up_code:ex_up_code,ex_down_code:ex_down_code)
             end
-        # else
-        #     Tdl.Puts "+INFO+ It generate SIM top File"
-        #     File.open(File.join(out_sv_path,"#{module_name}_sim.sv"),"w") do |f|
-        #         f.puts build_module(ex_param:ex_param,ex_port:ex_port,ex_up_code:ex_up_code,ex_down_code:ex_down_code)
-        #     end
-        # end
+        end 
     end
 
-    def gen_sv_module_text
-        # @out_sv_path ||= File.dirname(File.expand_path(__FILE__))
-        return if (@origin_sv || @dont_gen_sv)
-        pre_inst_stack_call
-        @out_sv_path ||= '..\..\tdl\test_sdlmodule'
-        # unless GlobalParam.sim
+    # def gen_sv_module_text
+    #     # @out_sv_path ||= File.dirname(File.expand_path(__FILE__))
+    #     return if (@origin_sv || @dont_gen_sv)
+    #     pre_inst_stack_call
+    #     @out_sv_path ||= '..\..\tdl\test_sdlmodule'
+    #     # unless GlobalParam.sim
 
-        return build_module(ex_param:ex_param,ex_port:ex_port,ex_up_code:ex_up_code,ex_down_code:ex_down_code)
+    #     return build_module(ex_param:ex_param,ex_port:ex_port,ex_up_code:ex_up_code,ex_down_code:ex_down_code)
 
-    end
+    # end
 
     def build_module(ex_param:"",ex_port:"",ex_up_code:"",ex_down_code:"")
         # Tdl.Puts pagination(module_name)
@@ -124,6 +130,58 @@ class SdlModule
         return str
     end
 
+    def build_module_verb(ex_param:"",ex_port:"",ex_up_code:"",ex_down_code:"") #return [ head, body]
+        # Tdl.Puts pagination(module_name)
+        Tdl.Build_SdlModule_Puts(module_name)
+
+        ex_param        = ex_param.to_s     unless ex_param
+        ex_port         = ex_port.to_s      unless ex_port
+        ex_up_code      = ex_up_code.to_s   unless ex_up_code
+        ex_down_code    = ex_down_code.to_s unless ex_down_code
+
+        # gen_auto_method     # auto generate class method for interface
+        # draw = Tdl.inst + Tdl.draw
+
+        instance_draw_str = instance_draw       # It must run before vars_define_inst,because some signals define when inst
+        vars_exec_inst_str = vars_exec_inst     # It must run before vars_define_inst,because some signals define when vars exec
+
+        post_str = post_inst_stack_call()
+
+        unless post_str.strip.empty?
+            post_str = pagination("ROOT REF") + post_str
+        end
+
+        draw = pagination("define") + vars_define_inst + pagination("instance") + instance_draw_str + pagination("expression") + vars_exec_inst_str + post_str
+
+        unless ex_up_code.empty?
+            ex_up_code = "\n//------>> EX CODE <<-------------------\n" + ex_up_code + "//------<< EX CODE >>-------------------\n"
+        end
+
+        unless ex_down_code.empty?
+            ex_down_code = "//------>> EX CODE <<-------------------\n" + ex_down_code + "//------<< EX CODE >>-------------------\n"
+        end
+
+        # str = module_head+"module #{@module_name}" + build_params(ex_param) + build_ports(ex_port) + ex_up_code + gen_lite_str() + draw + ex_down_code + "\nendmodule\n"
+        # unless GlobalParam.sim
+            module_name_str = @module_name
+        # else
+        #     module_name_str = @module_name+"_sim"
+        # end
+        unless head_import_packages
+            str = "module #{module_name_str}" + build_params(ex_param) + build_ports(ex_port) + ex_up_code + draw + ex_down_code + "\nendmodule\n" + add_sub_module_file_paths
+        else
+            head_import_pkgs_str = head_import_packages.map{|e| "import #{e}::*;" }.join('')
+            str = "module #{module_name_str} #{head_import_pkgs_str}" + build_params(ex_param) + build_ports(ex_port) + ex_up_code + draw + ex_down_code + "\nendmodule\n" + add_sub_module_file_paths
+        end
+
+        create_vivado_tcl if @create_tcl
+        create_constraints_file if @create_sdc
+
+        # return str
+        return [module_head_verb, str]
+    end
+
+
     private
 
     def old_module_head
@@ -149,6 +207,13 @@ madified:
 }
     end
 
+    def module_head_verb
+%Q{#{$__sdlmodule_head_logo__.sub(/created:.*/, "created: #{Time.now()}")}
+#{macro_def}
+#{head_class}
+}
+            end
+
     def head_class
         case(@target_class.to_s)
         when "AxiStream"

data/lib/tdl/sdlmodule/test_unit_module.rb

@@ -1,9 +1,208 @@
-class TestUnitModule < SdlModule 
-    attr_accessor :dve_wave_signals
+class SdlModule
+    # attr_accessor :dve_wave_signals
+
+    def tracked_by_dve(flag:nil, &filter_block) ## 被dve track
+        @@__tracked_by_dve_hash__ ||= Hash.new
+        # if @@__tracked_by_dve_hash__.has_key?(self)
+        #     raise TdlError.new(" `#{module_name}` Cant be tracked again!!!")
+        # end
+        @@__tracked_by_dve_hash__[self] = filter_block
+        @__track_filter_block__ = filter_block
+        @__dve_track_flag__ = flag
+    end
+
+    def self.tracked_by_dve ## 收集添加有 dve track 的模块
+        @@__tracked_by_dve_hash__ ||= Hash.new ## key:sdlmodule, value:filter_block
+    end
+    
+    def add_to_dve_wave(flag: :default,base_ele: nil,&block)
+        @__track_signals_hash__ ||=Hash.new 
+        @__track_signals_hash__[flag] ||= Hash.new
+
+        if @__track_signals_hash__[flag].has_key?(base_ele)
+            raise TdlError.new(" `#{module_name}.#{base_ele.to_s}` Cant be tracked again!!!")
+        end
+
+        @__track_signals_hash__[flag][base_ele] = block
+
+        unless base_ele.is_a?(AxiTdl::SdlModuleActiveBaseElm)
+            raise TdlError.new(" `#{base_ele.to_s}<class #{base_ele.class}>` is not AxiTdl::SdlModuleActiveBaseElm !!! ")
+        end
+    end
+
+    def track_signals_hash
+        @__track_signals_hash__ ||=Hash.new
+
+        unless @__dve_track_flag__
+            @__track_signals_hash__
+        else 
+            rel = {}
+            rel[@__dve_track_flag__] = @__track_signals_hash__[@__dve_track_flag__]
+            rel
+        end
+    end
+
+    def gen_dev_wave_tcl ## 返回一个[]
+        dve_tcl_hash = {}
+        track_signals_hash.each do |flag, base_ele_bhash|
+            base_elms = []
+            intf_elms = []
+            intf_elms_name = []
+            base_ele_bhash.each do |ele, sub_filter_block|
+                _ref_paths = ele.path_refs(&@__track_filter_block__)
+
+                if sub_filter_block
+                    _ref_paths = _ref_paths.select do |e| 
+                        sub_filter_block.call(e) 
+                    end 
+                end 
+
+                if _ref_paths.size == 1
+                    # rels[0]
+                elsif _ref_paths.size == 0
+                    raise TdlError.new "#{ele.to_s} Cant find root ref"
+                else
+                    raise TdlError.new "#{ele.to_s} Find multi root refs \n#{_ref_paths.join("\n")}\n"
+                end
+
+
+                if ele.is_a?(BaseElm) || ele.is_a?(ClassHDL::EnumStruct) || ele.is_a?(ClassHDL::StructVar)
+                    base_elms   << _ref_paths[0].sub("$root.","Sim:") 
+                elsif ele.is_a? TdlSpace::TdlBaseInterface
+                    if ele.modport_type
+                        base_elms   << _ref_paths[0].sub("$root.","Sim:")  
+                    else
+                        intf_elms   << _ref_paths[0].sub("$root.","Sim:") 
+                        intf_elms_name << ele.inst_name
+                    end
+                end
+
+                
+            end
+
+            dve_tcl_hash[flag] = [base_elms, intf_elms,intf_elms_name]
+
+        end
+
+        add_ss = []
+        add_list = []
+        add_bar = []
+        dve_tcl_hash.each do |flag, ary|
+            add_ss  << TdlSpace.dev_signals_to_tcl(flag: "#{module_name}_#{flag}", signals: ary[0] )
+
+            add_list << TdlSpace.gui_list_add_group(flag: "Group2_#{module_name}_#{flag}")
+
+            ary[1].each_index do |index|
+                add_ss << TdlSpace.dev_interface_to_tcl(flag: "#{module_name}_#{flag}", iname: ary[2][index] ,signals: [ ary[1][index] ])
+                add_list <<  TdlSpace.gui_list_add_group(flag: "#{module_name}_#{flag}|#{ary[2][index]}")
+            end
+
+            add_bar  << TdlSpace.gui_list_set_insertion_bar(flag: "#{module_name}_#{flag}")
+        end
+
+        # TdlSpace.dve_tcl_temp(add_ss.join("\n"), add_list.join("\n"), add_bar.join("\n") )
+
+        return [add_ss.join("\n"), add_list.join("\n"), add_bar.join("\n")]
+
+    end
+
+    def self.gen_dev_wave_tcl(filepath=nil)
+        ctcl_ss,ctcl_list,ctcl_bar = [],[],[]
+        self.tracked_by_dve.each do |sdlm,filter_block|
+            tcl_ss,tcl_list,tcl_bar = sdlm.gen_dev_wave_tcl
+
+            ctcl_ss << tcl_ss
+            ctcl_list << tcl_list
+            ctcl_bar << tcl_bar
+        end
+
+        rel = TdlSpace.dve_tcl_temp(ctcl_ss.join("\n"), ctcl_list.join("\n"), ctcl_bar.join("\n") )
+        if filepath 
+            File.open(filepath,'w') do |f|
+                f.puts rel 
+            end
+        end
+        rel
+    end
+
+    
+
+    def self.echo_tracked_by_dve 
+        # Flag module root_path
+        # rels = {}
+        flags = []
+        _modules = []
+        _root_path = []
+        _signals = []
+        _max_name = 'module_name'.size
+        _max_flag = 'FLAG'.size
+        _max_signal = 'SIGNAL'.size
+        self.tracked_by_dve.each do |sdlm, filter_block|
+            __track_signals_hash__ = sdlm.track_signals_hash || Hash.new 
+            __track_signals_hash__.each do |flag, sub_hash|
+
+                sub_hash.each do |ele, sub_filter_block|
+                    _root_refs = ele.path_refs(&filter_block)
+                    if sub_filter_block 
+                        _root_refs.select! do |e| sub_filter_block.call(e) end
+                    end    
+
+                    if _root_refs.size == 1
+                        # rels[0]
+                    elsif _root_refs.size == 0
+                        raise TdlError.new "#{ele.to_s} Cant find root ref"
+                    else
+                        raise TdlError.new "#{ele.to_s} Find multi root refs \n#{_root_refs.join("\n")}\n"
+                    end
+
+                    flags << flag.to_s 
+                    _modules << sdlm.module_name
+                    if sdlm.module_name.size > _max_name
+                        _max_name = sdlm.module_name.size
+                    end
+                    if flag.to_s.size > _max_flag
+                        _max_flag   = flag.to_s.size 
+                    end
+                    # _root_path << _root_refs[0]
+                    _root_path << File.expand_path(ele.belong_to_module.real_sv_path)
+
+                    _signals << ele.to_s
+                    if ele.to_s.size > _max_signal 
+                        _max_signal = ele.to_s.size 
+                    end
+                end
+            end
+        end
+        
+        collect = ["[%s]    %-#{_max_flag}s    %#{_max_name+4}s  %-#{_max_signal}s    %s" % ['index', 'FLAG', 'MODULE-NAME', 'SIGNAL', 'belong_to_module']]
+        flags.each_index do |index|
+           collect << "[%5d]    %-#{_max_flag}s    %#{_max_name+4}s  %-#{_max_signal}s    %s" % [index+1, flags[index], _modules[index], _signals[index], _root_path[index]]
+        end
+
+        collect.join("\n")
+    end
+end
+
+module AxiTdl 
+    module TestUnitTrack # included AxiTdl::SdlModuleActiveBaseElm
+        def tracked_by_dve(flag= :default,&filter_block)
+            self.belong_to_module.tracked_by_dve
+            self.belong_to_module.add_to_dve_wave(flag: flag, base_ele: self, &filter_block)
+        end
+    end
+end
+
+module AxiTdl 
+    class SdlModuleActiveBaseElm
+        include AxiTdl::TestUnitTrack
+    end
+end
+
+class TestUnitModule < SdlModule ##TestUnitModule 是在编译完 TopModule TB后才会运行
 
     def initialize(name: "tdlmodule",out_sv_path: nil)
         super(name: name,out_sv_path: out_sv_path)
-        @dve_wave_signals = []
+        # @dve_wave_signals = []
     end
 
     def test_unit_init(&block)
@@ -11,21 +210,77 @@ class TestUnitModule < SdlModule
             to_down_pass    <= 1.b0
             initial_exec("wait(from_up_pass)")
             initial_exec("$root.#{TopModule.current.techbench.module_name}.test_unit_region = \"#{module_name}\"")
-            block.call 
+            block.call ## collect __root_ref_eles__ at here
             to_down_pass    <= 1.b1
         end
     end
 
-    def add_to_dve_wave(tp,&block)
-        # @dve_wave_signals ||= []
-        # tps.each do |e|
-        #     # dve_wave_signals << e.root_ref.sub("$root.","Sim:")
-        #     @dve_wave_signals << e
-        # end
-        # 
-        @dve_wave_signals << tp
-        tp.tp_instance.filter_block = block if block_given?
-        @dve_wave_signals
+    def add_root_ref_ele(*eles)
+        @__root_ref_eles__ ||= []
+        @__root_ref_eles__ += eles
+        @__root_ref_eles__.uniq!
+    end
+
+    def root_ref_eles 
+        @__root_ref_eles__ || []
+    end
+
+    def be_instanced_by_sim
+        @@__be_instanced_by_sim__ ||= []
+        @@__be_instanced_by_sim__ << self
+    end
+
+    def self.be_instanced_by_sim
+        @@__be_instanced_by_sim__ || []
+    end
+
+    def self.echo_be_instanced_by_sim
+        @@__be_instanced_by_sim__ ||= []
+
+        _module_name = []
+        _ref_module_name = []
+        _signal_name = []
+        _ref_module_path = []
+
+        _max_module_name = 'test_module'.size 
+        _max_signal_name = 'SIGNAL'.size 
+        _max_ref = 'REF_MODULE'.size
+        @@__be_instanced_by_sim__.each do |tm|
+            __root_ref_eles__ = tm.root_ref_eles
+
+            __root_ref_eles__.each do |ele|
+                _module_name << tm.module_name
+                _ref_module_name << ele.belong_to_module.module_name
+                _signal_name << ele.to_s 
+                _ref_module_path << File.expand_path(ele.belong_to_module.real_sv_path)
+
+                if tm.module_name.size > _max_module_name
+                    _max_module_name    = tm.module_name.size 
+                end 
+
+                if ele.belong_to_module.module_name.size > _max_ref
+                    _max_ref  = ele.belong_to_module.module_name.size 
+                end 
+
+                if ele.to_s.size > _max_signal_name
+                    _max_signal_name = ele.to_s.size 
+                end
+            end
+        end
+
+        collect = ["[%5s]    %-#{_max_module_name}s    %#{_max_ref}s  %-#{_max_signal_name}s    %s" % ['index', 'TEST-MODULE','REF-MODULE','SIGNAL', 'REF-MODULE-PATH'] ] 
+
+        _module_name.each_index do |index|
+            collect << "[%5d]    %-#{_max_module_name}s    %#{_max_ref}s  %-#{_max_signal_name}s    %s" % [index+1, _module_name[index], _ref_module_name[index], _signal_name[index], _ref_module_path[index]]
+        end
+
+        collect.join("\n")
+    end
+
+
+    def self.gen_dve_tcl(filepath)
+
+
     end
 end
 
@@ -56,23 +311,6 @@ class TdlTestUnit < TdlBuild
         sdlm
     end
 
-    # def self.collect_unit(tu)
-    #     @@__collect_units__ ||= []
-    #     @@__collect_units__ << tu 
-    # end
-
-    # def self.echo_units
-    #     @@__collect_units__ ||= []
-    #     index = 1
-
-    #     rels = []
-    #     @@__collect_units__.each do |ue|
-    #         rels << "  [#{index}]  #{ue.origin.module_name}"
-    #         index += 1
-    #     end
-    #     rels.join("\n")
-    # end
-
 end
 
 class TopModule
@@ -109,11 +347,12 @@ class TopModule
                     h.output.logic.to_down_pass     (nqq ? unit_pass_d : unit_pass_d[index])
                 end
 
+                tu_inst.origin.be_instanced_by_sim
                 # TdlTestUnit.collect_unit tu_inst
-                TopModule.current.test_unit.collect_unit tu_inst
+                # TopModule.current.test_unit.collect_unit tu_inst
 
                 ## 添加dve wave 信号
-                TopModule.current.test_unit.dve_wave(name: _inst_name_, signals: tu_inst.origin.dve_wave_signals )
+                # TopModule.current.test_unit.dve_wave(name: _inst_name_, signals: tu_inst.origin.dve_wave_signals )
 
                 if index == 0
                     Assign do