axi_tdl 0.0.10 → 0.1.0

data/lib/tdl/examples/2_hdl_class/tmp/test_foreach.sv

@@ -24,9 +24,9 @@ logic [32-1:0]  data[32-1:0] ;
 //-------- expression ------------------------------------------------------
 always_comb begin 
     foreach(data[i1])begin
-         4-i1;
-        if( i1==( NUM* 4-i1))begin
-             data[i1] = '0;
+        4-i1;
+        if(i1==(NUM*4-i1))begin
+            data[i1] = '0;
         end
     end
 end

data/lib/tdl/examples/2_hdl_class/tmp/test_function.sv

@@ -30,23 +30,23 @@ typedef enum {
 SE_STATE_ctrl CSTATE_ctrl,NSTATE_ctrl;
 function status(input [7:0] code,output logic [15:0] pl); 
     if(89)begin
-         gp = code;
+        gp = code;
     end
 endfunction:status
 
 function logic status_xp(input [7:0] code,output logic [15:0] pl); 
-     status_xp = ( ( inm!=0)|( inm!=1));
+    status_xp = (inm!=0)|(inm!=1);
 endfunction:status_xp
 
 function SE_STATE_ctrl pre_status(input [7:0] code,output logic [15:0] pl,input SE_STATE_ctrl ll); 
     if(89)begin
-         gp = code;
-         pre_status = 0;
+        gp = code;
+        pre_status = 0;
     end
 endfunction:pre_status
 
-assign  gp = status(67, gp+1,opop);
-assign  gp = pre_status();
-assign  gp = ( ( inm!=0)|( inm!=1));
+assign gp = status(67,gp+1,opop);
+assign gp = pre_status();
+assign gp = (inm!=0)|(inm!=1);
 
 endmodule

data/lib/tdl/examples/2_hdl_class/tmp/test_initial_assert.sv

@@ -22,10 +22,10 @@ logic ppx;
 //-------- expression ------------------------------------------------------
 initial begin
     assert(9)else begin
-         $error("iiiiiiiiiiiii");
-         $stop;
+        $error("iiiiiiiiiiiii");
+        $stop;
     end
-     ppx = 1'b0;
+    ppx = 1'b0;
 end
 
 endmodule

data/lib/tdl/examples/2_hdl_class/tmp/test_module.sv

@@ -21,9 +21,9 @@ module test_module (
 //==========================================================================
 //-------- define ----------------------------------------------------------
 logic [axi_wr_inf.ASIZE-1:0]  addr ;
-logic [ axi_wr_inf.IDSIZE-4-1:0]  id ;
+logic [axi_wr_inf.IDSIZE-4-1:0]  id ;
 logic [24-1:0]  length ;
-axi_inf #(.DSIZE(axi_wr_inf.DSIZE),.IDSIZE( axi_wr_inf.IDSIZE-4),.ASIZE(axi_wr_inf.ASIZE),.LSIZE(24),.MODE("ONLY_WRITE"),.ADDR_STEP(8192)) pre_axi_wr_inf (.axi_aclk(axi_wr_inf.axi_aclk),.axi_aresetn(axi_wr_inf.axi_aresetn)) ;
+axi_inf #(.DSIZE(axi_wr_inf.DSIZE),.IDSIZE(axi_wr_inf.IDSIZE-4),.ASIZE(axi_wr_inf.ASIZE),.LSIZE(24),.MODE("ONLY_WRITE"),.ADDR_STEP(8192)) pre_axi_wr_inf (.axi_aclk(axi_wr_inf.axi_aclk),.axi_aresetn(axi_wr_inf.axi_aresetn)) ;
 //==========================================================================
 //-------- instance --------------------------------------------------------
 axi_stream_cache_35bit cache_inst(

data/lib/tdl/examples/2_hdl_class/tmp/test_module_var.sv

@@ -5,7 +5,7 @@ _______________________________________
 descript:
 author : Cook.Darwin
 Version: VERA.0.0
-created: xxxx.xx.xx
+created: 2021-03-20 20:34:51 +0800
 madified:
 ***********************************************/
 `timescale 1ns/1ps

data/lib/tdl/examples/2_hdl_class/tmp/test_package.sv

@@ -5,13 +5,12 @@ _______________________________________
 descript:
 author : Cook.Darwin
 Version: VERA.0.0
-created: xxxx.xx.xx
+created: 2021-03-20 12:10:27 +0800
 madified:
 ***********************************************/
 
 
-package test_package;
-parameter  NUM = 6;
+module test_packageparameter  NUM = 6;();
 //==========================================================================
 //-------- define ----------------------------------------------------------
 typedef struct {
@@ -33,6 +32,6 @@ s_ing s_ing_v1;
 
 //==========================================================================
 //-------- expression ------------------------------------------------------
-assign  zing_v0.op[9] = 0;
+assign zing_v0.op[9] = 0;
 
-endpackage:test_package
+endmodule

data/lib/tdl/examples/2_hdl_class/tmp/test_package2.sv

@@ -27,10 +27,10 @@ z_ing y0;
 
 //==========================================================================
 //-------- expression ------------------------------------------------------
-assign  out = NUM;
-assign  out = data;
+assign out = NUM;
+assign out = data;
 
-assign  y0.op = 0;
-assign  y0.op[0] = 0;
+assign y0.op = 0;
+assign y0.op[0] = 0;
 
 endmodule

data/lib/tdl/examples/2_hdl_class/tmp/test_struct_function.sv

@@ -37,8 +37,8 @@ s_map s_map_a1;
 //==========================================================================
 //-------- expression ------------------------------------------------------
 function s_map f_g(input s_map fin); 
-     f_g = fin.op;
-     f_g.yp = 1;
+    f_g = fin.op;
+    f_g.yp = 1;
 endfunction:f_g
 
 endmodule

data/lib/tdl/examples/2_hdl_class/tmp/test_vcs_string.sv

@@ -5,7 +5,7 @@ _______________________________________
 descript:
 author : Cook.Darwin
 Version: VERA.0.0
-created: xxxx.xx.xx
+created: 2021-03-21 10:19:17 +0800
 madified:
 ***********************************************/
 `timescale 1ns/1ps

data/lib/tdl/examples/2_hdl_class/tmp/text_generate.sv

@@ -15,10 +15,10 @@ module text_generate #(
     parameter  BOARD_TOTAL = 4,
     parameter  WW          = "OFF"
 )(
-    input [ NUM-1:0]        ip_s_addr          [32-1:0],
-    input [ NUM-1:0]        ip_d_addr          [32-1:0],
-    input [ NUM-1:0]        mac_s_addr         [48-1:0],
-    input [ NUM-1:0]        mac_d_addr         [48-1:0],
+    input [NUM-1:0]         ip_s_addr          [32-1:0],
+    input [NUM-1:0]         ip_d_addr          [32-1:0],
+    input [NUM-1:0]         mac_s_addr         [48-1:0],
+    input [NUM-1:0]         mac_d_addr         [48-1:0],
     input [15:0]            fpga_udp_ctrl_port,
     input [15:0]            fpga_udp_data_port,
     input [15:0]            fpga_udp_dire_port,
@@ -43,12 +43,12 @@ for(genvar KK0=0;KK0 < NUM;KK0++)begin
     for(genvar KK1=0;KK1 < 7;KK1++)begin
         for(genvar KK2=0;KK2 < 6;KK2++)begin
 
-            if( KK0==2)begin
-                assign  rx_udp_data_8bit[ 8*1][ 1*2] = "90909";
+            if(KK0==2)begin
+                assign rx_udp_data_8bit[8*1][1*2] = "90909";
             end end
     end
 end
 endgenerate
-assign  mac_s_addr[0][0] = mac_d_addr[0][0];
+assign mac_s_addr[0][0] = mac_d_addr[0][0];
 
 endmodule

data/lib/tdl/examples/4_generate/test_generate.sv

@@ -13,12 +13,12 @@ madified:
 module test_generate #(
     parameter  NUM = 8
 )(
-    input [7:0]       ain,
-    output [7:0]      bout,
-    input [5:0]       cin  [NUM-1:0],
-    output [ NUM-1:0] dout [6-1:0],
-    input [ NUM-1:0]  ein,
-    output [ NUM-1:0] fout
+    input [7:0]      ain,
+    output [7:0]     bout,
+    input [5:0]      cin  [NUM-1:0],
+    output [NUM-1:0] dout [6-1:0],
+    input [NUM-1:0]  ein,
+    output [NUM-1:0] fout
 );
 
 //==========================================================================
@@ -32,18 +32,18 @@ module test_generate #(
 //-------- expression ------------------------------------------------------
 generate
 for(genvar KK0=0;KK0 < 8;KK0++)begin
-    assign  bout[ KK0] = ain[ 7-( KK0)];
+    assign bout[KK0] = ain[7-(KK0)];
 end
 endgenerate
 
 generate
 for(genvar KK0=0;KK0 < NUM;KK0++)begin
 
-    if( KK0<4)begin
-        assign  dout[ KK0] = cin[ KK0];
+    if(KK0<4)begin
+        assign dout[KK0] = cin[KK0];
     end 
     else begin
-        assign  dout[ KK0] = ( cin[ KK0]+( KK0));
+        assign dout[KK0] = cin[KK0]+(KK0);
     end
 end
 endgenerate
@@ -51,7 +51,7 @@ endgenerate
 generate
 for(genvar KK0=0;KK0 < NUM;KK0++)begin
     for(genvar KK1=0;KK1 < 6;KK1++)begin
-        assign  fout[ KK0][ KK1] = ein[ KK1][ KK0];
+        assign fout[KK0][KK1] = ein[KK1][KK0];
     end
 end
 endgenerate

data/lib/tdl/examples/5_logic_combin/test_logic_combin.sv

@@ -29,8 +29,8 @@ logic [16-1:0]  cc[2-1:0] ;
 
 //==========================================================================
 //-------- expression ------------------------------------------------------
-assign  ca = {a0,a1,a2};
-assign  cb = {>>{b1,b0}};
-assign  cc = {<<{c0,c1}};
+assign ca = {a0,a1,a2};
+assign cb = {>>{b1,b0}};
+assign cc = {<<{c0,c1}};
 
 endmodule

data/lib/tdl/examples/7_module_with_package/body_package.sv

@@ -5,13 +5,12 @@ _______________________________________
 descript:
 author : Cook.Darwin
 Version: VERA.0.0
-created: xxxx.xx.xx
+created: 2021-03-20 12:10:27 +0800
 madified:
 ***********************************************/
 
 
-package body_package;
-parameter  BDSIZE = 10;
+module body_packageparameter  BDSIZE = 10;();
 //==========================================================================
 //-------- define ----------------------------------------------------------
 
@@ -22,4 +21,4 @@ parameter  BDSIZE = 10;
 //==========================================================================
 //-------- expression ------------------------------------------------------
 
-endpackage:body_package
+endmodule

data/lib/tdl/examples/7_module_with_package/example_pkg.sv

@@ -11,8 +11,8 @@ madified:
 `timescale 1ns/1ps
 
 module example_pkg import head_package::*;(
-    input [ HDSIZE-1:0] indata,
-    output logic[31:0]  odata
+    input [HDSIZE-1:0] indata,
+    output logic[31:0] odata
 );
 
 //------>> EX CODE <<-------------------
@@ -29,7 +29,7 @@ s_head ss_head;
 
 //==========================================================================
 //-------- expression ------------------------------------------------------
-assign  ss_head.idata = 4;
-assign  ss_head.valid = 1'b1;
+assign ss_head.idata = 4;
+assign ss_head.valid = 1'b1;
 
 endmodule

data/lib/tdl/examples/7_module_with_package/head_package.sv

@@ -5,13 +5,12 @@ _______________________________________
 descript:
 author : Cook.Darwin
 Version: VERA.0.0
-created: xxxx.xx.xx
+created: 2021-03-20 12:10:27 +0800
 madified:
 ***********************************************/
 
 
-package head_package;
-parameter  HDSIZE = 8;
+module head_packageparameter  HDSIZE = 8;();
 //==========================================================================
 //-------- define ----------------------------------------------------------
 typedef struct {
@@ -26,4 +25,4 @@ logic valid;
 //==========================================================================
 //-------- expression ------------------------------------------------------
 
-endpackage:head_package
+endmodule

data/lib/tdl/examples/8_top_module/tb_test_top.sv

@@ -5,11 +5,10 @@ _______________________________________
 descript:
 author : Cook.Darwin
 Version: VERA.0.0
-created: xxxx.xx.xx
+created: 2021-03-20 12:10:27 +0800
 madified:
 ***********************************************/
 `timescale 1ns/1ps
-`timescale 1ns/1ps
 
 module tb_test_top();
 //==========================================================================

data/lib/tdl/examples/9_itegration/clock_manage/itgt_module_clock_manage.rb

@@ -29,5 +29,18 @@ class ClockManage < ItegrationVerb
 
     end
 
+    def_test_unit('test_clock_xx',__dir__) do 
+        test_unit_init do 
+
+        end
+    end
+
+    def_test_unit('test_clock_bb',__dir__) do 
+        test_unit_init do 
+
+        end
+    end
+
+
 end
 

data/lib/tdl/examples/9_itegration/clock_manage/test_clock_bb.sv

@@ -0,0 +1,34 @@
+/**********************************************
+_______________________________________ 
+___________    Cook Darwin   __________    
+_______________________________________
+descript:
+author : Cook.Darwin
+Version: VERA.0.0
+created: 2021-03-20 23:48:13 +0800
+madified:
+***********************************************/
+`timescale 1ns/1ps
+
+module test_clock_bb(
+    input        from_up_pass,
+    output logic to_down_pass
+);
+
+//==========================================================================
+//-------- define ----------------------------------------------------------
+
+
+//==========================================================================
+//-------- instance --------------------------------------------------------
+
+//==========================================================================
+//-------- expression ------------------------------------------------------
+initial begin
+    to_down_pass = 1'b0;
+    wait(from_up_pass);
+    $root.tb_test_tttop_sim.test_unit_region = "test_clock_bb";
+    to_down_pass = 1'b1;
+end
+
+endmodule

data/lib/tdl/examples/9_itegration/tb_test_top.sv

@@ -5,7 +5,7 @@ _______________________________________
 descript:
 author : Cook.Darwin
 Version: VERA.0.0
-created: xxxx.xx.xx
+created: 2021-03-20 20:34:51 +0800
 madified:
 ***********************************************/
 `timescale 1ns/1ps
@@ -23,7 +23,7 @@ test_top rtl_top(
 //==========================================================================
 //-------- expression ------------------------------------------------------
 initial begin
-     forever begin #(33ns);gl_clk = ~gl_clk;end;
+    forever begin #(33ns);gl_clk = ~gl_clk;end;
 end
 
 endmodule

data/lib/tdl/examples/9_itegration/tb_test_tttop.sv

@@ -23,7 +23,7 @@ test_tttop rtl_top(
 //==========================================================================
 //-------- expression ------------------------------------------------------
 initial begin
-     forever begin #(33ns);gl_clk = ~gl_clk;end;
+    forever begin #(33ns);gl_clk = ~gl_clk;end;
 end
 
 endmodule

data/lib/tdl/examples/9_itegration/tb_test_tttop_sim.sv

@@ -0,0 +1,38 @@
+/**********************************************
+_______________________________________ 
+___________    Cook Darwin   __________    
+_______________________________________
+descript:
+author : Cook.Darwin
+Version: VERA.0.0
+created: xxxx.xx.xx
+madified:
+***********************************************/
+`timescale 1ns/1ps
+
+module tb_test_tttop_sim();
+//==========================================================================
+//-------- define ----------------------------------------------------------
+logic gl_clk;
+string test_unit_region;
+logic unit_pass_u;
+logic unit_pass_d;
+
+//==========================================================================
+//-------- instance --------------------------------------------------------
+test_tttop_sim rtl_top(
+/* input clock */.global_sys_clk (gl_clk )
+);
+test_clock_bb test_unit_0(
+/* input  */.from_up_pass (unit_pass_u ),
+/* output */.to_down_pass (unit_pass_d )
+);
+//==========================================================================
+//-------- expression ------------------------------------------------------
+initial begin
+    forever begin #(33ns);gl_clk = ~gl_clk;end;
+end
+
+assign unit_pass_u = 1'b1;
+
+endmodule