axi_tdl 0.0.10 → 0.1.0

data/lib/axi_tdl.rb

@@ -20,6 +20,7 @@ add_to_tdl_paths    File.expand_path(File.join(__dir__, "axi/common_fifo"))
 add_to_tdl_paths    File.expand_path(File.join(__dir__, "axi/common"))
 add_to_tdl_paths    File.expand_path(File.join(__dir__, "axi/data_interface")) 
 add_to_tdl_paths    File.expand_path(File.join(__dir__, "axi/data_interface/data_inf_c"))
+add_to_tdl_paths    File.expand_path(File.join(__dir__, "axi/techbench"))
 
 ## base require 
 require_hdl 'axis_master_empty.sv'

data/lib/axi_tdl/version.rb

@@ -1,3 +1,3 @@
 module AxiTdl
-  VERSION = "0.0.10"
+  VERSION = "0.1.0"
 end

data/lib/tdl/auto_script/autogensdl.rb

@@ -232,10 +232,21 @@ class AutoGenSdl
     end
 
     def gen_file
-        @autof = File.open(@autof_name,"w") do |f|
-            f.puts gen_head
-            f.puts gen_content
-            # f.puts "sm.origin_sv = true"
+        unless File.exist?(@autof_name) 
+            @autof = File.open(@autof_name,"w") do |f|
+                f.print gen_head
+                f.print gen_content
+                # f.puts "sm.origin_sv = true"
+            end
+        else 
+            _old_str  = File.open(@autof_name).read
+            _new_str = gen_head+gen_content
+            if _old_str != _new_str
+                @autof = File.open(@autof_name,"w") do |f|
+                    f.print _new_str
+                    # f.puts "sm.origin_sv = true"
+                end
+            end
         end
     end
 
@@ -255,7 +266,7 @@ self.path = File.expand_path(__FILE__)
     end
 
     def gen_content
-        (@param_port_inst+@signals_ports_inst+@inf_ports_inst + ["end"]).join("\n")
+        (@param_port_inst+@signals_ports_inst+@inf_ports_inst + ["end\n\n"]).join("\n")
     end
 
 

data/lib/tdl/axi4/axi4_interconnect_verb.rb

@@ -218,16 +218,18 @@ class Axi4
                 else
                     mode_str = "ONLY_READ_to_BOTH"
                 end
+                require_hdl 'axi4_direct_B1.sv'
                 # Axi4.axi4_direct_a1(mode:mode_str,slaver:lo,master:"#{sub_name}[#{index}]",belong_to_module:belong_to_module)
                 belong_to_module.Instance('axi4_direct_B1',"axi4_direct_a1_long_to_wide_#{sub_name}_#{globle_random_name_flag()}") do |h|
                     # h.param.MODE    mode_str    #//ONLY_READ to BOTH,ONLY_WRITE to BOTH,BOTH to BOTH,BOTH to ONLY_READ,BOTH to ONLY_WRITE
-                    h.slaver        lo
-                    h.master        "#{sub_name}[#{index}]".to_nq
+                    h.slaver_inf        lo
+                    h.master_inf        "#{sub_name}[#{index}]".to_nq
                 end
 
             else
                 los = short_only.pop
                 @_long_slim_to_wide.delete los
+                require_hdl 'axi4_combin_wr_rd_batch.sv'
                 if wr_lg
                     # Axi4.axi4_combin_wr_rd_batch(wr_slaver:lo,rd_slaver:los,master:"#{sub_name}[#{index}]",belong_to_module:belong_to_module)
                     belong_to_module.Instance(:axi4_combin_wr_rd_batch,"axi4_combin_wr_rd_batch_inst_#{sub_name}") do |h|

data/lib/tdl/basefunc.rb

@@ -264,6 +264,7 @@ class Integer
     def clog2
         b = Math.log2(self)
         c = b.ceil
+        return c
     end
 
 end

data/lib/tdl/class_hdl/hdl_always_comb.rb

@@ -3,9 +3,10 @@ module ClassHDL
 
     class HDLAlwaysCombBlock 
         attr_accessor :opertor_chains
-
-        def initialize
+        attr_reader :belong_to_module
+        def initialize(belong_to_module)
             @opertor_chains = []
+            @belong_to_module = belong_to_module
         end
 
         def instance
@@ -28,7 +29,7 @@ module ClassHDL
     end
 
     def self.AlwaysComb(sdl_m,&block)
-        ClassHDL::AssignDefOpertor.with_new_assign_block(ClassHDL::HDLAlwaysCombBlock.new) do |ab|
+        ClassHDL::AssignDefOpertor.with_new_assign_block(ClassHDL::HDLAlwaysCombBlock.new(sdl_m)) do |ab|
             AssignDefOpertor.with_rollback_opertors(:new,&block)
             # return ClassHDL::AssignDefOpertor.curr_assign_block
             AssignDefOpertor.with_rollback_opertors(:old) do

data/lib/tdl/class_hdl/hdl_always_ff.rb

@@ -30,14 +30,14 @@ module ClassHDL
     class ClassNegedge < ClassEdge
     end
 
-
-    class HDLAlwaysFFBlock 
+    class HDLAlwaysBlock 
         attr_accessor :opertor_chains,:posedges,:negedges
-
-        def initialize
+        attr_reader :belong_to_module
+        def initialize(belong_to_module)
             @opertor_chains = []
             @posedges = []
             @negedges = []
+            @belong_to_module = belong_to_module
         end
 
         def edge_instance(flag='posedge',edges=[])
@@ -50,6 +50,32 @@ module ClassHDL
             return es.map{|e| "#{flag} #{e.to_s}"}
         end
 
+        def instance
+            str = []
+
+            pose_str = edge_instance('posedge',@posedges)
+            nege_str = edge_instance('negedge',@negedges)
+            pose_str.concat nege_str
+
+            str.push "always@(#{pose_str.join(",")}) begin "
+            opertor_chains.each do |op|
+                unless op.is_a? OpertorChain
+                    str.push op.instance(:always_ff).gsub(/^./){ |m| "    #{m}"}
+                else 
+                    unless op.slaver
+                        rel_str = ClassHDL.compact_op_ch(op.instance(:always_ff))
+                        str.push "    #{rel_str};"
+                    end
+                end
+                
+            end
+            str.push "end\n"
+            str.join("\n")
+        end
+    end
+
+    class HDLAlwaysFFBlock < HDLAlwaysBlock
+
         def instance
             str = []
 
@@ -74,8 +100,21 @@ module ClassHDL
         end
     end
 
+    def self.Always(sdl_m: nil,posedge: [],negedge: [],&block)
+        ClassHDL::AssignDefOpertor.with_new_assign_block(ClassHDL::HDLAlwaysBlock.new(sdl_m)) do |ab|
+            ab.posedges = posedge
+            ab.negedges = negedge
+
+            AssignDefOpertor.with_rollback_opertors(:new,&block)
+            # return ClassHDL::AssignDefOpertor.curr_assign_block
+            AssignDefOpertor.with_rollback_opertors(:old) do
+                sdl_m.Logic_draw.push ab.instance
+            end
+        end
+    end
+
     def self.AlwaysFF(sdl_m: nil,posedge: [],negedge: [],&block)
-        ClassHDL::AssignDefOpertor.with_new_assign_block(ClassHDL::HDLAlwaysFFBlock.new) do |ab|
+        ClassHDL::AssignDefOpertor.with_new_assign_block(ClassHDL::HDLAlwaysFFBlock.new(sdl_m)) do |ab|
             ab.posedges = posedge
             ab.negedges = negedge
 
@@ -116,7 +155,7 @@ module ClassHDL
     end
 
     def self.AlwaysSIM(sdl_m: nil,posedge: [],negedge: [],&block)
-        ClassHDL::AssignDefOpertor.with_new_assign_block(ClassHDL::HDLAlwaysSIMBlock.new) do |ab|
+        ClassHDL::AssignDefOpertor.with_new_assign_block(ClassHDL::HDLAlwaysSIMBlock.new(sdl_m)) do |ab|
             ab.posedges = posedge
             ab.negedges = negedge
 
@@ -144,16 +183,18 @@ class SdlModule
     end
 
     def Always(posedge: nil,negedge: nil,&block)
-        ClassHDL::AlwaysFF(sdl_m: self,posedge: posedge,negedge: negedge,&block)
+        ClassHDL::Always(sdl_m: self,posedge: posedge,negedge: negedge,&block)
     end
 
+    alias_method :always, :Always
+
     def Always_ff(posedge: nil,negedge: nil,&block)
         ClassHDL::AlwaysFF(sdl_m: self,posedge: posedge,negedge: negedge,&block)
     end
 
     def always_ff(*args,&block)
         if args[0].is_a? Hash 
-            return Always(args[0],&block)
+            return Always(**args[0],&block)
         end 
         posedge_list = []
         negedge_list = [] 

data/lib/tdl/class_hdl/hdl_assign.rb

@@ -3,9 +3,11 @@ module ClassHDL
 
     class HDLAssignBlock 
         attr_accessor :opertor_chains
-
-        def initialize
+        attr_reader :belong_to_module
+        
+        def initialize(belong_to_module)
             @opertor_chains = []
+            @belong_to_module = belong_to_module
         end
 
         def instance
@@ -29,7 +31,7 @@ module ClassHDL
 
     def self.Assign(sdl_m,&block)
         # ClassHDL::AssignDefOpertor.curr_assign_block = ClassHDL::HDLAssignBlock.new
-        ClassHDL::AssignDefOpertor.with_new_assign_block(ClassHDL::HDLAssignBlock.new) do |ab|
+        ClassHDL::AssignDefOpertor.with_new_assign_block(ClassHDL::HDLAssignBlock.new(sdl_m)) do |ab|
             AssignDefOpertor.with_rollback_opertors(:new,&block)
             # return ClassHDL::AssignDefOpertor.curr_assign_block
             AssignDefOpertor.with_rollback_opertors(:old) do 

data/lib/tdl/class_hdl/hdl_block_ifelse.rb

@@ -2,9 +2,11 @@ module ClassHDL
 
     class BlockIF
         attr_accessor :cond,:opertor_chains,:slaver
-        def initialize
+        attr_reader :belong_to_module
+        def initialize(belong_to_module)
             @opertor_chains = []
             @cond = nil
+            @belong_to_module = belong_to_module
         end
 
         def instance(as_type= :cond)
@@ -180,7 +182,7 @@ module ClassHDL
 end
 
 module ClassHDL
-    class EnumStruct
+    class EnumStruct < AxiTdl::SdlModuleActiveBaseElm
         # attr_accessor :sdl_m
         attr_accessor :belong_to_module
         def initialize(sdl_m,*args)
@@ -238,7 +240,7 @@ end
 class SdlModule
 
     def IF(cond,&block)
-        new_op = ClassHDL::BlockIF.new
+        new_op = ClassHDL::BlockIF.new(self)
         # if ClassHDL::AssignDefOpertor.curr_assign_block.is_a? ClassHDL::BlockIF
         #     new_op.slaver = true
         # end
@@ -255,7 +257,7 @@ class SdlModule
     end
 
     def ELSIF(cond,&block)
-        new_op = ClassHDL::BlockELSIF.new
+        new_op = ClassHDL::BlockELSIF.new(self)
         # if ClassHDL::AssignDefOpertor.curr_assign_block.is_a? ClassHDL::BlockIF
         #     new_op.slaver = true
         # end
@@ -272,7 +274,7 @@ class SdlModule
     end
 
     def ELSE(&block)
-        new_op = ClassHDL::BlockELSE.new
+        new_op = ClassHDL::BlockELSE.new(self)
         # if ClassHDL::AssignDefOpertor.curr_assign_block.is_a? ClassHDL::BlockIF
         #     new_op.slaver = true
         # end
@@ -284,7 +286,7 @@ class SdlModule
     end
 
     def CASE(cond,&block)
-        new_op = ClassHDL::BlockCASE.new
+        new_op = ClassHDL::BlockCASE.new(self)
         # if ClassHDL::AssignDefOpertor.curr_assign_block.is_a? ClassHDL::BlockIF
         #     new_op.slaver = true
         # end
@@ -301,7 +303,7 @@ class SdlModule
     end
 
     def CASEX(cond,&block)
-        new_op = ClassHDL::BlockCASEX.new
+        new_op = ClassHDL::BlockCASEX.new(self)
         # if ClassHDL::AssignDefOpertor.curr_assign_block.is_a? ClassHDL::BlockIF
         #     new_op.slaver = true
         # end
@@ -318,7 +320,7 @@ class SdlModule
     end
 
     def WHEN(*cond,&block)
-        new_op = ClassHDL::BlockCASEWHEN.new
+        new_op = ClassHDL::BlockCASEWHEN.new(self)
 
         ClassHDL::AssignDefOpertor.with_new_assign_block(new_op) do |ab|
             if cond.is_a? ClassHDL::OpertorChain
@@ -333,7 +335,7 @@ class SdlModule
     end
 
     def DEFAULT(&block)
-        new_op = ClassHDL::BlockCASEDEFAULT.new
+        new_op = ClassHDL::BlockCASEDEFAULT.new(self)
 
         ClassHDL::AssignDefOpertor.with_new_assign_block(new_op) do |ab|
             block.call

data/lib/tdl/class_hdl/hdl_foreach.rb

@@ -55,7 +55,7 @@ class SdlModule
         ClassHDL::AssignDefOpertor.with_normal_opertor do 
             @@__foreach_index_cnt__ += 1
         end
-        new_op = ClassHDL::BlockFOREACH.new
+        new_op = ClassHDL::BlockFOREACH.new(self)
 
         ClassHDL::AssignDefOpertor.with_new_opertor do 
             ClassHDL::AssignDefOpertor.with_new_assign_block(new_op) do |ab|
@@ -81,7 +81,7 @@ class SdlModule
         ClassHDL::AssignDefOpertor.with_normal_opertor do 
             @@__for_index_cnt__ += 1
         end
-        new_op = ClassHDL::BlockFOR.new
+        new_op = ClassHDL::BlockFOR.new(self)
 
         ClassHDL::AssignDefOpertor.with_new_opertor do 
             ClassHDL::AssignDefOpertor.with_new_assign_block(new_op) do |ab|

data/lib/tdl/class_hdl/hdl_function.rb

@@ -57,12 +57,14 @@ module ClassHDL
         attr_accessor :opertor_chains,:name
         attr_accessor :open_ivoke
         attr_reader   :return_type
+        attr_reader   :belong_to_module
 
-        def initialize(name,return_type,*argvs)
+        def initialize(belong_to_module,name,return_type,*argvs)
             @opertor_chains = []
             @name = name
             @argvs = argvs
             @return_type = return_type
+            @belong_to_module = belong_to_module
         end
 
         def inst_port
@@ -117,7 +119,7 @@ module ClassHDL
 
     def self.Function(sdl_m,name,return_type,*argvs,&block)
         define_func_block_method(sdl_m,*argvs)
-        func_inst = ClassHDL::HDLFunction.new(name,return_type,*argvs)
+        func_inst = ClassHDL::HDLFunction.new(sdl_m,name,return_type,*argvs)
         ## 给 sdl module 定义函数方法
         sdl_m.define_singleton_method(name) do |*fargvs|
             # new_op = OpertorChain.new 

data/lib/tdl/class_hdl/hdl_generate.rb

@@ -3,9 +3,10 @@ module ClassHDL
     class HDLAssignGenerateBlock  
 
         attr_accessor :opertor_chains
-
-        def initialize
+        attr_reader :belong_to_module
+        def initialize(belong_to_module)
             @opertor_chains = []
+            @belong_to_module = belong_to_module
         end
 
         def instance
@@ -160,11 +161,11 @@ class SdlModule
         add_children_modules(inst_obj:inst_obj ,module_poit: tmp_sm)
 
         args.each_index do |e|
-            new_op = ClassHDL::OpertorChain.new 
+            new_op = ClassHDL::OpertorChain.new(nil, self) 
             new_op.tree.push(["KK#{e}".to_nq])
             kk_args << new_op
         end
-        ClassHDL::AssignDefOpertor.with_new_assign_block(ClassHDL::HDLAssignGenerateBlock.new ) do 
+        ClassHDL::AssignDefOpertor.with_new_assign_block(ClassHDL::HDLAssignGenerateBlock.new(self) ) do 
             ClassHDL::AssignDefOpertor.with_rollback_opertors(:new) do 
                 tmp_sm.instance_exec(*kk_args,&block)
             end

data/lib/tdl/class_hdl/hdl_initial.rb

@@ -3,9 +3,10 @@ module ClassHDL
 
     class HDLInitialBlock 
         attr_accessor :opertor_chains
-
-        def initialize
+        attr_reader :belong_to_module
+        def initialize(belong_to_module)
             @opertor_chains = []
+            @belong_to_module = belong_to_module
         end
 
         def instance(block_name=nil)
@@ -28,7 +29,7 @@ module ClassHDL
     end
 
     def self.Initial(sdl_m,block_name=nil,&block)
-        ClassHDL::AssignDefOpertor.with_new_assign_block(ClassHDL::HDLInitialBlock.new) do |ab|
+        ClassHDL::AssignDefOpertor.with_new_assign_block(ClassHDL::HDLInitialBlock.new(sdl_m)) do |ab|
             AssignDefOpertor.with_rollback_opertors(:new,&block)
             # return ClassHDL::AssignDefOpertor.curr_assign_block
             AssignDefOpertor.with_rollback_opertors(:old) do
@@ -82,7 +83,7 @@ class SdlModule
             return assert_old(cond,argv_str=formats,&block)
         end
 
-        new_op = ClassHDL::BlocAssertIF.new
+        new_op = ClassHDL::BlocAssertIF.new(self)
         ClassHDL::AssignDefOpertor.with_new_assign_block(new_op) do |ab|
             if cond.is_a? ClassHDL::OpertorChain
                 cond.slaver = true
@@ -102,7 +103,7 @@ class SdlModule
     end
 
     def assert_old(cond,argv_str=nil,&block)
-        new_op = ClassHDL::BlocAssertIF.new
+        new_op = ClassHDL::BlocAssertIF.new(self)
         # if ClassHDL::AssignDefOpertor.curr_assign_block.is_a? ClassHDL::BlockIF
         #     new_op.slaver = true
         # end
@@ -130,17 +131,17 @@ class SdlModule
     end
 
     def assert_error(argv_str)
-        ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(ClassHDL::OpertorChain.new(["$error(\"#{argv_str}\")".to_nq]))
-        ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(ClassHDL::OpertorChain.new(["$stop".to_nq]))
+        ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(ClassHDL::OpertorChain.new(["$error(\"#{argv_str}\")".to_nq], self))
+        ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(ClassHDL::OpertorChain.new(["$stop".to_nq], self))
     end
 
     def assert_format_error(formats=[],args=[])
-        ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(ClassHDL::OpertorChain.new(["$error(\"#{formats.join(' ')}\",#{args.map{|s| s.to_s}.join(',')})".to_nq]))
-        ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(ClassHDL::OpertorChain.new(["$stop".to_nq]))
+        ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(ClassHDL::OpertorChain.new(["$error(\"#{formats.join(' ')}\",#{args.map{|s| s.to_s}.join(',')})".to_nq], self))
+        ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(ClassHDL::OpertorChain.new(["$stop".to_nq], self))
     end
 
     def initial_exec(str)
-        ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(ClassHDL::OpertorChain.new([str.to_s.to_nq]))
+        ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(ClassHDL::OpertorChain.new([str.to_s.to_nq], self))
     end
 
     alias_method :always_sim_exec, :initial_exec

data/lib/tdl/class_hdl/hdl_module_def.rb

@@ -70,6 +70,9 @@ module ClassHDL
         def initialize(name,sdlm)
             @name = name
             @sdlm = sdlm
+            unless SdlModule.exist_module?(@name)
+                raise TdlError.new("Cant find module `#{name}` !!!")
+            end
         end
 
         def inst(dname,&block)
@@ -95,9 +98,23 @@ module ClassHDL
             # else 
             #     @sdlm.Instance(@name,dname.to_s,&block)
             # end
+            rel = nil
             AssignDefOpertor.with_rollback_opertors(:old) do 
-                inst(dname,&block)
+                if block_given?
+                    rel = inst(dname,&block)
+                else
+                    ## 当没有block 判断 sdlm是否相应方法
+                    # if @sdlm.has_signal?(dname)
+                    # if SdlModule.call_module(@name).has_signal?(dname)
+                    if SdlModule.call_module(@name).respond_to?(dname)
+                        rel =  SdlModule.call_module(@name).signal(dname)
+                    else 
+                        # super 
+                        raise TdlError.new( "Cant find signal `#{dname}` in module `#{@name}` path: #{SdlModule.call_module(@name).real_sv_path } !!!" )
+                    end
+                end
             end
+            return rel
         end
 
     end