axi_tdl 0.0.10 → 0.1.0

data/lib/tdl/examples/9_itegration/test_top.sv

@@ -5,7 +5,7 @@ _______________________________________
 descript:
 author : Cook.Darwin
 Version: VERA.0.0
-created: xxxx.xx.xx
+created: 2021-03-20 20:34:51 +0800
 madified:
 ***********************************************/
 `timescale 1ns/1ps
@@ -33,8 +33,8 @@ a_test_md a_test_md_inst(
 );
 //==========================================================================
 //-------- expression ------------------------------------------------------
-assign  x_origin_inf.axis_tvalid = 1'b0;
-assign  x_origin_inf.axis_tdata = '0;
-assign  x_origin_inf.axis_tlast = 1'b0;
+assign x_origin_inf.axis_tvalid = 1'b0;
+assign x_origin_inf.axis_tdata = '0;
+assign x_origin_inf.axis_tlast = 1'b0;
 
 endmodule

data/lib/tdl/examples/9_itegration/test_tttop.sv

@@ -5,7 +5,7 @@ _______________________________________
 descript:
 author : Cook.Darwin
 Version: VERA.0.0
-created: xxxx.xx.xx
+created: 2021-03-21 10:19:00 +0800
 madified:
 ***********************************************/
 `timescale 1ns/1ps
@@ -33,8 +33,8 @@ a_test_md a_test_md_inst(
 );
 //==========================================================================
 //-------- expression ------------------------------------------------------
-assign  x_origin_inf.axis_tvalid = 1'b0;
-assign  x_origin_inf.axis_tdata = '0;
-assign  x_origin_inf.axis_tlast = 1'b0;
+assign x_origin_inf.axis_tvalid = 1'b0;
+assign x_origin_inf.axis_tdata = '0;
+assign x_origin_inf.axis_tlast = 1'b0;
 
 endmodule

data/lib/tdl/examples/9_itegration/test_tttop_sim.sv

@@ -0,0 +1,9 @@
+
+`timescale 1ns/1ps
+module test_tttop_sim();
+initial begin
+    #(1us);
+    $warning("Check TopModule.sim,please!!!");
+    $stop;
+end
+endmodule

data/lib/tdl/examples/9_itegration/top.rb

@@ -8,4 +8,5 @@ TopModule.test_tttop(__dir__) do
     add_itegration('ClockManage',pins_map: :CM)
     add_itegration('ABlock')
 
+    add_test_unit('test_clock_bb')
 end

data/lib/tdl/exlib/axis_eth_ex.rb

@@ -0,0 +1,95 @@
+
+module AxiTdl
+    class EthernetStreamDefAtom
+
+        def initialize(belong_to_module: nil, stream: nil, start: 0, length: 32)
+            @belong_to_module = belong_to_module
+            @stream = stream
+            @start = start
+            @length = length
+        end
+
+        def -(str)
+            @stream.x_all_bits_slice(name: str.to_s ,start: @start, length: @length)
+        end
+    end
+end
+
+class AxiStream
+
+    ## 转到 网络流
+    def to_eth(esize=8) # SIZE:8 ,64, 32
+        @__ethernet_type__ = esize
+    end
+
+    ## 截取流数据段
+    def all_bits_slice(start: 8*4,length:32)
+        return AxiTdl::EthernetStreamDefAtom.new(belong_to_module: @belong_to_module, stream: self, start: start, length: length)
+    end
+
+    def x_all_bits_slice(name: "slice_#{globle_random_name_flag()}", start: 8*4,length:32)
+        raise TdlError.new("#{name} is not ethernet stream, before used it must be call to_eth") unless @__ethernet_type__
+        # @belong_to_module.logic[length]     - name
+        @belong_to_module.instance_exec(self,name,start,length,@__ethernet_type__) do |_targget_axis, _name, _start, _length, _ethernet_type|
+            logic[_length]     - _name
+            _end = _start + _length -1
+
+            ## 如果选的区域在一个Clock里面
+            if _start / _ethernet_type == (_end) / _ethernet_type
+                _target_cnt = _start/_ethernet_type
+
+                always_ff(posedge: _targget_axis.aclk, negedge: _targget_axis.aresetn) do 
+                    IF ~_targget_axis.aresetn do 
+                        signal(_name)   <= 0.A 
+                    end
+                    ELSE do 
+                        IF _targget_axis.vld_rdy do 
+                            IF (_targget_axis.axis_tcnt[15,0] == "16'd#{_target_cnt}".to_nq) do
+                                signal(_name) <= _targget_axis.axis_tdata[rubyOP{_ethernet_type - _start%_ethernet_type - 1}, rubyOP{_ethernet_type - _end%_ethernet_type - 1}, ]
+                            end 
+                            ELSE do 
+                                signal(_name) <= signal(_name)
+                            end
+                        end
+                        ELSE do 
+                            signal(_name)   <= signal(_name)
+                        end
+                    end
+                end
+            end
+
+            ## 如果夸Clock
+            if _start / _ethernet_type != (_end) / _ethernet_type
+                _slice_range = ( (_start / _ethernet_type)..(_end) / _ethernet_type ).to_a
+
+                always_ff(posedge: _targget_axis.aclk, negedge: _targget_axis.aresetn) do 
+                    IF ~_targget_axis.aresetn do 
+                        signal(_name)   <= 0.A 
+                    end
+                    ELSE do 
+                        IF _targget_axis.vld_rdy do 
+                            _slice_range.each do |e|
+                                IF (_targget_axis.axis_tcnt[15,0] == "16'd#{e}".to_nq) do
+                                    ##第一个
+                                    if ClassHDL::AssignDefOpertor.with_rollback_opertors(:old,&(proc { e == _slice_range.first}) )  
+                                        signal(_name)[rubyOP{_length-1}, rubyOP{_length - (_ethernet_type - _start%_ethernet_type)}] <= _targget_axis.axis_tdata[rubyOP{_ethernet_type - _start%_ethernet_type-1}, 0]
+                                    ## 最后一个
+                                    elsif ClassHDL::AssignDefOpertor.with_rollback_opertors(:old,&(proc { e == _slice_range.last}) )  
+                                        signal(_name)[rubyOP{_end%_ethernet_type},0] <= _targget_axis.axis_tdata[rubyOP{_ethernet_type-1}, rubyOP{_ethernet_type-_end%_ethernet_type-1}]
+                                    else 
+                                        signal(_name)[rubyOP{(_end - e*_ethernet_type)}, rubyOP{(_end - e*_ethernet_type - _ethernet_type+1)}] <= _targget_axis.axis_tdata
+                                    end
+                                end
+                            end
+                        end
+                        ELSE do 
+                            signal(_name)   <= signal(_name)
+                        end
+                    end
+                end
+
+            end
+        end
+        @belong_to_module.signal(name)
+    end
+end

data/lib/tdl/exlib/axis_verify.rb

@@ -0,0 +1,264 @@
+
+module AxiTdl
+
+    module AxisVerify 
+
+        class Iteration
+
+            # attr_accessor :axis_tlast, :axis_tuser, :axis_tkeep, :axis_tdata
+            def initialize(length: 1024, data: [0], vld_perc: 50,user:[0], keep:[1] , rand_seed: 0 ,dsize: 8, usize: 1)
+                @axis_tdata = data.to_a * (length / data.size + 1)
+                @axis_tuser = user.to_a * (length / user.size + 1)
+                @axis_tkeep = keep.to_a * (length / keep.size + 1)
+                @vld_perc = vld_perc / 100.0
+                @length = length
+                @prng = Random.new( rand_seed )
+                @dsize = dsize
+                @usize = usize 
+                @ksize = @dsize / 8 + (@dsize%8==0 ? 0 : 1)
+
+                raise TdlError.new("valid percetage cant be zero") if vld_perc==0
+            end
+
+            # def each(&block)
+            #     # yield(axis_tlast, axis_tuser, axis_tkeep, axis_tdata)
+            #     # @length.each do |index|
+            #     #     yield(axis_tlast, axis_tuser, axis_tkeep, axis_tdata)
+            #     # end
+            #     index = 0
+            #     while true 
+
+            #         # @length  -= 1
+            #         # @length = axis_tcnt
+            #         # yield(@length, axis_tvalid, axis_tlast, axis_tuser, axis_tkeep, axis_tdata)
+                    
+            #         yield(index, (@vld_perc > @prng.rand ? 1 : 0), @axis_tuser[index], @axis_tkeep[index], (@length==0 ? 1 : 0), @axis_tdata[index])
+                    
+            #         if @length <= index + 1
+            #             break 
+            #         end
+            #         index += 1
+            #     end
+            # end
+
+            def to_a 
+                collect = []
+                index = 0
+                10000.times do  
+
+                    vld = (@vld_perc > @prng.rand ? 1 : 0)
+                    
+                    collect << [ index, vld , @axis_tuser[index], @axis_tkeep[index], (@length==(index+vld) ? 1 : 0), @axis_tdata[index] ]
+                    
+                    if @length <= index + vld
+                        break 
+                    end
+
+                    index += vld
+                end
+
+                collect 
+            end
+
+            def stream_context
+                collect = []
+                to_a.each do |axis_tcnt, axis_tvalid, axis_tuser, axis_tkeep, axis_tlast, axis_tdata|
+                    u0 = axis_tdata % (2**@dsize)
+                    u3 = axis_tlast << (@dsize)
+                    u1 = (axis_tkeep % (2**@ksize)) << (@dsize + 1)
+                    u2 = (axis_tuser % (2**@usize)) << (@dsize + @ksize + 1)
+                    u4 = axis_tvalid << (@dsize + @ksize + @usize + 1)
+                    collect << (u0+u1+u2+u3+u4)
+                end
+
+                collect.map do |e| 
+                    "%0#{(@dsize + @ksize + @usize + 1 + 1)/4  + ( ((@dsize + @ksize + @usize + 1 + 1)%4 == 0) ? 0 : 1 )}x"%e
+                end
+                # collect
+            end
+        end
+
+        class SimpleStreams 
+            attr_accessor :streams
+            def initialize(length: [10,200], gap_len: [0,10], data: [ (0...100) ] * 10 , vld_perc: [50, 100], dsize: 8)
+                max_len = [length.size, gap_len.size, data.size , vld_perc.size ].max
+                @lengths = length.to_a * (max_len / length.size + 1 )
+                @gap_lens = gap_len.to_a * (max_len / gap_len.size + 1 )
+                @datas = data.to_a * (max_len / data.size + 1 )
+                @vld_percs = vld_perc.to_a * (max_len / vld_perc.size + 1 )
+                
+                @dsize = dsize 
+                @max_len = max_len
+                @streams = []
+                gen_itr
+            end
+
+            def gen_itr 
+                @max_len.times do |index|
+                   itr = Iteration.new(length: @lengths[index], data: @datas[index], vld_perc: @vld_percs[index],user:[0], keep:[1] , rand_seed: index ,dsize: @dsize, usize: 1)
+                   streams << itr
+               end
+            end
+
+            def coe 
+                collect = []
+                @max_len.times do |index|
+                     ## add grap 
+                    if @gap_lens[index] != 0
+                        collect += ["0"]*@gap_lens[index]
+                    end 
+                    itr = @streams[index]
+                    collect += itr.stream_context
+                end
+
+                mmp = [] 
+                collect.each_index do |index| 
+                    mmp << "@%04x #{collect[index]}\n"%index
+                end
+
+                mmp.join("")
+
+            end
+        end
+    
+    end
+
+end
+
+
+class AxiStream
+
+    def to_simple_sim_master_coe(length: [10,200], gap_len: [0,10], data: [ (0...100) ] , vld_perc: [50, 100], loop_coe: true)
+        # raise TdlError.new "file cant be empty"  unless file
+        file = File.join(AxiTdl::TDL_PATH,"./auto_script/tmp/","#{self.name}_#{globle_random_name_flag}.coe")
+        _sps = nil
+        ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do
+            require_sdl 'axis_sim_master_model.rb'
+            File.open(file,'w') do |f|
+                _sps = AxiTdl::AxisVerify::SimpleStreams.new(length: length, gap_len: gap_len, data: data , vld_perc: vld_perc)
+                f.print _sps.coe
+            end
+        end
+
+        self.define_singleton_method(:verification) do 
+            _sps 
+        end
+
+        @belong_to_module.instance_exec(self,file,loop_coe) do |_self,file,loop_coe| 
+
+            Instance(:axis_sim_master_model,"sim_model_inst_#{_self.name}") do |h| 
+                h.param.LOOP                (loop_coe ? "TRUE" : "FALSE")
+                h.param.RAM_DEPTH           File.open(File.expand_path(file)).readlines.size
+                h.input.load_trigger        1.b0
+                h.input[32].total_length    h.param.RAM_DEPTH
+                h.input[512*8].mem_file     File.expand_path(file) # {axis_tvalid, axis_tuser, axis_tkeep, axis_tlast, axis_tdata}
+                h.port.axis.master.out_inf  _self
+            end
+        end
+
+    end
+
+    def to_simple_sim_slaver(rdy_percetage=50,loop_rdy=true)
+        unless rdy_percetage.is_a?(Array)
+            @belong_to_module.instance_exec(self) do |_self|
+
+                always_ff(posedge: _self.aclk) do 
+                    IF ~_self.aresetn do 
+                        _self.axis_tready   <= 1.b0 
+                    end
+                    ELSE do 
+                        _self.axis_tready   <= rdy_percetage.precent_true
+                    end
+                end
+            end
+        else  
+            @belong_to_module.instance_exec(self,rdy_percetage,loop_rdy) do |_self,rdy_percetage,loop_rdy|
+
+                __xx = logic[32] - "#{_self.name}_rdy_percetage_index"
+                __rr = logic[rdy_percetage.size, 32] - "#{_self.name}_rdy_percetage"
+                Initial do 
+                    __xx <= 0
+                    rdy_percetage.each_index do |index|
+                        __rr[index] <= rdy_percetage[index]
+                    end
+                end 
+
+                Always(posedge: _self.aclk) do 
+                    IF _self.vld_rdy_last do 
+                        IF __xx >= (rdy_percetage.size - 1 ) do 
+                            if loop_rdy  
+                                __xx <= 0
+                            else 
+                                __xx <= __xx 
+                                __rr[__xx] = 0
+                            end
+                        end
+                        ELSE do 
+                            __xx <= __xx + 1.b1 
+                        end
+                    end
+                    ELSE do 
+                        __xx <= __xx 
+                    end
+                end 
+
+                always_ff(posedge: _self.aclk) do 
+                    IF ~_self.aresetn do 
+                        _self.axis_tready   <= 1.b0 
+                    end
+                    ELSE do 
+                        _self.axis_tready   <= "($urandom_range(0,99) <= #{__rr[__xx]})".to_nq
+                    end
+                end
+            end
+        end
+    end
+
+    def simple_verify_by_coe(file)
+        unless File.file?(file)
+            if file.is_a?(String)
+                wfile = File.join(AxiTdl::TDL_PATH,"./auto_script/tmp/","#{self.name}_#{globle_random_name_flag}.coe")
+                File.open(wfile,'w') do |f|
+                    f.puts file
+                end
+                file = wfile
+            end
+        end 
+
+        require_hdl 'axis_sim_verify_by_coe.sv'
+
+        @belong_to_module.instance_exec(self,File.open(file).readlines.size,file) do |_self,_ram_depth,_file|
+
+            Instance(:axis_sim_verify_by_coe, "axis_sim_verify_by_coe_inst_#{_self.name}") do |h|#(
+                h.param.RAM_DEPTH           _ram_depth
+                h.param.VERIFY_KEEP         "OFF"
+                h.param.VERIFY_USER         "OFF"
+                h.input.load_trigger        1.b0
+                h.input[32].total_length    _ram_depth
+                h.input[4096].mem_file      File.expand_path(_file)
+                h.port.axis.mirror.mirror_inf   _self
+            end
+        end
+    end
+end
+
+## Extand Array 
+module AxiTdl 
+    module Verification 
+        class CoeArray < Array 
+
+            def initialize(obj_array=nil)
+                super obj_array
+            end
+
+            def coe 
+                xcollect = []
+                self.each_index do |index|
+                    xcollect << "@#{index.to_s(16)} #{self[index].to_s(16)}\n"
+                end 
+                xcollect.join("")
+            end
+
+        end
+    end
+end

data/lib/tdl/exlib/clock_reset_verify.rb

@@ -0,0 +1,29 @@
+
+class Clock 
+
+    def to_sim_source
+        
+        @belong_to_module.instance_exec(self) do |_self|
+            Initial do 
+                _self   <= 1.b0 
+                initial_exec("#(100ns)")
+                initial_exec("forever begin #(#{1000.0/_self.freqM/2}ns);#{_self} = ~#{_self};end")
+            end
+        end
+    end
+end
+
+class Reset
+    def to_sim_source(ns=100)
+        
+        @belong_to_module.instance_exec(self,ns) do |_self,ns|
+            _xxx = (_self.active == 'low') ? 1.b0 : 1.b1 
+
+            Initial do 
+                _self   <= _xxx
+                initial_exec("#(#{ns}ns)")
+                _self   <= ~_self
+            end
+        end
+    end
+end