axi_tdl 0.0.10 → 0.1.0

data/lib/tdl/class_hdl/hdl_redefine_opertor.rb

@@ -39,13 +39,14 @@ module ClassHDL
 
     class OpertorChain
         attr_accessor :slaver,:tree,:instance_add_brackets
-
-        def initialize(arg=nil)
+        attr_reader :belong_to_module
+        def initialize(arg, belong_to_module)
             @tree = [] #[[inst0,symb0],[inst1,symb1],[other_chain,symb2],[other_chain,symb3]]
                        # self <symb0> inst0 <symb1> inst1 <symb2> ( other_chain ) <symb3> ( other_chain )
             if arg 
                 @tree << arg 
             end  
+            @belong_to_module = belong_to_module
         end
 
         ClassHDL::OP_SYMBOLS.each do |os|
@@ -61,14 +62,14 @@ module ClassHDL
                 new_op = nil
                 AssignDefOpertor.with_rollback_opertors(:old) do 
                     if tree.size == 2 && tree.last[1].to_s == "<="
-                        new_op =  OpertorChain.new 
+                        new_op =  OpertorChain.new(nil,belong_to_module) 
                         new_op.tree = new_op.tree + self.tree
                         new_op.tree.push [b,os] 
                     elsif  tree.size >= 2 && (!['*',"/","~"].include?(tree.last[1].to_s))
                         new_op =  brackets 
                         new_op.tree.push [b,os] 
                     else
-                        new_op =  OpertorChain.new 
+                        new_op =  OpertorChain.new(nil,belong_to_module)  
                         new_op.tree = new_op.tree + self.tree
                         new_op.tree.push [b,os] 
                     end 
@@ -107,12 +108,12 @@ module ClassHDL
 
         def brackets
             self.slaver = true
-            new_op = OpertorChain.new(["(#{self.instance})".to_nq])
+            new_op = OpertorChain.new(["(#{self.instance})".to_nq], belong_to_module)
         end
 
         def clog2
             self.slaver = true
-            new_op = OpertorChain.new(["$clog2(#{self.instance})".to_nq])
+            new_op = OpertorChain.new(["$clog2(#{self.instance})".to_nq],belong_to_module)
         end
 
         def self.define_op_flag(ruby_op,hdl_op)
@@ -126,7 +127,7 @@ module ClassHDL
                 # 计算生成新的OpertorChain 是 self 也需要抛弃
                 self.slaver = true
                 # return self
-                new_op =  OpertorChain.new 
+                new_op =  OpertorChain.new(nil, belong_to_module) 
                 new_op.tree = new_op.tree + self.tree
                 new_op.tree.push [b,hdl_op] 
     
@@ -159,10 +160,18 @@ module ClassHDL
                                 sb = " = "
                             end 
                         else 
-                            sb = "#{node[1].to_s}"
+                            # if(node[1].respond_to?(:belong_to_module) && node[1].belong_to_module && node[1].belong_to_module != belong_to_module)
+                            #     sb = "#{node[1].root_ref.to_s}"
+                            # else
+                                sb = "#{node[1].to_s}"
+                            # end
                         end
                     else
-                        sb = "#{node[1].to_s} "
+                        # if(node[1].respond_to?(:belong_to_module) && node[1].belong_to_module && node[1].belong_to_module != belong_to_module)
+                        #     sb = "#{node[1].root_ref.to_s}"
+                        # else
+                            sb = "#{node[1].to_s}"
+                        # end
                     end
                     
                     unless node[0].is_a? OpertorChain
@@ -173,7 +182,18 @@ module ClassHDL
                             # "如果是字符串 则原始输出"
                             str += (sb + '"' + node[0].to_s + '"')
                         else 
-                            str += (sb + node[0].to_s)
+                            # str += (sb + node[0].to_s)
+                            if(node[0].respond_to?(:root_ref) && node[0].respond_to?(:belong_to_module) && node[0].belong_to_module && (node[0].belong_to_module != belong_to_module) && node[0].belong_to_module.top_tb_ref? )
+                                # sb = "#{node[1].root_ref.to_s}"
+                                str += (sb + node[0].root_ref)
+                                ## 反向添加到 TestUnitModule
+                                if belong_to_module.is_a?(TestUnitModule)
+                                    belong_to_module.add_root_ref_ele(node[0])
+                                end
+                            else
+                                # sb = "#{node[1].to_s}"
+                                str += (sb + node[0].to_s)
+                            end
                         end
                     else 
                         node[0].slaver = true
@@ -215,8 +235,8 @@ module ClassHDL
 
     module AssignDefOpertor
         @@included_class = []
-        @@curr_assign_block = HDLAssignBlock.new ##HDLAssignBlock ##HDLAlwaysCombBlock
-        @@curr_assign_block_stack = [HDLAssignBlock.new ]
+        @@curr_assign_block = HDLAssignBlock.new(nil) ##HDLAssignBlock ##HDLAlwaysCombBlock
+        @@curr_assign_block_stack = [HDLAssignBlock.new(nil) ]
         @@curr_opertor_stack = [:old]
 
         def self.curr_opertor_stack
@@ -275,7 +295,8 @@ module ClassHDL
                     if b.is_a? OpertorChain
                         b.slaver = true 
                     end
-                    new_op = OpertorChain.new 
+                    ## 当 进行 X < Y 等运算时OpertorChain 需要获取 assign block的 belong_to_module
+                    new_op = OpertorChain.new(nil,@@curr_assign_block && @@curr_assign_block.belong_to_module) 
                     new_op.tree.push([self])
                     new_op.tree.push([b,symb])
                     if @@curr_assign_block
@@ -642,7 +663,7 @@ module TdlSpace
 end
 
 module ClassHDL
-    class StructVar 
+    class StructVar < AxiTdl::SdlModuleActiveBaseElm
         include ClassHDL::AssignDefOpertor
     end 
 end

data/lib/tdl/class_hdl/hdl_struct.rb

@@ -132,7 +132,7 @@ module ClassHDL
 
     end
 
-    class StructVar 
+    class StructVar < AxiTdl::SdlModuleActiveBaseElm
         # include ClassHDL::AssignDefOpertor
         attr_accessor :belong_to_module
         attr_accessor :dimension

data/lib/tdl/class_hdl/hdl_verify.rb

@@ -76,7 +76,7 @@ module ClassHDL
                     IF ~intf.rst_n do  
                         track_ci <= 0.A
                     end 
-                    ELSIF intf.vld_rdy do 
+                    ELSIF intf.vld_rdy do  
                         assert(intf.data == "#{mem_args}[#{track_ci}]".to_nq,"TRACK <#{intf.to_s}> Error;","Real<%d>"," != Expect<%d>",intf.data,"#{mem_args}[#{track_ci}]".to_nq)
                         track_ci <= track_ci + 1.b1
                     end

data/lib/tdl/elements/originclass.rb

@@ -99,8 +99,13 @@ module TdlSpace
     end
 end
 
+module AxiTdl
+    class SdlModuleActiveBaseElm
+    end
+end
+
 
-class BaseElm
+class BaseElm < AxiTdl::SdlModuleActiveBaseElm
     # attr_accessor :belong_module
     attr_accessor :belong_to_module
     attr_accessor :name

data/lib/tdl/elements/parameter.rb

@@ -183,7 +183,7 @@ class Parameter # add +
             else  
                 rel = NqString.new(signal.concat("#{symb}").concat('"').concat(a.to_s)).concat('"')
             end
-            new_op = ClassHDL::OpertorChain.new 
+            new_op = ClassHDL::OpertorChain.new(nil,belong_to_module) 
             new_op.tree.push([rel])
 
             return new_op

data/lib/tdl/examples/10_random/exp_random.sv

@@ -28,9 +28,9 @@ module exp_random #(
 //==========================================================================
 //-------- expression ------------------------------------------------------
 initial begin
-     param_random_b = ($urandom_range(0,99) <= PX);
-     int_random_b = ($urandom_range(1,100) > 34);
-     rd_range = $urandom_range(12,1000);
+    param_random_b = $urandom_range(0,99) <= PX;
+    int_random_b = $urandom_range(1,100) > 34;
+    rd_range = $urandom_range(12,1000);
 end
 
 endmodule

data/lib/tdl/examples/11_test_unit/dve.tcl

@@ -12,6 +12,128 @@ gui_set_time_units 1ps
 ## gui_sg_addsignal -group "$_wave_session_group" { {Sim:tb_Mammo_TCP_sim.g1_test_mac_1g_inst.test_fpga_version_inst.ctrl_udp_rd_version} {Sim:tb_Mammo_TCP_sim.rtl_top.fpga_version_verb.to_ctrl_tap_in_inf} {Sim:tb_Mammo_TCP_sim.rtl_top.fpga_version_verb.ctrl_tap_inf} {Sim:tb_Mammo_TCP_sim.g1_test_mac_1g_inst.tcp_udp_proto_workshop_1G_inst.genblk1[0].tcp_data_stack_top_inst.client_port} }
 ## ==== [add_signal] ===== ##
 
+## -------------- sub_md0_logic -------------------------
+set _wave_session_group_sub_md0_logic sub_md0_logic
+# set _wave_session_group_sub_md0_logic [gui_sg_generate_new_name -seed sub_md0_logic]
+if {[gui_sg_is_group -name "$_wave_session_group_sub_md0_logic"]} {
+    set _wave_session_group_sub_md0_logic [gui_sg_generate_new_name]
+}
+set Group2_sub_md0_logic "$_wave_session_group_sub_md0_logic"
+
+## 添加信号到 group
+gui_sg_addsignal -group "$_wave_session_group_sub_md0_logic" {  {Sim:tb_exp_test_unit.rtl_top.sub_md0_inst.cnt}  }
+## ============== sub_md0_logic =========================
+        
+
+## -------------- sub_md0_interface -------------------------
+set _wave_session_group_sub_md0_interface sub_md0_interface
+# set _wave_session_group_sub_md0_interface [gui_sg_generate_new_name -seed sub_md0_interface]
+if {[gui_sg_is_group -name "$_wave_session_group_sub_md0_interface"]} {
+    set _wave_session_group_sub_md0_interface [gui_sg_generate_new_name]
+}
+set Group2_sub_md0_interface "$_wave_session_group_sub_md0_interface"
+
+## 添加信号到 group
+gui_sg_addsignal -group "$_wave_session_group_sub_md0_interface" {  {Sim:tb_exp_test_unit.rtl_top.sub_md0_inst.axis_in}  }
+## ============== sub_md0_interface =========================
+        
+
+## -------------- sub_md0_default -------------------------
+set _wave_session_group_sub_md0_default sub_md0_default
+# set _wave_session_group_sub_md0_default [gui_sg_generate_new_name -seed sub_md0_default]
+if {[gui_sg_is_group -name "$_wave_session_group_sub_md0_default"]} {
+    set _wave_session_group_sub_md0_default [gui_sg_generate_new_name]
+}
+set Group2_sub_md0_default "$_wave_session_group_sub_md0_default"
+
+## 添加信号到 group
+gui_sg_addsignal -group "$_wave_session_group_sub_md0_default" {  }
+## ============== sub_md0_default =========================
+        
+
+## -------------- sub_md0_default.inter_tf -------------------------
+## set _wave_session_group_sub_md0_default_inter_tf Group1
+## set _wave_session_group_sub_md0_default_inter_tf [gui_sg_generate_new_name -seed inter_tf -parent $_wave_session_group_sub_md0_default ]
+
+set _wave_session_group_sub_md0_default_inter_tf $_wave_session_group_sub_md0_default|
+append _wave_session_group_sub_md0_default_inter_tf inter_tf
+set sub_md0_default|inter_tf "$_wave_session_group_sub_md0_default_inter_tf"
+
+# set Group2_sub_md0_default_inter_tf "$_wave_session_group_sub_md0_default_inter_tf"
+
+## 添加信号到 group
+gui_sg_addsignal -group "$_wave_session_group_sub_md0_default_inter_tf" {  {Sim:tb_exp_test_unit.rtl_top.sub_md0_inst.inter_tf}  }  
+## ============== sub_md0_default.inter_tf =========================
+        
+
+## -------------- sub_md1_default -------------------------
+set _wave_session_group_sub_md1_default sub_md1_default
+# set _wave_session_group_sub_md1_default [gui_sg_generate_new_name -seed sub_md1_default]
+if {[gui_sg_is_group -name "$_wave_session_group_sub_md1_default"]} {
+    set _wave_session_group_sub_md1_default [gui_sg_generate_new_name]
+}
+set Group2_sub_md1_default "$_wave_session_group_sub_md1_default"
+
+## 添加信号到 group
+gui_sg_addsignal -group "$_wave_session_group_sub_md1_default" {  {Sim:tb_exp_test_unit.rtl_top.sub_md1_inst.cnt}  {Sim:tb_exp_test_unit.rtl_top.sub_md1_inst.axis_out}  {Sim:tb_exp_test_unit.rtl_top.sub_md1_inst.enable}  }
+## ============== sub_md1_default =========================
+        
+
+## -------------- sub_md1_inner -------------------------
+set _wave_session_group_sub_md1_inner sub_md1_inner
+# set _wave_session_group_sub_md1_inner [gui_sg_generate_new_name -seed sub_md1_inner]
+if {[gui_sg_is_group -name "$_wave_session_group_sub_md1_inner"]} {
+    set _wave_session_group_sub_md1_inner [gui_sg_generate_new_name]
+}
+set Group2_sub_md1_inner "$_wave_session_group_sub_md1_inner"
+
+## 添加信号到 group
+gui_sg_addsignal -group "$_wave_session_group_sub_md1_inner" {  }
+## ============== sub_md1_inner =========================
+        
+
+## -------------- sub_md1_inner.inter_tf -------------------------
+## set _wave_session_group_sub_md1_inner_inter_tf Group1
+## set _wave_session_group_sub_md1_inner_inter_tf [gui_sg_generate_new_name -seed inter_tf -parent $_wave_session_group_sub_md1_inner ]
+
+set _wave_session_group_sub_md1_inner_inter_tf $_wave_session_group_sub_md1_inner|
+append _wave_session_group_sub_md1_inner_inter_tf inter_tf
+set sub_md1_inner|inter_tf "$_wave_session_group_sub_md1_inner_inter_tf"
+
+# set Group2_sub_md1_inner_inter_tf "$_wave_session_group_sub_md1_inner_inter_tf"
+
+## 添加信号到 group
+gui_sg_addsignal -group "$_wave_session_group_sub_md1_inner_inter_tf" {  {Sim:tb_exp_test_unit.rtl_top.sub_md1_inst.inter_tf}  }  
+## ============== sub_md1_inner.inter_tf =========================
+        
+
+## -------------- exp_test_unit_default -------------------------
+set _wave_session_group_exp_test_unit_default exp_test_unit_default
+# set _wave_session_group_exp_test_unit_default [gui_sg_generate_new_name -seed exp_test_unit_default]
+if {[gui_sg_is_group -name "$_wave_session_group_exp_test_unit_default"]} {
+    set _wave_session_group_exp_test_unit_default [gui_sg_generate_new_name]
+}
+set Group2_exp_test_unit_default "$_wave_session_group_exp_test_unit_default"
+
+## 添加信号到 group
+gui_sg_addsignal -group "$_wave_session_group_exp_test_unit_default" {  }
+## ============== exp_test_unit_default =========================
+        
+
+## -------------- exp_test_unit_default.axis_data_inf -------------------------
+## set _wave_session_group_exp_test_unit_default_axis_data_inf Group1
+## set _wave_session_group_exp_test_unit_default_axis_data_inf [gui_sg_generate_new_name -seed axis_data_inf -parent $_wave_session_group_exp_test_unit_default ]
+
+set _wave_session_group_exp_test_unit_default_axis_data_inf $_wave_session_group_exp_test_unit_default|
+append _wave_session_group_exp_test_unit_default_axis_data_inf axis_data_inf
+set exp_test_unit_default|axis_data_inf "$_wave_session_group_exp_test_unit_default_axis_data_inf"
+
+# set Group2_exp_test_unit_default_axis_data_inf "$_wave_session_group_exp_test_unit_default_axis_data_inf"
+
+## 添加信号到 group
+gui_sg_addsignal -group "$_wave_session_group_exp_test_unit_default_axis_data_inf" {  {Sim:tb_exp_test_unit.rtl_top.axis_data_inf}  }  
+## ============== exp_test_unit_default.axis_data_inf =========================
+        
 
 ## 创建波形窗口
 if {![info exists useOldWindow]} { 
@@ -40,7 +162,33 @@ gui_wv_zoom_timerange -id ${Wave.3} 0 1000000000
 ## gui_list_add_group -id ${Wave.3}  -after ${Group2} [list ${Group2|tx_inf}]
 ## gui_list_expand -id ${Wave.3} tb_Mammo_TCP_sim.rtl_top.fpga_version_verb.ctrl_tap_inf
 ## === [add_signal_wave] === ##
-
+## -------------- Group2_sub_md0_logic -------------------------
+gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_sub_md0_logic}]
+## ============== Group2_sub_md0_logic =========================
+## -------------- Group2_sub_md0_interface -------------------------
+gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_sub_md0_interface}]
+## ============== Group2_sub_md0_interface =========================
+## -------------- Group2_sub_md0_default -------------------------
+gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_sub_md0_default}]
+## ============== Group2_sub_md0_default =========================
+## -------------- sub_md0_default|inter_tf -------------------------
+gui_list_add_group -id ${Wave.3} -after {New Group} [list ${sub_md0_default|inter_tf}]
+## ============== sub_md0_default|inter_tf =========================
+## -------------- Group2_sub_md1_default -------------------------
+gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_sub_md1_default}]
+## ============== Group2_sub_md1_default =========================
+## -------------- Group2_sub_md1_inner -------------------------
+gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_sub_md1_inner}]
+## ============== Group2_sub_md1_inner =========================
+## -------------- sub_md1_inner|inter_tf -------------------------
+gui_list_add_group -id ${Wave.3} -after {New Group} [list ${sub_md1_inner|inter_tf}]
+## ============== sub_md1_inner|inter_tf =========================
+## -------------- Group2_exp_test_unit_default -------------------------
+gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_exp_test_unit_default}]
+## ============== Group2_exp_test_unit_default =========================
+## -------------- exp_test_unit_default|axis_data_inf -------------------------
+gui_list_add_group -id ${Wave.3} -after {New Group} [list ${exp_test_unit_default|axis_data_inf}]
+## ============== exp_test_unit_default|axis_data_inf =========================
 
 gui_seek_criteria -id ${Wave.3} {Any Edge}
 
@@ -57,7 +205,12 @@ gui_list_set_filter -id ${Wave.3} -list { {Buffer 1} {Input 1} {Others 1} {Linka
 gui_list_set_filter -id ${Wave.3} -text {*}
 ##gui_list_set_insertion_bar  -id ${Wave.3} -group ${Group2}  -position in
 ## === [add_bar] === ##
-
+gui_list_set_insertion_bar  -id ${Wave.3} -group ${Group2_sub_md0_logic}  -position in
+gui_list_set_insertion_bar  -id ${Wave.3} -group ${Group2_sub_md0_interface}  -position in
+gui_list_set_insertion_bar  -id ${Wave.3} -group ${Group2_sub_md0_default}  -position in
+gui_list_set_insertion_bar  -id ${Wave.3} -group ${Group2_sub_md1_default}  -position in
+gui_list_set_insertion_bar  -id ${Wave.3} -group ${Group2_sub_md1_inner}  -position in
+gui_list_set_insertion_bar  -id ${Wave.3} -group ${Group2_exp_test_unit_default}  -position in
 
 gui_marker_move -id ${Wave.3} {C1} 560248001
 gui_view_scroll -id ${Wave.3} -vertical -set 35

data/lib/tdl/examples/11_test_unit/exp_test_unit.rb

@@ -22,17 +22,18 @@ TopModule.exp_test_unit(__dir__) do
     end
 
     ## CREATE TEST POINT
-    axis_data_inf.create_tp(' top test point',__FILE__,__LINE__)    - 'axis_data_inf'
+    # axis_data_inf.create_tp(' top test point',__FILE__,__LINE__)    - 'axis_data_inf'
+    axis_data_inf.tracked_by_dve
 
     TdlTestUnit.tu0(__dir__) do 
-        add_to_dve_wave TdlTestPoint.sub_md1.enable_tp
-        add_to_dve_wave(TdlTestPoint.sub_md0.tp_axis_in)
-        add_to_dve_wave(TdlTestPoint.sub_md1.tp_inter_tf)
+        # add_to_dve_wave TdlTestPoint.sub_md1.enable_tp
+        # add_to_dve_wave(TdlTestPoint.sub_md0.tp_axis_in)
+        # add_to_dve_wave(TdlTestPoint.sub_md1.tp_inter_tf)
     
         test_unit_init do 
-            TdlTestPoint.sub_md1.enable_tp.root_ref   <= 1.b1 
+            sub_md1.enable   <= 1.b1 
             initial_exec("#(1us)")
-            TdlTestPoint.sub_md1.enable_tp.root_ref   <= 1.b0 
+            sub_md1.enable   <= 1.b0 
             initial_exec("#(500us)")
         end
     
@@ -40,8 +41,8 @@ TopModule.exp_test_unit(__dir__) do
     
     TdlTestUnit.tu1(__dir__) do 
         # puts TdlTestPoint.sub_md0.tp_cnt.path_refs
-        add_to_dve_wave(TdlTestPoint.sub_md0.tp_cnt)
-        add_to_dve_wave(TdlTestPoint.sub_md1.tp_cnt)
+        # add_to_dve_wave(TdlTestPoint.sub_md0.tp_cnt)
+        # add_to_dve_wave(TdlTestPoint.sub_md1.tp_cnt)
     end
 
     add_test_unit('tu0','tu1')

data/lib/tdl/examples/11_test_unit/exp_test_unit.sv

@@ -5,7 +5,7 @@ _______________________________________
 descript:
 author : Cook.Darwin
 Version: VERA.0.0
-created: xxxx.xx.xx
+created: 2021-03-20 12:08:01 +0800
 madified:
 ***********************************************/
 `timescale 1ns/1ps

data/lib/tdl/examples/11_test_unit/modules/sub_md0.rb

@@ -17,7 +17,10 @@ TdlBuild.sub_md0(__dir__) do
     end
 
     ## CREATE TEST POINT
-    cnt.create_tp('count test point')   - 'tp_cnt'
-    axis_in.create_tp('test point of axis_in',__FILE__,__LINE__)    - 'tp_axis_in'
-    inter_tf.create_tp('inner test point',__FILE__,__LINE__)        - 'tp_inter_tf'
+    # cnt.create_tp('count test point')   - 'tp_cnt'
+    # axis_in.create_tp('test point of axis_in',__FILE__,__LINE__)    - 'tp_axis_in'
+    # inter_tf.create_tp('inner test point',__FILE__,__LINE__)        - 'tp_inter_tf'
+    cnt.tracked_by_dve(:logic)
+    axis_in.tracked_by_dve(:interface)
+    inter_tf.tracked_by_dve
 end

data/lib/tdl/examples/11_test_unit/modules/sub_md0.sv

@@ -5,7 +5,7 @@ _______________________________________
 descript:
 author : Cook.Darwin
 Version: VERA.0.0
-created: xxxx.xx.xx
+created: 2021-03-20 12:08:00 +0800
 madified:
 ***********************************************/
 `timescale 1ns/1ps
@@ -26,15 +26,15 @@ data_inf_c #(.DSIZE(8)) inter_tf (.clock(clock),.rst_n(rst_n)) ;
 
 //==========================================================================
 //-------- expression ------------------------------------------------------
-assign  clock = axis_in.aclk;
-assign  rst_n = axis_in.aresetn;
+assign clock = axis_in.aclk;
+assign rst_n = axis_in.aresetn;
 
 always_ff@(posedge clock,negedge rst_n) begin 
     if(~rst_n)begin
-         cnt <= '0;
+        cnt <= '0;
     end
     else begin
-         cnt <= ( cnt+1'b1);
+        cnt <= (cnt+1'b1);
     end
 end