axi_tdl 0.0.10 → 0.1.0

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Files changed (124) hide show
  1. checksums.yaml +4 -4
  2. data/.github/workflows/gem-push.yml +44 -0
  3. data/.github/workflows/ruby.yml +35 -0
  4. data/.gitignore +3 -1
  5. data/.travis.yml +9 -0
  6. data/Gemfile +4 -0
  7. data/README.EN.md +7 -2
  8. data/README.md +6 -2
  9. data/Rakefile +2 -6
  10. data/axi_tdl.gemspec +3 -4
  11. data/lib/axi/AXI4/axi4_direct_B1.sv +23 -23
  12. data/lib/axi/AXI4/axi4_dpram_cache.sv +33 -33
  13. data/lib/axi/AXI4/axis_to_axi4_wr.rb +1 -0
  14. data/lib/axi/AXI4/axis_to_axi4_wr.sv +20 -20
  15. data/lib/axi/AXI4/packet_partition/axi4_partition_rd_verb.sv +32 -32
  16. data/lib/axi/AXI4/packet_partition/data_inf_partition.rb +2 -0
  17. data/lib/axi/AXI4/packet_partition/data_inf_partition.sv +71 -71
  18. data/lib/axi/AXI4/wide_axis_to_axi4_wr.rb +2 -1
  19. data/lib/axi/AXI4/wide_axis_to_axi4_wr.sv +23 -23
  20. data/lib/axi/AXI_stream/axi_stream_split_channel.rb +7 -1
  21. data/lib/axi/AXI_stream/axis_head_cut_verb.sv +6 -2
  22. data/lib/axi/AXI_stream/axis_insert_copy.rb +18 -4
  23. data/lib/axi/AXI_stream/axis_sim_master_model.rb +28 -0
  24. data/lib/axi/AXI_stream/axis_sim_slaver_model.rb +26 -0
  25. data/lib/axi/AXI_stream/axis_sim_verify_by_coe.sv +101 -0
  26. data/lib/axi/AXI_stream/axis_split_channel_verb.rb +2 -0
  27. data/lib/axi/common/common_ram_sim_wrapper.sv +9 -9
  28. data/lib/axi/common/common_ram_wrapper.sv +12 -12
  29. data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.sv +26 -26
  30. data/lib/axi/data_interface/data_inf_c/data_c_sim_master_model.sv +69 -0
  31. data/lib/axi/data_interface/data_inf_c/data_c_sim_slaver_model.sv +58 -0
  32. data/lib/axi/data_interface/data_inf_c/logic_sim_model.sv +64 -0
  33. data/lib/axi/techbench/tb_axi_stream_split_channel.rb +69 -0
  34. data/lib/axi/techbench/tb_axi_stream_split_channel.sv +149 -0
  35. data/lib/axi/techbench/tb_axis_split_channel_verb.rb +69 -0
  36. data/lib/axi/techbench/tb_axis_split_channel_verb.sv +125 -0
  37. data/lib/axi_tdl.rb +1 -0
  38. data/lib/axi_tdl/version.rb +1 -1
  39. data/lib/tdl/auto_script/autogensdl.rb +16 -5
  40. data/lib/tdl/axi4/axi4_interconnect_verb.rb +4 -2
  41. data/lib/tdl/basefunc.rb +1 -0
  42. data/lib/tdl/class_hdl/hdl_always_comb.rb +4 -3
  43. data/lib/tdl/class_hdl/hdl_always_ff.rb +49 -8
  44. data/lib/tdl/class_hdl/hdl_assign.rb +5 -3
  45. data/lib/tdl/class_hdl/hdl_block_ifelse.rb +11 -9
  46. data/lib/tdl/class_hdl/hdl_foreach.rb +2 -2
  47. data/lib/tdl/class_hdl/hdl_function.rb +4 -2
  48. data/lib/tdl/class_hdl/hdl_generate.rb +5 -4
  49. data/lib/tdl/class_hdl/hdl_initial.rb +11 -10
  50. data/lib/tdl/class_hdl/hdl_module_def.rb +18 -1
  51. data/lib/tdl/class_hdl/hdl_redefine_opertor.rb +35 -14
  52. data/lib/tdl/class_hdl/hdl_struct.rb +1 -1
  53. data/lib/tdl/class_hdl/hdl_verify.rb +1 -1
  54. data/lib/tdl/elements/originclass.rb +6 -1
  55. data/lib/tdl/elements/parameter.rb +1 -1
  56. data/lib/tdl/examples/10_random/exp_random.sv +3 -3
  57. data/lib/tdl/examples/11_test_unit/dve.tcl +155 -2
  58. data/lib/tdl/examples/11_test_unit/exp_test_unit.rb +9 -8
  59. data/lib/tdl/examples/11_test_unit/exp_test_unit.sv +1 -1
  60. data/lib/tdl/examples/11_test_unit/modules/sub_md0.rb +6 -3
  61. data/lib/tdl/examples/11_test_unit/modules/sub_md0.sv +5 -5
  62. data/lib/tdl/examples/11_test_unit/modules/sub_md1.rb +9 -4
  63. data/lib/tdl/examples/11_test_unit/modules/sub_md1.sv +5 -5
  64. data/lib/tdl/examples/11_test_unit/tb_exp_test_unit.sv +1 -3
  65. data/lib/tdl/examples/11_test_unit/tu0.sv +9 -9
  66. data/lib/tdl/examples/11_test_unit/tu1.sv +1 -1
  67. data/lib/tdl/examples/1_define_module/exmple_md.sv +12 -12
  68. data/lib/tdl/examples/2_hdl_class/tmp/always_comb_test.sv +60 -60
  69. data/lib/tdl/examples/2_hdl_class/tmp/always_ff_test.sv +2 -2
  70. data/lib/tdl/examples/2_hdl_class/tmp/case_test.sv +17 -17
  71. data/lib/tdl/examples/2_hdl_class/tmp/head_pkg_module.sv +9 -9
  72. data/lib/tdl/examples/2_hdl_class/tmp/simple_assign_test.sv +1 -1
  73. data/lib/tdl/examples/2_hdl_class/tmp/state_case_test.sv +10 -10
  74. data/lib/tdl/examples/2_hdl_class/tmp/test_foreach.sv +3 -3
  75. data/lib/tdl/examples/2_hdl_class/tmp/test_function.sv +7 -7
  76. data/lib/tdl/examples/2_hdl_class/tmp/test_initial_assert.sv +3 -3
  77. data/lib/tdl/examples/2_hdl_class/tmp/test_module.sv +2 -2
  78. data/lib/tdl/examples/2_hdl_class/tmp/test_module_var.sv +1 -1
  79. data/lib/tdl/examples/2_hdl_class/tmp/test_package.sv +4 -5
  80. data/lib/tdl/examples/2_hdl_class/tmp/test_package2.sv +4 -4
  81. data/lib/tdl/examples/2_hdl_class/tmp/test_struct_function.sv +2 -2
  82. data/lib/tdl/examples/2_hdl_class/tmp/test_vcs_string.sv +1 -1
  83. data/lib/tdl/examples/2_hdl_class/tmp/text_generate.sv +7 -7
  84. data/lib/tdl/examples/4_generate/test_generate.sv +11 -11
  85. data/lib/tdl/examples/5_logic_combin/test_logic_combin.sv +3 -3
  86. data/lib/tdl/examples/7_module_with_package/body_package.sv +3 -4
  87. data/lib/tdl/examples/7_module_with_package/example_pkg.sv +4 -4
  88. data/lib/tdl/examples/7_module_with_package/head_package.sv +3 -4
  89. data/lib/tdl/examples/8_top_module/tb_test_top.sv +1 -2
  90. data/lib/tdl/examples/9_itegration/clock_manage/itgt_module_clock_manage.rb +13 -0
  91. data/lib/tdl/examples/9_itegration/clock_manage/test_clock_bb.sv +34 -0
  92. data/lib/tdl/examples/9_itegration/tb_test_top.sv +2 -2
  93. data/lib/tdl/examples/9_itegration/tb_test_tttop.sv +1 -1
  94. data/lib/tdl/examples/9_itegration/tb_test_tttop_sim.sv +38 -0
  95. data/lib/tdl/examples/9_itegration/test_top.sv +4 -4
  96. data/lib/tdl/examples/9_itegration/test_tttop.sv +4 -4
  97. data/lib/tdl/examples/9_itegration/test_tttop_sim.sv +9 -0
  98. data/lib/tdl/examples/9_itegration/top.rb +1 -0
  99. data/lib/tdl/exlib/axis_eth_ex.rb +95 -0
  100. data/lib/tdl/exlib/axis_verify.rb +264 -0
  101. data/lib/tdl/exlib/clock_reset_verify.rb +29 -0
  102. data/lib/tdl/exlib/dve_tcl.rb +30 -11
  103. data/lib/tdl/exlib/itegration.rb +15 -3
  104. data/lib/tdl/exlib/itegration_verb.rb +166 -129
  105. data/lib/tdl/exlib/logic_verify.rb +88 -0
  106. data/lib/tdl/exlib/test_point.rb +96 -94
  107. data/lib/tdl/exlib/test_point.rb.bak +293 -0
  108. data/lib/tdl/rebuild_ele/ele_base.rb +1 -1
  109. data/lib/tdl/sdlmodule/sdlmodlule_path_db.rb +34 -0
  110. data/lib/tdl/sdlmodule/sdlmodule.rb +18 -14
  111. data/lib/tdl/sdlmodule/sdlmodule_draw.rb +81 -16
  112. data/lib/tdl/sdlmodule/test_unit_module.rb +278 -33
  113. data/lib/tdl/sdlmodule/test_unit_module.rb.bak +143 -0
  114. data/lib/tdl/sdlmodule/top_module.rb +62 -58
  115. data/lib/tdl/sdlmodule/top_module.rb.bak +547 -0
  116. data/lib/tdl/tdl.rb +18 -3
  117. metadata +35 -134
  118. data/Gemfile.lock +0 -28
  119. data/lib/axi/AXI_stream/axi_stream_split_channel.sv +0 -149
  120. data/lib/axi/AXI_stream/axis_head_cut_verc.sv +0 -242
  121. data/lib/axi/AXI_stream/axis_insert_copy.sv +0 -66
  122. data/lib/axi/AXI_stream/axis_pipe_sync_seam.sv +0 -48
  123. data/lib/axi/AXI_stream/axis_rom_contect_sim.sv +0 -113
  124. data/lib/axi/AXI_stream/axis_split_channel_verb.sv +0 -62
data/lib/axi/AXI_stream/axis_head_cut_verc.sv DELETED
@@ -1,242 +0,0 @@
1
- /**********************************************
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- _______________________________________
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- ___________ Cook Darwin __________
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- _______________________________________
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- descript:
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- author : Cook.Darwin
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- Version: VERA.0.0
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- created: xxxx.xx.xx
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- madified:
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- ***********************************************/
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- `timescale 1ns/1ps
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-
13
- module axis_head_cut_verc #(
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- parameter BYTE_BITS = 8,
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- parameter DX = origin_inf.DSIZE/BYTE_BITS
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- )(
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- input [9:0] bytes,
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- axi_stream_inf.slaver origin_inf,
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- axi_stream_inf.master out_inf
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- );
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-
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- //==========================================================================
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- //-------- define ----------------------------------------------------------
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- logic clock;
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- logic rst_n;
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- logic [18-1:0] origin_sync_info[3-1:0] ;
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- logic [18-1:0] origin_sync_info_out[3-1:0] ;
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- logic [10-1:0] bytes_Q ;
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- logic [10-1:0] bytes_QQ ;
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- logic [4-1:0] bytes_x ;
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- logic [4-1:0] bytes_x_Q ;
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- logic [4-1:0] bytes_x_tmp ;
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- logic [4-1:0] bytes_x_sub_nDx ;
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- logic [4-1:0] bytes_x_sub_nDx_tmp ;
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- logic [2-1:0] route_addr ;
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- logic [2-1:0] route_addr_tmp ;
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- logic fifo_wr_en;
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- logic [4-1:0] int_cut_len ;
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- logic [4-1:0] shift_sel_pre ;
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- logic fifo_wr_en_lat;
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- logic [4-1:0] shift_sel ;
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- axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.USIZE(1)) origin_inf_post (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
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- axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.USIZE(1)) sub_origin_inf [2:0] (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
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- axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.USIZE(1)) origin_inf_ss (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
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- axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.USIZE(1)) origin_inf_cut_mix (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
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- axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.USIZE(1)) origin_inf_ss_E0 (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
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- axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.USIZE(1)) origin_inf_ss_E0_CH (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
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- axi_stream_inf #(.DSIZE(out_inf.DSIZE),.USIZE(1)) out_inf_branchR671 (.aclk(out_inf.aclk),.aresetn(out_inf.aresetn),.aclken(1'b1)) ;
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- //==========================================================================
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- //-------- instance --------------------------------------------------------
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- axis_pipe_sync_seam #(
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- .LAT (3 ),
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- .DSIZE (18 )
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- )axis_pipe_sync_seam_inst(
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- /* input */.in_datas (origin_sync_info ),
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- /* output */.out_datas (origin_sync_info_out ),
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- /* axi_stream_inf.slaver */.in_inf (origin_inf ),
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- /* axi_stream_inf.master */.out_inf (origin_inf_post )
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- );
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- axi_stream_interconnect_S2M #(
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- .NUM (3 )
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- )axi_stream_interconnect_S2M_inst(
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- /* input */.addr (route_addr ),
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- /* axi_stream_inf.slaver */.s00 (origin_inf_post ),
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- /* axi_stream_inf.master */.m00 (sub_origin_inf )
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- );
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- common_fifo #(
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- .DEPTH (4 ),
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- .DSIZE (4 )
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- )common_fifo_head_bytesx_inst(
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- /* input */.clock (clock ),
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- /* input */.rst_n (rst_n ),
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- /* input */.wdata (bytes_x ),
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- /* input */.wr_en (fifo_wr_en && (bytes_x!= '0) ),
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- /* output */.rdata (int_cut_len ),
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- /* input */.rd_en ((sub_origin_inf[1].axis_tvalid && sub_origin_inf[1].axis_tready && sub_origin_inf[1].axis_tlast) ),
77
- /* output */.count (/*unused */ ),
78
- /* output */.empty (/*unused */ ),
79
- /* output */.full (/*unused */ )
80
- );
81
- axis_head_cut_verb axis_head_cut_verb_inst(
82
- /* input */.length ({12'd0,int_cut_len} ),
83
- /* axi_stream_inf.slaver */.axis_in (sub_origin_inf[1] ),
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- /* axi_stream_inf.master */.axis_out (origin_inf_ss )
85
- );
86
- axis_append_A1 #(
87
- .MODE ("END" ),
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- .DSIZE (out_inf.DSIZE ),
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- .HEAD_FIELD_LEN (1 ),
90
- .HEAD_FIELD_NAME ("HEAD Filed" ),
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- .END_FIELD_LEN (1 ),
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- .END_FIELD_NAME ("END Filed" )
93
- )axis_append_A1_inst(
94
- /* input */.enable (1'b1 ),
95
- /* input */.head_value (/*unused */ ),
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- /* input */.end_value ('0 ),
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- /* axi_stream_inf.slaver */.origin_in (origin_inf_cut_mix ),
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- /* axi_stream_inf.master */.append_out (origin_inf_ss_E0 )
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- );
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- common_fifo #(
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- .DEPTH (4 ),
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- .DSIZE (4 )
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- )common_fifo_head_nDx_inst(
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- /* input */.clock (clock ),
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- /* input */.rst_n (rst_n ),
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- /* input */.wdata (shift_sel_pre ),
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- /* input */.wr_en (fifo_wr_en_lat ),
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- /* output */.rdata (shift_sel ),
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- /* input */.rd_en (origin_inf_ss_E0.axis_tvalid && origin_inf_ss_E0.axis_tready && origin_inf_ss_E0.axis_tlast ),
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- /* output */.count (/*unused */ ),
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- /* output */.empty (/*unused */ ),
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- /* output */.full (/*unused */ )
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- );
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- axis_connect_pipe_right_shift_verb #(
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- .SHIFT_BYTE_BIT (BYTE_BITS ),
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- .SNUM (DX )
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- )axis_connect_pipe_right_shift_verb_inst(
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- /* input */.shift_sel (shift_sel ),
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- /* axi_stream_inf.slaver */.axis_in (origin_inf_ss_E0 ),
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- /* axi_stream_inf.master */.axis_out (origin_inf_ss_E0_CH )
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- );
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- axis_head_cut_verb last_cut_inst(
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- /* input */.length (16'd1 ),
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- /* axi_stream_inf.slaver */.axis_in (origin_inf_ss_E0_CH ),
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- /* axi_stream_inf.master */.axis_out (out_inf_branchR671 )
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- );
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- //==========================================================================
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- //-------- expression ------------------------------------------------------
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-
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- axi_stream_inf #(.DSIZE(out_inf.DSIZE)) sub_out_inf[2-1:0](.aclk(out_inf.aclk),.aresetn(out_inf.aresetn),.aclken(1'b1));
131
-
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-
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- axis_direct axis_direct_out_inf_inst0 (
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- /* axi_stream_inf.slaver*/ .slaver (sub_origin_inf[0]),
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- /* axi_stream_inf.master*/ .master (sub_out_inf[0])
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- );
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-
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- axis_direct axis_direct_out_inf_inst1 (
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- /* axi_stream_inf.slaver*/ .slaver (out_inf_branchR671),
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- /* axi_stream_inf.master*/ .master (sub_out_inf[1])
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- );
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-
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-
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- axi_stream_inf #(.DSIZE(origin_inf_cut_mix.DSIZE)) sub_origin_inf_cut_mix[2-1:0](.aclk(origin_inf_cut_mix.aclk),.aresetn(origin_inf_cut_mix.aresetn),.aclken(1'b1));
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-
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-
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- axis_direct axis_direct_origin_inf_cut_mix_inst0 (
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- /* axi_stream_inf.slaver*/ .slaver (origin_inf_ss),
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- /* axi_stream_inf.master*/ .master (sub_origin_inf_cut_mix[0])
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- );
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-
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- axis_direct axis_direct_origin_inf_cut_mix_inst1 (
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- /* axi_stream_inf.slaver*/ .slaver (sub_origin_inf[2]),
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- /* axi_stream_inf.master*/ .master (sub_origin_inf_cut_mix[1])
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- );
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- initial begin
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- assert( DX<17)else begin
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- $error("param.DX<%0d> !< 17",DX);
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- $stop;
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- end
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- end
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-
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- assign clock = origin_inf.aclk;
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- assign rst_n = origin_inf.aresetn;
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-
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- always_comb begin
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- bytes_x_tmp = '0;
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- for(integer gvar_cc_1=0;gvar_cc_1<10;gvar_cc_1=gvar_cc_1+1)begin
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- if( bytes<DX*(10-gvar_cc_1))begin
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- bytes_x_tmp = ( ( 10-1)-gvar_cc_1);
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- end
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- end
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- end
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-
175
- assign origin_sync_info[0] = {bytes_x_tmp,bytes_x_tmp,bytes};
176
- assign {bytes_x,bytes_Q} = {origin_sync_info_out[0][13:10],origin_sync_info_out[0][9:0]};
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- assign bytes_x_sub_nDx_tmp = ( bytes_Q-( bytes_x*DX));
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- assign origin_sync_info[1] = {bytes_x_sub_nDx_tmp,bytes_x,bytes_Q};
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- assign {bytes_x_sub_nDx,bytes_x_Q,bytes_QQ} = {origin_sync_info_out[1][17:14],origin_sync_info_out[1][13:10],origin_sync_info_out[1][9:0]};
180
- assign origin_sync_info[2] = {10'd0,route_addr_tmp};
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- assign route_addr = origin_sync_info_out[2][1:0];
182
-
183
- always_comb begin
184
- if( bytes_QQ=='0)begin
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- route_addr_tmp = 2'd0;
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- end
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- else if( bytes_x_Q=='0)begin
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- route_addr_tmp = 2'd2;
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- end
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- else if( bytes_x_sub_nDx=='0)begin
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- route_addr_tmp = 2'd1;
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- end
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- else begin
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- route_addr_tmp = 2'd1;
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- end
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- end
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-
198
- always_ff@(posedge clock,negedge rst_n) begin
199
- if(~rst_n)begin
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- fifo_wr_en <= 1'b0;
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- end
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- else begin
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- fifo_wr_en <= ( origin_inf.axis_tcnt=='0&& origin_inf.axis_tvalid && origin_inf.axis_tready);
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- end
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- end
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-
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- assign shift_sel_pre = ( DX-bytes_x_sub_nDx);
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-
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-
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- //----->> fifo_wr_en LAST DELAY <<------------------
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- latency #(
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- .LAT (2),
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- .DSIZE (1)
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- )fifo_wr_en_lat2_inst(
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- clock,
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- rst_n,
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- fifo_wr_en,
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- fifo_wr_en_lat
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- );
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- //-----<< fifo_wr_en LAST DELAY >>------------------
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-
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-
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- axi_stream_interconnect_M2S_A1 #(
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- //axi_stream_interconnect_M2S_noaddr #(
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- .NUM (2)
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- // .DSIZE (out_inf.DSIZE)
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- )out_inf_M2S_noaddr_inst(
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- /* axi_stream_inf.slaver */ .s00 (sub_out_inf ), //[NUM-1:0],
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- /* axi_stream_inf.master */ .m00 (out_inf) //
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- );
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-
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-
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- axi_stream_interconnect_M2S_A1 #(
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- //axi_stream_interconnect_M2S_noaddr #(
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- .NUM (2)
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- // .DSIZE (origin_inf.DSIZE)
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- )origin_inf_cut_mix_M2S_noaddr_inst(
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- /* axi_stream_inf.slaver */ .s00 (sub_origin_inf_cut_mix ), //[NUM-1:0],
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- /* axi_stream_inf.master */ .m00 (origin_inf_cut_mix) //
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- );
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-
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- endmodule
data/lib/axi/AXI_stream/axis_insert_copy.sv DELETED
@@ -1,66 +0,0 @@
1
- /**********************************************
2
- _______________________________________
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- ___________ Cook Darwin __________
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- _______________________________________
5
- descript:
6
- author : Cook.Darwin
7
- Version: VERA.0.0
8
- created: xxxx.xx.xx
9
- madified:
10
- ***********************************************/
11
- `timescale 1ns/1ps
12
-
13
- module axis_insert_copy (
14
- input [15:0] insert_seed,
15
- input [7:0] insert_len,
16
- axi_stream_inf.slaver in_inf,
17
- axi_stream_inf.master out_inf
18
- );
19
-
20
- //==========================================================================
21
- //-------- define ----------------------------------------------------------
22
- logic clock;
23
- logic rst_n;
24
- logic insert_tri;
25
- axi_stream_inf #(.DSIZE(in_inf.DSIZE),.USIZE(1)) in_inf_valve (.aclk(in_inf.aclk),.aresetn(in_inf.aresetn),.aclken(1'b1)) ;
26
- //==========================================================================
27
- //-------- instance --------------------------------------------------------
28
- axis_connect_pipe axis_connect_pipe_inst(
29
- /* axi_stream_inf.slaver */.axis_in (in_inf_valve ),
30
- /* axi_stream_inf.master */.axis_out (out_inf )
31
- );
32
- //==========================================================================
33
- //-------- expression ------------------------------------------------------
34
- assign clock = in_inf.aclk;
35
- assign rst_n = in_inf.aresetn;
36
-
37
- assign in_inf_valve.axis_tdata = in_inf.axis_tdata;
38
- assign in_inf_valve.axis_tvalid = ( in_inf.axis_tvalid|insert_tri);
39
- assign in_inf_valve.axis_tuser = in_inf.axis_tuser;
40
- assign in_inf_valve.axis_tkeep = in_inf.axis_tkeep;
41
- assign in_inf.axis_tready = ( in_inf_valve.axis_tready&~insert_tri);
42
- assign in_inf_valve.axis_tlast = ( in_inf.axis_tlast&~insert_tri);
43
-
44
- always_ff@(posedge clock,negedge rst_n) begin
45
- if(~rst_n)begin
46
- insert_tri <= 1'b0;
47
- end
48
- else begin
49
- if( insert_seed=='0)begin
50
- if(in_inf.axis_tvalid && in_inf.axis_tready && in_inf.axis_tlast)begin
51
- insert_tri <= 1'b1;
52
- end
53
- else if(in_inf.axis_tvalid && in_inf.axis_tready)begin
54
- insert_tri <= ( in_inf_valve.axis_tcnt>=( insert_len-1'b1));
55
- end
56
- else begin
57
- insert_tri <= insert_tri;
58
- end
59
- end
60
- else begin
61
- insert_tri <= ( in_inf_valve.axis_tcnt>=( insert_seed-1'b1)&& in_inf_valve.axis_tvalid && in_inf_valve.axis_tready && ( in_inf_valve.axis_tcnt<( ( insert_seed+insert_len)-1'b1))&& ~in_inf.axis_tlast);
62
- end
63
- end
64
- end
65
-
66
- endmodule
data/lib/axi/AXI_stream/axis_pipe_sync_seam.sv DELETED
@@ -1,48 +0,0 @@
1
- /**********************************************
2
- _______________________________________
3
- ___________ Cook Darwin __________
4
- _______________________________________
5
- descript:
6
- author : Cook.Darwin
7
- Version: VERA.0.0
8
- created: xxxx.xx.xx
9
- madified:
10
- ***********************************************/
11
- `timescale 1ns/1ps
12
-
13
- module axis_pipe_sync_seam #(
14
- parameter LAT = 4,
15
- parameter DSIZE = 32
16
- )(
17
- input [ DSIZE-1:0] in_datas [LAT-1:0],
18
- output [ DSIZE-1:0] out_datas [LAT-1:0],
19
- axi_stream_inf.slaver in_inf,
20
- axi_stream_inf.master out_inf
21
- );
22
-
23
- //==========================================================================
24
- //-------- define ----------------------------------------------------------
25
-
26
- data_inf_c #(.DSIZE(in_inf.DSIZE+in_inf.KSIZE+1+in_inf.USIZE)) data_in_inf (.clock(in_inf.aclk),.rst_n(in_inf.aresetn)) ;
27
- data_inf_c #(.DSIZE(in_inf.DSIZE+in_inf.KSIZE+1+in_inf.USIZE)) data_out_inf (.clock(in_inf.aclk),.rst_n(in_inf.aresetn)) ;
28
- //==========================================================================
29
- //-------- instance --------------------------------------------------------
30
- data_c_pipe_sync_seam #(
31
- .LAT (LAT ),
32
- .DSIZE (DSIZE )
33
- )data_c_pipe_sync_seam_inst(
34
- /* input */.in_datas (in_datas ),
35
- /* output */.out_datas (out_datas ),
36
- /* data_inf_c.slaver */.in_inf (data_in_inf ),
37
- /* data_inf_c.master */.out_inf (data_out_inf )
38
- );
39
- //==========================================================================
40
- //-------- expression ------------------------------------------------------
41
- assign data_in_inf.data = {>>{in_inf.axis_tuser,in_inf.axis_tkeep,in_inf.axis_tlast,in_inf.axis_tdata}};
42
- assign data_in_inf.valid = in_inf.axis_tvalid;
43
- assign in_inf.axis_tready = data_in_inf.ready;
44
- assign {out_inf.axis_tuser,out_inf.axis_tkeep,out_inf.axis_tlast,out_inf.axis_tdata} = data_out_inf.data;
45
- assign out_inf.axis_tvalid = data_out_inf.valid;
46
- assign data_out_inf.ready = out_inf.axis_tready;
47
-
48
- endmodule
data/lib/axi/AXI_stream/axis_rom_contect_sim.sv DELETED
@@ -1,113 +0,0 @@
1
- /**********************************************
2
- _______________________________________
3
- ___________ Cook Darwin __________
4
- _______________________________________
5
- descript:
6
- author : Cook.Darwin
7
- Version: VERA.0.0
8
- created: xxxx.xx.xx
9
- madified:
10
- ***********************************************/
11
- `timescale 1ns/1ps
12
-
13
- module axis_rom_contect_sim #(
14
- parameter FNUM = 8,
15
- parameter STEP = 1
16
- )(
17
- input [ FNUM-1:0] load_files,
18
- input [4095:0] init_files [FNUM-1:0],
19
- axi_stream_inf.slaver a_axis_zip,
20
- axi_stream_inf.slaver b_axis_zip,
21
- axi_stream_inf.master a_rom_contect_inf,
22
- axi_stream_inf.master b_rom_contect_inf
23
- );
24
-
25
- //==========================================================================
26
- //-------- define ----------------------------------------------------------
27
-
28
- axi_stream_inf #(.DSIZE( a_axis_zip.DSIZE/2),.USIZE(1)) a_axis_unzip (.aclk(a_axis_zip.aclk),.aresetn(a_axis_zip.aresetn),.aclken(1'b1)) ;
29
- axi_stream_inf #(.DSIZE( b_axis_zip.DSIZE/2),.USIZE(1)) b_axis_unzip (.aclk(b_axis_zip.aclk),.aresetn(b_axis_zip.aresetn),.aclken(1'b1)) ;
30
- cm_ram_inf #(.DSIZE(a_rom_contect_inf.DSIZE),.RSIZE(a_axis_zip.DSIZE),.MSIZE(1)) xram_inf();
31
- axi_stream_inf #(.DSIZE(a_rom_contect_inf.DSIZE+ a_axis_zip.DSIZE/2),.USIZE(1)) a_rom_contect_inf_pre (.aclk(a_rom_contect_inf.aclk),.aresetn(a_rom_contect_inf.aresetn),.aclken(1'b1)) ;
32
- axi_stream_inf #(.DSIZE(b_rom_contect_inf.DSIZE+ b_axis_zip.DSIZE/2),.USIZE(1)) b_rom_contect_inf_pre (.aclk(b_rom_contect_inf.aclk),.aresetn(b_rom_contect_inf.aresetn),.aclken(1'b1)) ;
33
- //==========================================================================
34
- //-------- instance --------------------------------------------------------
35
- axis_uncompress_A1 #(
36
- .ASIZE ( a_axis_zip.DSIZE/2 ),
37
- .LSIZE ( a_axis_zip.DSIZE/2 ),
38
- .STEP (STEP )
39
- )axis_uncompress_A1_ainst(
40
- /* axi_stream_inf.slaver */.axis_zip (a_axis_zip ),
41
- /* axi_stream_inf.master */.axis_unzip (a_axis_unzip )
42
- );
43
- axis_uncompress_A1 #(
44
- .ASIZE ( a_axis_zip.DSIZE/2 ),
45
- .LSIZE ( a_axis_zip.DSIZE/2 ),
46
- .STEP (STEP )
47
- )axis_uncompress_A1_binst(
48
- /* axi_stream_inf.slaver */.axis_zip (b_axis_zip ),
49
- /* axi_stream_inf.master */.axis_unzip (b_axis_unzip )
50
- );
51
- common_ram_sim_wrapper #(
52
- .FNUM (FNUM )
53
- )common_ram_wrapper_sim_inst(
54
- /* input */.load_files (load_files ),
55
- /* input */.init_files (init_files ),
56
- /* cm_ram_inf.slaver */.ram_inf (xram_inf )
57
- );
58
- axi_stream_planer #(
59
- .LAT (3 ),
60
- .DSIZE (a_rom_contect_inf.DSIZE ),
61
- .HEAD ("FALSE" )
62
- )axi_stream_planer_ainst(
63
- /* input */.reset (~a_axis_zip.aresetn ),
64
- /* input */.pack_data (xram_inf.doa ),
65
- /* axi_stream_inf.slaver */.axis_in (a_axis_unzip ),
66
- /* axi_stream_inf.master */.axis_out (a_rom_contect_inf_pre )
67
- );
68
- axi_stream_planer #(
69
- .LAT (3 ),
70
- .DSIZE (b_rom_contect_inf.DSIZE ),
71
- .HEAD ("FALSE" )
72
- )axi_stream_planer_binst(
73
- /* input */.reset (~b_axis_zip.aresetn ),
74
- /* input */.pack_data (xram_inf.dob ),
75
- /* axi_stream_inf.slaver */.axis_in (b_axis_unzip ),
76
- /* axi_stream_inf.master */.axis_out (b_rom_contect_inf_pre )
77
- );
78
- //==========================================================================
79
- //-------- expression ------------------------------------------------------
80
- initial begin
81
- assert( a_axis_zip.DSIZE==b_axis_zip.DSIZE)else begin
82
- $error("a_axis_zip.DSIZE<%0d> must equal b_axis_zip.DSIZE<%0d>",a_axis_zip.DSIZE,b_axis_zip.DSIZE);
83
- $stop;
84
- end
85
- assert( a_rom_contect_inf.DSIZE==b_rom_contect_inf.DSIZE)else begin
86
- $error("a_rom_contect_inf.DSIZE<%0d>==b_rom_contect_inf.DSIZE<%0d>",a_rom_contect_inf.DSIZE,b_rom_contect_inf.DSIZE);
87
- $stop;
88
- end
89
- end
90
-
91
- assign xram_inf.addra = a_axis_unzip.axis_tdata;
92
- assign xram_inf.dia = '0;
93
- assign xram_inf.wea = '0;
94
- assign xram_inf.ena = 1'b1;
95
- assign xram_inf.clka = a_axis_zip.aclk;
96
- assign xram_inf.rsta = ~a_axis_zip.aresetn;
97
- assign xram_inf.addrb = b_axis_unzip.axis_tdata;
98
- assign xram_inf.dib = '0;
99
- assign xram_inf.web = '0;
100
- assign xram_inf.enb = 1'b1;
101
- assign xram_inf.clkb = b_axis_zip.aclk;
102
- assign xram_inf.rstb = ~b_axis_zip.aresetn;
103
-
104
- assign a_rom_contect_inf.axis_tdata = a_rom_contect_inf_pre.axis_tdata[ a_rom_contect_inf.DSIZE-1:0];
105
- assign a_rom_contect_inf.axis_tvalid = a_rom_contect_inf_pre.axis_tvalid;
106
- assign a_rom_contect_inf.axis_tlast = a_rom_contect_inf_pre.axis_tlast;
107
- assign a_rom_contect_inf_pre.axis_tready = a_rom_contect_inf.axis_tready;
108
- assign b_rom_contect_inf.axis_tdata = b_rom_contect_inf_pre.axis_tdata[ b_rom_contect_inf.DSIZE-1:0];
109
- assign b_rom_contect_inf.axis_tvalid = b_rom_contect_inf_pre.axis_tvalid;
110
- assign b_rom_contect_inf.axis_tlast = b_rom_contect_inf_pre.axis_tlast;
111
- assign b_rom_contect_inf_pre.axis_tready = b_rom_contect_inf.axis_tready;
112
-
113
- endmodule