axi_tdl 0.0.10 → 0.1.0

data/lib/axi/AXI4/packet_partition/axi4_partition_rd_verb.sv

@@ -44,49 +44,49 @@ common_fifo #(
     .DEPTH (6 ),
     .DSIZE (1 )
 )common_fifo_inst(
-/* input  */.clock (clock                                                              ),
-/* input  */.rst_n (rst_n                                                              ),
-/* input  */.wdata (partition_pulse_inf.data                                           ),
-/* input  */.wr_en (partition_pulse_inf.valid && partition_pulse_inf.ready             ),
-/* output */.rdata (                                                                   ),
-/* input  */.rd_en ( (short_inf.axi_rvalid & short_inf.axi_rready)&short_inf.axi_rlast ),
-/* output */.count (/*unused */                                                        ),
-/* output */.empty (fifo_empty                                                         ),
-/* output */.full  (fifo_full                                                          )
+/* input  */.clock (clock                                                             ),
+/* input  */.rst_n (rst_n                                                             ),
+/* input  */.wdata (partition_pulse_inf.data                                          ),
+/* input  */.wr_en (partition_pulse_inf.valid && partition_pulse_inf.ready            ),
+/* output */.rdata (                                                                  ),
+/* input  */.rd_en ((short_inf.axi_rvalid & short_inf.axi_rready)&short_inf.axi_rlast ),
+/* output */.count (/*unused */                                                       ),
+/* output */.empty (fifo_empty                                                        ),
+/* output */.full  (fifo_full                                                         )
 );
 //==========================================================================
 //-------- expression ------------------------------------------------------
-assign  clock = long_inf.axi_aclk;
-assign  rst_n = long_inf.axi_aresetn;
+assign clock = long_inf.axi_aclk;
+assign rst_n = long_inf.axi_aresetn;
 
-assign  pre_partition_data_inf.data = {long_inf.axi_arid,long_inf.axi_araddr,long_inf.axi_arlen};
-assign  pre_partition_data_inf.valid = long_inf.axi_arvalid;
-assign  long_inf.axi_arready = pre_partition_data_inf.ready;
-assign  {short_inf.axi_arid,short_inf.axi_araddr,short_inf.axi_arlen} = post_partition_data_inf.data;
-assign  short_inf.axi_arvalid = post_partition_data_inf.valid;
-assign  post_partition_data_inf.ready = short_inf.axi_arready;
+assign pre_partition_data_inf.data = {long_inf.axi_arid,long_inf.axi_araddr,long_inf.axi_arlen};
+assign pre_partition_data_inf.valid = long_inf.axi_arvalid;
+assign long_inf.axi_arready = pre_partition_data_inf.ready;
+assign {short_inf.axi_arid,short_inf.axi_araddr,short_inf.axi_arlen} = post_partition_data_inf.data;
+assign short_inf.axi_arvalid = post_partition_data_inf.valid;
+assign post_partition_data_inf.ready = short_inf.axi_arready;
 
-assign  partition_pulse_inf.ready = ~fifo_full;
+assign partition_pulse_inf.ready = ~fifo_full;
 
-assign  short_inf.axi_arsize = long_inf.axi_arsize;
-assign  short_inf.axi_arburst = long_inf.axi_arburst;
-assign  short_inf.axi_arlock = long_inf.axi_arlock;
-assign  short_inf.axi_arcache = long_inf.axi_arcache;
-assign  short_inf.axi_arprot = long_inf.axi_arprot;
-assign  short_inf.axi_arqos = long_inf.axi_arqos;
-assign  long_inf.axi_rid = short_inf.axi_rid[ long_inf.IDSIZE-1:0];
-assign  long_inf.axi_rdata = short_inf.axi_rdata;
-assign  long_inf.axi_rresp = short_inf.axi_rresp;
-assign  long_inf.axi_rlast = ( short_inf.axi_rlast&fifo_empty);
-assign  long_inf.axi_rvalid = short_inf.axi_rvalid;
-assign  short_inf.axi_rready = long_inf.axi_rready;
+assign short_inf.axi_arsize = long_inf.axi_arsize;
+assign short_inf.axi_arburst = long_inf.axi_arburst;
+assign short_inf.axi_arlock = long_inf.axi_arlock;
+assign short_inf.axi_arcache = long_inf.axi_arcache;
+assign short_inf.axi_arprot = long_inf.axi_arprot;
+assign short_inf.axi_arqos = long_inf.axi_arqos;
+assign long_inf.axi_rid = short_inf.axi_rid[long_inf.IDSIZE-1:0];
+assign long_inf.axi_rdata = short_inf.axi_rdata;
+assign long_inf.axi_rresp = short_inf.axi_rresp;
+assign long_inf.axi_rlast = short_inf.axi_rlast&fifo_empty;
+assign long_inf.axi_rvalid = short_inf.axi_rvalid;
+assign short_inf.axi_rready = long_inf.axi_rready;
 
 always_ff@(posedge clock,negedge rst_n) begin 
     if(~rst_n)begin
-         wait_last_inf.ready <= 1'b0;
+        wait_last_inf.ready <= 1'b0;
     end
     else begin
-         wait_last_inf.ready <= ( ( long_inf.axi_rvalid&long_inf.axi_rready)&long_inf.axi_rlast);
+        wait_last_inf.ready <= ((long_inf.axi_rvalid&long_inf.axi_rready)&long_inf.axi_rlast);
     end
 end
 

data/lib/axi/AXI4/packet_partition/data_inf_partition.rb

@@ -1,3 +1,5 @@
+require_hdl 'common_fifo.sv'
+
 TdlBuild.data_inf_partition(__dir__) do
     parameter.PLEN          128 
     parameter.LSIZE         8

data/lib/axi/AXI4/packet_partition/data_inf_partition.sv

@@ -29,9 +29,9 @@ logic  rst_n;
 logic tail_len;
 logic one_long_stream;
 logic fifo_wr;
-logic [ IDSIZE+4-1:0]  curr_id ;
+logic [IDSIZE+4-1:0]  curr_id ;
 logic [LSIZE-1:0]  curr_length ;
-logic [ ( data_in.DSIZE-IDSIZE)-LSIZE-1:0]  curr_addr ;
+logic [(data_in.DSIZE-IDSIZE)-LSIZE-1:0]  curr_addr ;
 logic [LSIZE-1:0]  wr_length ;
 (* MARK_DEBUG="true" *)(* dont_touch="true" *)logic fifo_full;
 (* MARK_DEBUG="true" *)(* dont_touch="true" *)logic fifo_empty;
@@ -68,21 +68,21 @@ typedef enum {
 } SE_STATE_ps;
 SE_STATE_ps CSTATE_ps,NSTATE_ps;
 initial begin
-    assert( ( data_in.DSIZE+4)==data_out.DSIZE)else begin
-         $error("data_in.DSIZE<%d> != data_out.DSIZE<%d>",data_in.DSIZE,data_out.DSIZE);
-         $stop;
+    assert((data_in.DSIZE+4)==data_out.DSIZE)else begin
+        $error("data_in.DSIZE<%d> != data_out.DSIZE<%d>",data_in.DSIZE,data_out.DSIZE);
+        $stop;
     end
 end
 
-assign  clock = data_in.clock;
-assign  rst_n = data_in.rst_n;
+assign clock = data_in.clock;
+assign rst_n = data_in.rst_n;
 
 always_ff@(posedge clock,negedge rst_n) begin 
     if(~rst_n)begin
-         CSTATE_ps <= IDLE;
+        CSTATE_ps <= IDLE;
     end
     else begin
-         CSTATE_ps <= NSTATE_ps;
+        CSTATE_ps <= NSTATE_ps;
     end
 end
 
@@ -90,85 +90,85 @@ always_comb begin
     case(CSTATE_ps) 
         IDLE:begin 
             if(data_in.valid && data_in.ready)begin
-                 NSTATE_ps = LOCK;
+                NSTATE_ps = LOCK;
             end
             else begin
-                 NSTATE_ps = IDLE;
+                NSTATE_ps = IDLE;
             end
         end
         LOCK:begin 
             if(one_long_stream)begin
-                 NSTATE_ps = Pl;
+                NSTATE_ps = Pl;
             end
             else begin
-                 NSTATE_ps = WAT_PP;
+                NSTATE_ps = WAT_PP;
             end
         end
         WAT_PP:begin 
             if(partition_pulse_inf.valid && partition_pulse_inf.ready)begin
-                 NSTATE_ps = Px;
+                NSTATE_ps = Px;
             end
             else begin
-                 NSTATE_ps = WAT_PP;
+                NSTATE_ps = WAT_PP;
             end
         end
         Px:begin 
             if(~fifo_full)begin
-                 NSTATE_ps = HOLD;
+                NSTATE_ps = HOLD;
             end
             else begin
-                 NSTATE_ps = Px;
+                NSTATE_ps = Px;
             end
         end
         HOLD:begin 
             if(tail_len)begin
-                 NSTATE_ps = Pl;
+                NSTATE_ps = Pl;
             end
             else begin
-                 NSTATE_ps = WAT_PP;
+                NSTATE_ps = WAT_PP;
             end
         end
         Pl:begin 
             if(~fifo_full)begin
-                 NSTATE_ps = DONE;
+                NSTATE_ps = DONE;
             end
             else begin
-                 NSTATE_ps = Pl;
+                NSTATE_ps = Pl;
             end
         end
         DONE:begin 
             if(fifo_empty)begin
-                 NSTATE_ps = WAIT;
+                NSTATE_ps = WAIT;
             end
             else begin
-                 NSTATE_ps = DONE;
+                NSTATE_ps = DONE;
             end
         end
         WAIT:begin 
             if(wait_last_inf.valid && wait_last_inf.ready)begin
-                 NSTATE_ps = IDLE;
+                NSTATE_ps = IDLE;
             end
             else begin
-                 NSTATE_ps = WAIT;
+                NSTATE_ps = WAIT;
             end
         end
         default:begin 
-             NSTATE_ps = IDLE;
+            NSTATE_ps = IDLE;
         end
     endcase
 end
 
 always_ff@(posedge clock,negedge rst_n) begin 
     if(~rst_n)begin
-         data_in.ready <= 1'b0;
+        data_in.ready <= 1'b0;
     end
     else begin
         case(NSTATE_ps) 
             IDLE:begin 
-                 data_in.ready <= 1'b1;
+                data_in.ready <= 1'b1;
             end
             default:begin 
-                 data_in.ready <= 1'b0;
+                data_in.ready <= 1'b0;
             end
         endcase
     end
@@ -176,23 +176,23 @@ end
 
 always_ff@(posedge clock,negedge rst_n) begin 
     if(~rst_n)begin
-         curr_addr <= '0;
-         curr_length <= '0;
+        curr_addr <= '0;
+        curr_length <= '0;
     end
     else begin
         case(NSTATE_ps) 
             LOCK:begin 
-                 one_long_stream <= data_in.data[ LSIZE-1:0]< PLEN;
-                 curr_id[ IDSIZE+4-1:IDSIZE] <= 2'b00;
-                 {curr_id[ IDSIZE-1:0],curr_addr,curr_length} <= data_in.data;
+                one_long_stream <= data_in.data[LSIZE-1:0]<PLEN;
+                curr_id[IDSIZE+4-1:IDSIZE] <= 2'b00;
+                {curr_id[IDSIZE-1:0],curr_addr,curr_length} <= data_in.data;
             end
             HOLD:begin 
-                 curr_length <= ( curr_length-PLEN);
-                 curr_addr <= ( curr_addr+( ADDR_STEP*PLEN/1024));
-                 curr_id[ IDSIZE+4-1:IDSIZE] <= ( curr_id[ IDSIZE+2-1:IDSIZE]+1'b1);
+                curr_length <= (curr_length-PLEN);
+                curr_addr <= (curr_addr+(ADDR_STEP*PLEN/1024));
+                curr_id[IDSIZE+4-1:IDSIZE] <= (curr_id[IDSIZE+2-1:IDSIZE]+1'b1);
             end
             IDLE,DONE:begin 
-                 one_long_stream <= 1'b0;
+                one_long_stream <= 1'b0;
             end
         endcase
     end
@@ -200,19 +200,19 @@ end
 
 always_ff@(posedge clock,negedge rst_n) begin 
     if(~rst_n)begin
-         tail_len <= 1'b0;
+        tail_len <= 1'b0;
     end
     else begin
         case(NSTATE_ps) 
             LOCK:begin 
-                 tail_len <= ( data_in.data[ LSIZE-1:0]<PLEN);
+                tail_len <= (data_in.data[LSIZE-1:0]<PLEN);
             end
             HOLD:begin 
-                if( curr_length<( PLEN*2-0))begin
-                     tail_len <= 1'b1;
+                if(curr_length<(PLEN*2-0))begin
+                    tail_len <= 1'b1;
                 end
                 else begin
-                     tail_len <= 1'b0;
+                    tail_len <= 1'b0;
                 end
             end
         endcase
@@ -221,21 +221,21 @@ end
 
 always_ff@(posedge clock,negedge rst_n) begin 
     if(~rst_n)begin
-         wr_length <= '0;
-         fifo_wr <= 1'b0;
+        wr_length <= '0;
+        fifo_wr <= 1'b0;
     end
     else begin
         case(NSTATE_ps) 
             Px:begin 
-                 wr_length <= ( PLEN-1'b1);
-                 fifo_wr <= 1'b1;
+                wr_length <= (PLEN-1'b1);
+                fifo_wr <= 1'b1;
             end
             Pl:begin 
-                 wr_length <= curr_length;
-                 fifo_wr <= 1'b1;
+                wr_length <= curr_length;
+                fifo_wr <= 1'b1;
             end
             default:begin 
-                 fifo_wr <= 1'b0;
+                fifo_wr <= 1'b0;
             end
         endcase
     end
@@ -243,39 +243,39 @@ end
 
 always_ff@(posedge clock,negedge rst_n) begin 
     if(~rst_n)begin
-         partition_pulse_inf.valid <= 1'b0;
-         partition_pulse_inf.data <= '0;
+        partition_pulse_inf.valid <= 1'b0;
+        partition_pulse_inf.data <= '0;
     end
     else begin
         case(NSTATE_ps) 
             WAT_PP:begin 
-                 partition_pulse_inf.valid <= 1'b1;
-                 partition_pulse_inf.data <= '0;
+                partition_pulse_inf.valid <= 1'b1;
+                partition_pulse_inf.data <= '0;
             end
             default:begin 
-                 partition_pulse_inf.valid <= 1'b0;
-                 partition_pulse_inf.data <= '0;
+                partition_pulse_inf.valid <= 1'b0;
+                partition_pulse_inf.data <= '0;
             end
         endcase
     end
 end
 
-assign  data_out.valid = ~fifo_empty;
+assign data_out.valid = ~fifo_empty;
 
 always_ff@(posedge clock,negedge rst_n) begin 
     if(~rst_n)begin
-         wait_last_inf.data <= '0;
-         wait_last_inf.valid <= '0;
+        wait_last_inf.data <= '0;
+        wait_last_inf.valid <= '0;
     end
     else begin
         case(NSTATE_ps) 
             WAIT:begin 
-                 wait_last_inf.data <= '0;
-                 wait_last_inf.valid <= 1'b1;
+                wait_last_inf.data <= '0;
+                wait_last_inf.valid <= 1'b1;
             end
             default:begin 
-                 wait_last_inf.data <= '0;
-                 wait_last_inf.valid <= 1'b0;
+                wait_last_inf.data <= '0;
+                wait_last_inf.valid <= 1'b0;
             end
         endcase
     end
@@ -283,22 +283,22 @@ end
 
 always_ff@(posedge clock,negedge rst_n) begin 
     if(~rst_n)begin
-         st5_cnt <= '0;
-         track_st5 <= 1'b0;
+        st5_cnt <= '0;
+        track_st5 <= 1'b0;
     end
     else begin
         case(NSTATE_ps) 
             WAT_PP:begin 
-                 st5_cnt <= ( st5_cnt+1'b1);
-                 track_st5 <= st5_cnt> 10'd200;
+                st5_cnt <= (st5_cnt+1'b1);
+                track_st5 <= st5_cnt>10'd200;
             end
             WAIT:begin 
-                 st5_cnt <= ( st5_cnt+1'b1);
-                 track_st5 <= st5_cnt> 10'd1000;
+                st5_cnt <= (st5_cnt+1'b1);
+                track_st5 <= st5_cnt>10'd1000;
             end
             default:begin 
-                 st5_cnt <= '0;
-                 track_st5 <= 1'b0;
+                st5_cnt <= '0;
+                track_st5 <= 1'b0;
             end
         endcase
     end

data/lib/axi/AXI4/wide_axis_to_axi4_wr.rb

@@ -1,5 +1,6 @@
 # require_relative "../prj_lib"
-require_hdl File.join(__dir__,"../AXI_stream/axis_length_split_with_addr.sv")
+require_hdl "axis_length_split_with_addr.sv"
+require_hdl 'axi_stream_wide_fifo.sv'
 new_m = SdlModule.new(name:File.basename(__FILE__,".rb"),out_sv_path:__dir__)
 new_m.target_class = AxiStream
 

data/lib/axi/AXI4/wide_axis_to_axi4_wr.sv

@@ -56,7 +56,7 @@ logic stream_en;
 axi_stream_inf #(.DSIZE(axis_in.DSIZE),.USIZE(1)) split_out (.aclk(axis_in.aclk),.aresetn(axis_in.aresetn),.aclken(1'b1)) ;
 axi_stream_inf #(.DSIZE(axis_in.DSIZE),.USIZE(1)) fifo_axis (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
 axi_stream_inf #(.DSIZE(axi_wr.IDSIZE + axi_wr.ASIZE + axi_wr.LSIZE),.USIZE(1)) id_add_len_in (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
-axi_inf #(.DSIZE(axi_wr.DSIZE),.IDSIZE(axi_wr.IDSIZE),.ASIZE(axi_wr.ASIZE),.LSIZE(axi_wr.LSIZE),.MODE(axi_wr.MODE),.ADDR_STEP(axi_wr.ADDR_STEP)) axi_wr_vcs_cp_R1842 (.axi_aclk(axi_wr.axi_aclk),.axi_aresetn(axi_wr.axi_aresetn)) ;
+axi_inf #(.DSIZE(axi_wr.DSIZE),.IDSIZE(axi_wr.IDSIZE),.ASIZE(axi_wr.ASIZE),.LSIZE(axi_wr.LSIZE),.MODE(axi_wr.MODE),.ADDR_STEP(axi_wr.ADDR_STEP)) axi_wr_vcs_cp_R236 (.axi_aclk(axi_wr.axi_aclk),.axi_aresetn(axi_wr.axi_aresetn)) ;
 axi_stream_inf #(.DSIZE(axis_in.DSIZE),.USIZE(1)) pipe_axis (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
 //==========================================================================
 //-------- instance --------------------------------------------------------
@@ -91,16 +91,16 @@ independent_clock_fifo #(
 /* output */.full     (fifo_full                                                                )
 );
 axi4_wr_auxiliary_gen_without_resp axi4_wr_auxiliary_gen_without_resp_inst(
-/* output                        */.stream_en     (stream_en           ),
-/* axi_stream_inf.slaver         */.id_add_len_in (id_add_len_in       ),
-/* axi_inf.master_wr_aux_no_resp */.axi_wr_aux    (axi_wr_vcs_cp_R1842 )
+/* output                        */.stream_en     (stream_en          ),
+/* axi_stream_inf.slaver         */.id_add_len_in (id_add_len_in      ),
+/* axi_inf.master_wr_aux_no_resp */.axi_wr_aux    (axi_wr_vcs_cp_R236 )
 );
 vcs_axi4_comptable #(
     .ORIGIN ("master_wr_aux_no_resp" ),
     .TO     ("master_wr"             )
-)vcs_axi4_comptable_axi_wr_aux_R1910_axi_wr_inst(
-/* input  */.origin (axi_wr_vcs_cp_R1842 ),
-/* output */.to     (axi_wr              )
+)vcs_axi4_comptable_axi_wr_aux_R372_axi_wr_inst(
+/* input  */.origin (axi_wr_vcs_cp_R236 ),
+/* output */.to     (axi_wr             )
 );
 axis_valve_with_pipe #(
     .MODE ("OUT" )
@@ -111,30 +111,30 @@ axis_valve_with_pipe #(
 );
 //==========================================================================
 //-------- expression ------------------------------------------------------
-always_ff@(posedge axis_in.aclk,negedge axis_in.aresetn) begin 
+always@(posedge axis_in.aclk,negedge axis_in.aresetn) begin 
     if(~axis_in.aresetn)begin
-         id <= 0;
+        id <= 0;
     end
     else if(split_out.axis_tvalid && split_out.axis_tready && split_out.axis_tlast)begin
-         id <= ( id+1);
+        id <= (id+1);
     end
     else begin
-         id <= id;
+        id <= id;
     end
 end
 
-assign  addr_s = addr_cur;
-assign  len_s = split_out.axis_tcnt;
-assign  id_add_len_in.axis_tvalid = ~fifo_empty;
-assign  id_add_len_in.axis_tdata = fifo_rdata;
-assign  id_add_len_in.axis_tlast = "1'b1";
-assign  fifo_rd_en = id_add_len_in.axis_tready;
+assign addr_s = addr_cur;
+assign len_s = split_out.axis_tcnt;
+assign id_add_len_in.axis_tvalid = ~fifo_empty;
+assign id_add_len_in.axis_tdata = fifo_rdata;
+assign id_add_len_in.axis_tlast = "1'b1";
+assign fifo_rd_en = id_add_len_in.axis_tready;
 
-assign  axi_wr.axi_wdata = pipe_axis.axis_tdata;
-assign  axi_wr.axi_wstrb = ~pipe_axis.axis_tkeep;
-assign  axi_wr.axi_wvalid = pipe_axis.axis_tvalid;
-assign  axi_wr.axi_wlast = pipe_axis.axis_tlast;
-assign  pipe_axis.axis_tready = axi_wr.axi_wready;
-assign  axi_wr.axi_bready = 1'b1;
+assign axi_wr.axi_wdata = pipe_axis.axis_tdata;
+assign axi_wr.axi_wstrb = ~pipe_axis.axis_tkeep;
+assign axi_wr.axi_wvalid = pipe_axis.axis_tvalid;
+assign axi_wr.axi_wlast = pipe_axis.axis_tlast;
+assign pipe_axis.axis_tready = axi_wr.axi_wready;
+assign axi_wr.axi_bready = 1'b1;
 
 endmodule