axi_tdl 0.0.10 → 0.1.0

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Files changed (124) hide show
  1. checksums.yaml +4 -4
  2. data/.github/workflows/gem-push.yml +44 -0
  3. data/.github/workflows/ruby.yml +35 -0
  4. data/.gitignore +3 -1
  5. data/.travis.yml +9 -0
  6. data/Gemfile +4 -0
  7. data/README.EN.md +7 -2
  8. data/README.md +6 -2
  9. data/Rakefile +2 -6
  10. data/axi_tdl.gemspec +3 -4
  11. data/lib/axi/AXI4/axi4_direct_B1.sv +23 -23
  12. data/lib/axi/AXI4/axi4_dpram_cache.sv +33 -33
  13. data/lib/axi/AXI4/axis_to_axi4_wr.rb +1 -0
  14. data/lib/axi/AXI4/axis_to_axi4_wr.sv +20 -20
  15. data/lib/axi/AXI4/packet_partition/axi4_partition_rd_verb.sv +32 -32
  16. data/lib/axi/AXI4/packet_partition/data_inf_partition.rb +2 -0
  17. data/lib/axi/AXI4/packet_partition/data_inf_partition.sv +71 -71
  18. data/lib/axi/AXI4/wide_axis_to_axi4_wr.rb +2 -1
  19. data/lib/axi/AXI4/wide_axis_to_axi4_wr.sv +23 -23
  20. data/lib/axi/AXI_stream/axi_stream_split_channel.rb +7 -1
  21. data/lib/axi/AXI_stream/axis_head_cut_verb.sv +6 -2
  22. data/lib/axi/AXI_stream/axis_insert_copy.rb +18 -4
  23. data/lib/axi/AXI_stream/axis_sim_master_model.rb +28 -0
  24. data/lib/axi/AXI_stream/axis_sim_slaver_model.rb +26 -0
  25. data/lib/axi/AXI_stream/axis_sim_verify_by_coe.sv +101 -0
  26. data/lib/axi/AXI_stream/axis_split_channel_verb.rb +2 -0
  27. data/lib/axi/common/common_ram_sim_wrapper.sv +9 -9
  28. data/lib/axi/common/common_ram_wrapper.sv +12 -12
  29. data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.sv +26 -26
  30. data/lib/axi/data_interface/data_inf_c/data_c_sim_master_model.sv +69 -0
  31. data/lib/axi/data_interface/data_inf_c/data_c_sim_slaver_model.sv +58 -0
  32. data/lib/axi/data_interface/data_inf_c/logic_sim_model.sv +64 -0
  33. data/lib/axi/techbench/tb_axi_stream_split_channel.rb +69 -0
  34. data/lib/axi/techbench/tb_axi_stream_split_channel.sv +149 -0
  35. data/lib/axi/techbench/tb_axis_split_channel_verb.rb +69 -0
  36. data/lib/axi/techbench/tb_axis_split_channel_verb.sv +125 -0
  37. data/lib/axi_tdl.rb +1 -0
  38. data/lib/axi_tdl/version.rb +1 -1
  39. data/lib/tdl/auto_script/autogensdl.rb +16 -5
  40. data/lib/tdl/axi4/axi4_interconnect_verb.rb +4 -2
  41. data/lib/tdl/basefunc.rb +1 -0
  42. data/lib/tdl/class_hdl/hdl_always_comb.rb +4 -3
  43. data/lib/tdl/class_hdl/hdl_always_ff.rb +49 -8
  44. data/lib/tdl/class_hdl/hdl_assign.rb +5 -3
  45. data/lib/tdl/class_hdl/hdl_block_ifelse.rb +11 -9
  46. data/lib/tdl/class_hdl/hdl_foreach.rb +2 -2
  47. data/lib/tdl/class_hdl/hdl_function.rb +4 -2
  48. data/lib/tdl/class_hdl/hdl_generate.rb +5 -4
  49. data/lib/tdl/class_hdl/hdl_initial.rb +11 -10
  50. data/lib/tdl/class_hdl/hdl_module_def.rb +18 -1
  51. data/lib/tdl/class_hdl/hdl_redefine_opertor.rb +35 -14
  52. data/lib/tdl/class_hdl/hdl_struct.rb +1 -1
  53. data/lib/tdl/class_hdl/hdl_verify.rb +1 -1
  54. data/lib/tdl/elements/originclass.rb +6 -1
  55. data/lib/tdl/elements/parameter.rb +1 -1
  56. data/lib/tdl/examples/10_random/exp_random.sv +3 -3
  57. data/lib/tdl/examples/11_test_unit/dve.tcl +155 -2
  58. data/lib/tdl/examples/11_test_unit/exp_test_unit.rb +9 -8
  59. data/lib/tdl/examples/11_test_unit/exp_test_unit.sv +1 -1
  60. data/lib/tdl/examples/11_test_unit/modules/sub_md0.rb +6 -3
  61. data/lib/tdl/examples/11_test_unit/modules/sub_md0.sv +5 -5
  62. data/lib/tdl/examples/11_test_unit/modules/sub_md1.rb +9 -4
  63. data/lib/tdl/examples/11_test_unit/modules/sub_md1.sv +5 -5
  64. data/lib/tdl/examples/11_test_unit/tb_exp_test_unit.sv +1 -3
  65. data/lib/tdl/examples/11_test_unit/tu0.sv +9 -9
  66. data/lib/tdl/examples/11_test_unit/tu1.sv +1 -1
  67. data/lib/tdl/examples/1_define_module/exmple_md.sv +12 -12
  68. data/lib/tdl/examples/2_hdl_class/tmp/always_comb_test.sv +60 -60
  69. data/lib/tdl/examples/2_hdl_class/tmp/always_ff_test.sv +2 -2
  70. data/lib/tdl/examples/2_hdl_class/tmp/case_test.sv +17 -17
  71. data/lib/tdl/examples/2_hdl_class/tmp/head_pkg_module.sv +9 -9
  72. data/lib/tdl/examples/2_hdl_class/tmp/simple_assign_test.sv +1 -1
  73. data/lib/tdl/examples/2_hdl_class/tmp/state_case_test.sv +10 -10
  74. data/lib/tdl/examples/2_hdl_class/tmp/test_foreach.sv +3 -3
  75. data/lib/tdl/examples/2_hdl_class/tmp/test_function.sv +7 -7
  76. data/lib/tdl/examples/2_hdl_class/tmp/test_initial_assert.sv +3 -3
  77. data/lib/tdl/examples/2_hdl_class/tmp/test_module.sv +2 -2
  78. data/lib/tdl/examples/2_hdl_class/tmp/test_module_var.sv +1 -1
  79. data/lib/tdl/examples/2_hdl_class/tmp/test_package.sv +4 -5
  80. data/lib/tdl/examples/2_hdl_class/tmp/test_package2.sv +4 -4
  81. data/lib/tdl/examples/2_hdl_class/tmp/test_struct_function.sv +2 -2
  82. data/lib/tdl/examples/2_hdl_class/tmp/test_vcs_string.sv +1 -1
  83. data/lib/tdl/examples/2_hdl_class/tmp/text_generate.sv +7 -7
  84. data/lib/tdl/examples/4_generate/test_generate.sv +11 -11
  85. data/lib/tdl/examples/5_logic_combin/test_logic_combin.sv +3 -3
  86. data/lib/tdl/examples/7_module_with_package/body_package.sv +3 -4
  87. data/lib/tdl/examples/7_module_with_package/example_pkg.sv +4 -4
  88. data/lib/tdl/examples/7_module_with_package/head_package.sv +3 -4
  89. data/lib/tdl/examples/8_top_module/tb_test_top.sv +1 -2
  90. data/lib/tdl/examples/9_itegration/clock_manage/itgt_module_clock_manage.rb +13 -0
  91. data/lib/tdl/examples/9_itegration/clock_manage/test_clock_bb.sv +34 -0
  92. data/lib/tdl/examples/9_itegration/tb_test_top.sv +2 -2
  93. data/lib/tdl/examples/9_itegration/tb_test_tttop.sv +1 -1
  94. data/lib/tdl/examples/9_itegration/tb_test_tttop_sim.sv +38 -0
  95. data/lib/tdl/examples/9_itegration/test_top.sv +4 -4
  96. data/lib/tdl/examples/9_itegration/test_tttop.sv +4 -4
  97. data/lib/tdl/examples/9_itegration/test_tttop_sim.sv +9 -0
  98. data/lib/tdl/examples/9_itegration/top.rb +1 -0
  99. data/lib/tdl/exlib/axis_eth_ex.rb +95 -0
  100. data/lib/tdl/exlib/axis_verify.rb +264 -0
  101. data/lib/tdl/exlib/clock_reset_verify.rb +29 -0
  102. data/lib/tdl/exlib/dve_tcl.rb +30 -11
  103. data/lib/tdl/exlib/itegration.rb +15 -3
  104. data/lib/tdl/exlib/itegration_verb.rb +166 -129
  105. data/lib/tdl/exlib/logic_verify.rb +88 -0
  106. data/lib/tdl/exlib/test_point.rb +96 -94
  107. data/lib/tdl/exlib/test_point.rb.bak +293 -0
  108. data/lib/tdl/rebuild_ele/ele_base.rb +1 -1
  109. data/lib/tdl/sdlmodule/sdlmodlule_path_db.rb +34 -0
  110. data/lib/tdl/sdlmodule/sdlmodule.rb +18 -14
  111. data/lib/tdl/sdlmodule/sdlmodule_draw.rb +81 -16
  112. data/lib/tdl/sdlmodule/test_unit_module.rb +278 -33
  113. data/lib/tdl/sdlmodule/test_unit_module.rb.bak +143 -0
  114. data/lib/tdl/sdlmodule/top_module.rb +62 -58
  115. data/lib/tdl/sdlmodule/top_module.rb.bak +547 -0
  116. data/lib/tdl/tdl.rb +18 -3
  117. metadata +35 -134
  118. data/Gemfile.lock +0 -28
  119. data/lib/axi/AXI_stream/axi_stream_split_channel.sv +0 -149
  120. data/lib/axi/AXI_stream/axis_head_cut_verc.sv +0 -242
  121. data/lib/axi/AXI_stream/axis_insert_copy.sv +0 -66
  122. data/lib/axi/AXI_stream/axis_pipe_sync_seam.sv +0 -48
  123. data/lib/axi/AXI_stream/axis_rom_contect_sim.sv +0 -113
  124. data/lib/axi/AXI_stream/axis_split_channel_verb.sv +0 -62
data/lib/tdl/examples/11_test_unit/modules/sub_md1.rb CHANGED
@@ -17,9 +17,14 @@ TdlBuild.sub_md1(__dir__) do
17
17
  end
18
18
 
19
19
  ## CREATE TEST POINT
20
- cnt.create_tp('count test point',__FILE__,__LINE__) - 'tp_cnt'
21
- axis_out.create_tp('test point of axis_out',__FILE__,__LINE__) - 'tp_axis_out'
22
- inter_tf.create_tp('inner test point',__FILE__,__LINE__) - 'tp_inter_tf'
23
- enable.create_tp('enable driver',__FILE__,__LINE__) - 'enable_tp'
20
+ # cnt.create_tp('count test point',__FILE__,__LINE__) - 'tp_cnt'
21
+ # axis_out.create_tp('test point of axis_out',__FILE__,__LINE__) - 'tp_axis_out'
22
+ # inter_tf.create_tp('inner test point',__FILE__,__LINE__) - 'tp_inter_tf'
23
+ # enable.create_tp('enable driver',__FILE__,__LINE__) - 'enable_tp'
24
+
25
+ cnt.tracked_by_dve
26
+ axis_out.tracked_by_dve
27
+ inter_tf.tracked_by_dve(:inner)
28
+ enable.tracked_by_dve
24
29
 
25
30
  end
data/lib/tdl/examples/11_test_unit/modules/sub_md1.sv CHANGED
@@ -5,7 +5,7 @@ _______________________________________
5
5
  descript:
6
6
  author : Cook.Darwin
7
7
  Version: VERA.0.0
8
- created: xxxx.xx.xx
8
+ created: 2021-03-20 12:08:00 +0800
9
9
  madified:
10
10
  ***********************************************/
11
11
  `timescale 1ns/1ps
@@ -26,15 +26,15 @@ data_inf_c #(.DSIZE(8)) inter_tf (.clock(clock),.rst_n(rst_n)) ;
26
26
 
27
27
  //==========================================================================
28
28
  //-------- expression ------------------------------------------------------
29
- assign clock = axis_out.aclk;
30
- assign rst_n = axis_out.aresetn;
29
+ assign clock = axis_out.aclk;
30
+ assign rst_n = axis_out.aresetn;
31
31
 
32
32
  always_ff@(posedge clock,negedge rst_n) begin
33
33
  if(~rst_n)begin
34
- cnt <= '0;
34
+ cnt <= '0;
35
35
  end
36
36
  else begin
37
- cnt <= ( cnt+1'b1);
37
+ cnt <= (cnt+1'b1);
38
38
  end
39
39
  end
40
40
 
data/lib/tdl/examples/11_test_unit/tb_exp_test_unit.sv CHANGED
@@ -5,12 +5,10 @@ _______________________________________
5
5
  descript:
6
6
  author : Cook.Darwin
7
7
  Version: VERA.0.0
8
- created: xxxx.xx.xx
8
+ created: 2021-03-20 12:08:01 +0800
9
9
  madified:
10
10
  ***********************************************/
11
11
  `timescale 1ns/1ps
12
- `timescale 1ns/1ps
13
- `timescale 1ns/1ps
14
12
 
15
13
  module tb_exp_test_unit();
16
14
  //==========================================================================
data/lib/tdl/examples/11_test_unit/tu0.sv CHANGED
@@ -5,7 +5,7 @@ _______________________________________
5
5
  descript:
6
6
  author : Cook.Darwin
7
7
  Version: VERA.0.0
8
- created: xxxx.xx.xx
8
+ created: 2021-03-20 12:08:00 +0800
9
9
  madified:
10
10
  ***********************************************/
11
11
  `timescale 1ns/1ps
@@ -25,14 +25,14 @@ module tu0 (
25
25
  //==========================================================================
26
26
  //-------- expression ------------------------------------------------------
27
27
  initial begin
28
- to_down_pass = 1'b0;
29
- wait(from_up_pass);
30
- $root.tb_exp_test_unit.test_unit_region = "tu0";
31
- $root.tb_exp_test_unit.rtl_top.sub_md1_inst.enable = 1'b1;
32
- #(1us);
33
- $root.tb_exp_test_unit.rtl_top.sub_md1_inst.enable = 1'b0;
34
- #(500us);
35
- to_down_pass = 1'b1;
28
+ to_down_pass = 1'b0;
29
+ wait(from_up_pass);
30
+ $root.tb_exp_test_unit.test_unit_region = "tu0";
31
+ $root.tb_exp_test_unit.rtl_top.sub_md1_inst.enable = 1'b1;
32
+ #(1us);
33
+ $root.tb_exp_test_unit.rtl_top.sub_md1_inst.enable = 1'b0;
34
+ #(500us);
35
+ to_down_pass = 1'b1;
36
36
  end
37
37
 
38
38
  endmodule
data/lib/tdl/examples/11_test_unit/tu1.sv CHANGED
@@ -5,7 +5,7 @@ _______________________________________
5
5
  descript:
6
6
  author : Cook.Darwin
7
7
  Version: VERA.0.0
8
- created: xxxx.xx.xx
8
+ created: 2021-03-20 12:08:00 +0800
9
9
  madified:
10
10
  ***********************************************/
11
11
  `timescale 1ns/1ps
data/lib/tdl/examples/1_define_module/exmple_md.sv CHANGED
@@ -14,13 +14,13 @@ module exmple_md #(
14
14
  parameter DSIZE = 8,
15
15
  parameter real MK = 1.1
16
16
  )(
17
- input insdata,
18
- output outsdata,
19
- input [7:0] inpdata,
20
- output [15:0] outpdata,
21
- output logic[ DSIZE-1:0] ldata,
22
- input clock,
23
- input rst_n
17
+ input insdata,
18
+ output outsdata,
19
+ input [7:0] inpdata,
20
+ output [15:0] outpdata,
21
+ output logic[DSIZE-1:0] ldata,
22
+ input clock,
23
+ input rst_n
24
24
  );
25
25
 
26
26
  //==========================================================================
@@ -32,18 +32,18 @@ logic [6-1:0] tmp_data[9-1:0][7-1:0] ;
32
32
 
33
33
  //==========================================================================
34
34
  //-------- expression ------------------------------------------------------
35
- assign outsdata = insdata;
35
+ assign outsdata = insdata;
36
36
 
37
37
  always_comb begin
38
- outpdata[8:0] = inpdata;
38
+ outpdata[8:0] = inpdata;
39
39
  end
40
40
 
41
- always_ff@(posedge clock,negedge rst_n) begin
41
+ always@(posedge clock,negedge rst_n) begin
42
42
  if(~rst_n)begin
43
- ldata <= '0;
43
+ ldata <= '0;
44
44
  end
45
45
  else begin
46
- ldata[ DSIZE-1:0] <= ( outpdata[7:0]+insdata);
46
+ ldata[DSIZE-1:0] <= (outpdata[7:0]+insdata);
47
47
  end
48
48
  end
49
49
 
data/lib/tdl/examples/2_hdl_class/tmp/always_comb_test.sv CHANGED
@@ -23,85 +23,85 @@ data_inf_c #(.DSIZE(18)) c_inf [2:0][6:0][7:0] (.clock(dclk),.rst_n(drstn)) ;
23
23
  //==========================================================================
24
24
  //-------- expression ------------------------------------------------------
25
25
  always_comb begin
26
- tmp1 = a_inf.data[ 6-1];
27
- a_inf.valid = 1;
26
+ tmp1 = a_inf.data[6-1];
27
+ a_inf.valid = 1;
28
28
  if(0)begin
29
- tmp1 = 90;
30
- tmp1 = a_inf.data[ 6-1];
31
- a_inf.valid = 1;
32
- a_inf.data[6:3] = ( 12+( a_inf.data[6:0]+tmp1));
33
- a_inf.data[6:3] = ( 12+( tmp1+a_inf.data[6:0]));
34
- a_inf.data = ( 12+12);
35
- "90"+"0";
29
+ tmp1 = 90;
30
+ tmp1 = a_inf.data[6-1];
31
+ a_inf.valid = 1;
32
+ a_inf.data[6:3] = 12+(a_inf.data[6:0]+tmp1);
33
+ a_inf.data[6:3] = 12+(tmp1+a_inf.data[6:0]);
34
+ a_inf.data = 12+12;
35
+ "90"+"0";
36
36
  end
37
37
  else if(1)begin
38
- c_inf[0][0][1].valid = 1;
39
- c_inf[0][0][1].data = 0;
40
- c_inf[0][0][1].data[0] = 3;
41
- c_inf[0][0][1].data[0] = 3<= 7;
42
- c_inf.data[0][0][0] = 0;
38
+ c_inf[0][0][1].valid = 1;
39
+ c_inf[0][0][1].data = 0;
40
+ c_inf[0][0][1].data[0] = 3;
41
+ c_inf[0][0][1].data[0] = 3<=7;
42
+ c_inf.data[0][0][0] = 0;
43
43
  end
44
44
  else begin
45
- c_inf[0][0][1].valid = 1;
46
- c_inf[0][0][1].data = 0;
47
- c_inf[0][0][1].data[0] = 3;
48
- c_inf[0][0][1].data[0] = 3<= 7;
49
- c_inf.data[0][0][0] = 0;
45
+ c_inf[0][0][1].valid = 1;
46
+ c_inf[0][0][1].data = 0;
47
+ c_inf[0][0][1].data[0] = 3;
48
+ c_inf[0][0][1].data[0] = 3<=7;
49
+ c_inf.data[0][0][0] = 0;
50
50
  end
51
51
  end
52
52
 
53
53
  always_comb begin
54
- tmp1 = a_inf.data[ 6-1];
55
- a_inf.valid = 1;
54
+ tmp1 = a_inf.data[6-1];
55
+ a_inf.valid = 1;
56
56
  if(tmp1)begin
57
- tmp1 = 90;
58
- tmp1 = a_inf.data[ 6-1];
59
- a_inf.valid = 1;
60
- a_inf.data[6:3] = ( 12+( a_inf.data[6:0]+tmp1));
61
- a_inf.data[6:3] = ( 12+( tmp1+a_inf.data[6:0]));
62
- a_inf.data = ( 12+12);
63
- "90"+"0";
57
+ tmp1 = 90;
58
+ tmp1 = a_inf.data[6-1];
59
+ a_inf.valid = 1;
60
+ a_inf.data[6:3] = 12+(a_inf.data[6:0]+tmp1);
61
+ a_inf.data[6:3] = 12+(tmp1+a_inf.data[6:0]);
62
+ a_inf.data = 12+12;
63
+ "90"+"0";
64
64
  if(9999)begin
65
- a_inf.valid = 1;
66
- a_inf.data[6:3] = ( 12+( a_inf.data[6:0]+tmp1));
67
- a_inf.data[6:3] = ( 12+( tmp1+a_inf.data[6:0]));
68
- a_inf.data = ( 12+12);
65
+ a_inf.valid = 1;
66
+ a_inf.data[6:3] = 12+(a_inf.data[6:0]+tmp1);
67
+ a_inf.data[6:3] = 12+(tmp1+a_inf.data[6:0]);
68
+ a_inf.data = 12+12;
69
69
  end
70
70
  end
71
- else if( tmp1>1)begin
72
- c_inf[0][0][1].valid = 1;
73
- c_inf[0][0][1].data = 0;
74
- c_inf[0][0][1].data[0] = 3;
75
- c_inf[0][0][1].data[0] = 3<= 7;
76
- c_inf.data[0][0][0] = 0;
71
+ else if(tmp1>1)begin
72
+ c_inf[0][0][1].valid = 1;
73
+ c_inf[0][0][1].data = 0;
74
+ c_inf[0][0][1].data[0] = 3;
75
+ c_inf[0][0][1].data[0] = 3<=7;
76
+ c_inf.data[0][0][0] = 0;
77
77
  end
78
78
  else if(~tmp1)begin
79
- c_inf[0][0][1].valid = 1;
80
- c_inf[0][0][1].data = 0;
81
- c_inf[0][0][1].data[0] = 3;
82
- c_inf[0][0][1].data[0] = 3<= 7;
83
- c_inf.data[0][0][0] = 0;
79
+ c_inf[0][0][1].valid = 1;
80
+ c_inf[0][0][1].data = 0;
81
+ c_inf[0][0][1].data[0] = 3;
82
+ c_inf[0][0][1].data[0] = 3<=7;
83
+ c_inf.data[0][0][0] = 0;
84
84
  end
85
- else if( tmp1>c_inf[0][0][1].data)begin
86
- c_inf[0][0][1].valid = 1;
87
- c_inf[0][0][1].data = 0;
88
- c_inf[0][0][1].data[0] = 3;
89
- c_inf[0][0][1].data[0] = 3<= 7;
90
- c_inf.data[0][0][0] = 0;
85
+ else if(tmp1>c_inf[0][0][1].data)begin
86
+ c_inf[0][0][1].valid = 1;
87
+ c_inf[0][0][1].data = 0;
88
+ c_inf[0][0][1].data[0] = 3;
89
+ c_inf[0][0][1].data[0] = 3<=7;
90
+ c_inf.data[0][0][0] = 0;
91
91
  end
92
- else if( c_inf[0][0][1].data+tmp0[0][0][0])begin
93
- c_inf[0][0][1].valid = 1;
94
- c_inf[0][0][1].data = 0;
95
- c_inf[0][0][1].data[0] = 3;
96
- c_inf[0][0][1].data[0] = 3<= 7;
97
- c_inf.data[0][0][0] = 0;
92
+ else if(c_inf[0][0][1].data+tmp0[0][0][0])begin
93
+ c_inf[0][0][1].valid = 1;
94
+ c_inf[0][0][1].data = 0;
95
+ c_inf[0][0][1].data[0] = 3;
96
+ c_inf[0][0][1].data[0] = 3<=7;
97
+ c_inf.data[0][0][0] = 0;
98
98
  end
99
99
  else begin
100
- c_inf[0][0][1].valid = 1;
101
- c_inf[0][0][1].data = 0;
102
- c_inf[0][0][1].data[0] = 3;
103
- c_inf[0][0][1].data[0] = 3<= 7;
104
- c_inf.data[0][0][0] = 0;
100
+ c_inf[0][0][1].valid = 1;
101
+ c_inf[0][0][1].data = 0;
102
+ c_inf[0][0][1].data[0] = 3;
103
+ c_inf[0][0][1].data[0] = 3<=7;
104
+ c_inf.data[0][0][0] = 0;
105
105
  end
106
106
  end
107
107
 
data/lib/tdl/examples/2_hdl_class/tmp/always_ff_test.sv CHANGED
@@ -28,8 +28,8 @@ data_inf_c #(.DSIZE(8)) c_inf [2:0][6:0][7:0] (.clock(dclk),.rst_n(drstn)) ;
28
28
 
29
29
  //==========================================================================
30
30
  //-------- expression ------------------------------------------------------
31
- always_ff@(posedge clock,negedge rst_n) begin
32
- ( 32*2- 5)-6;
31
+ always@(posedge clock,negedge rst_n) begin
32
+ (32*2-5)-6;
33
33
  end
34
34
 
35
35
  endmodule
data/lib/tdl/examples/2_hdl_class/tmp/case_test.sv CHANGED
@@ -28,38 +28,38 @@ data_inf_c #(.DSIZE(8)) c_inf [2:0][6:0][7:0] (.clock(dclk),.rst_n(drstn)) ;
28
28
 
29
29
  //==========================================================================
30
30
  //-------- expression ------------------------------------------------------
31
- always_ff@(posedge clock) begin
31
+ always@(posedge clock) begin
32
32
  case(tmp0)
33
33
  a_inf.data:begin
34
34
  if(90)begin
35
- tmp1 <= 0;
35
+ tmp1 <= 0;
36
36
  end
37
37
  else begin
38
- tmp1 <= 1;
38
+ tmp1 <= 1;
39
39
  end
40
40
  end
41
41
  1,2:begin
42
42
  if(90)begin
43
- tmp1 <= 0;
43
+ tmp1 <= 0;
44
44
  end
45
45
  else begin
46
- tmp1 <= 1;
46
+ tmp1 <= 1;
47
47
  end
48
48
  end
49
49
  c_inf[0][1][2].data,2:begin
50
50
  if(c_inf[0][1][2].valid)begin
51
- tmp1 <= 0;
51
+ tmp1 <= 0;
52
52
  end
53
53
  else begin
54
- tmp1 <= 1;
54
+ tmp1 <= 1;
55
55
  end
56
56
  end
57
57
  default:begin
58
58
  if(909)begin
59
- tmp1 <= 0;
59
+ tmp1 <= 0;
60
60
  end
61
61
  else begin
62
- tmp1 <= 1;
62
+ tmp1 <= 1;
63
63
  end
64
64
  end
65
65
  endcase
@@ -69,34 +69,34 @@ always_comb begin
69
69
  case(tmp0)
70
70
  a_inf.data:begin
71
71
  if(90)begin
72
- tmp1 = 0;
72
+ tmp1 = 0;
73
73
  end
74
74
  else begin
75
- tmp1 = 1;
75
+ tmp1 = 1;
76
76
  end
77
77
  end
78
78
  1,2:begin
79
79
  if(90)begin
80
- tmp1 = 0;
80
+ tmp1 = 0;
81
81
  end
82
82
  else begin
83
- tmp1 = 1;
83
+ tmp1 = 1;
84
84
  end
85
85
  end
86
86
  c_inf[0][1][2].data,2:begin
87
87
  if(c_inf[0][1][2].valid)begin
88
- tmp1 = 0;
88
+ tmp1 = 0;
89
89
  end
90
90
  else begin
91
- tmp1 = 1;
91
+ tmp1 = 1;
92
92
  end
93
93
  end
94
94
  default:begin
95
95
  if(909)begin
96
- tmp1 = 0;
96
+ tmp1 = 0;
97
97
  end
98
98
  else begin
99
- tmp1 = 1;
99
+ tmp1 = 1;
100
100
  end
101
101
  end
102
102
  endcase
data/lib/tdl/examples/2_hdl_class/tmp/head_pkg_module.sv CHANGED
@@ -21,22 +21,22 @@ module head_pkg_module import test_package::*;(
21
21
  //-------- define ----------------------------------------------------------
22
22
  z_ing y0;
23
23
  z_ing curr_y0;
24
- logic [ $clog2( NUM*8)-1:0] clog2_data ;
24
+ logic [$clog2(NUM*8)-1:0] clog2_data ;
25
25
 
26
26
  //==========================================================================
27
27
  //-------- instance --------------------------------------------------------
28
28
 
29
29
  //==========================================================================
30
30
  //-------- expression ------------------------------------------------------
31
- assign out = NUM;
32
- assign out = data;
33
- assign struct_z_l[8].op[0] = 0;
31
+ assign out = NUM;
32
+ assign out = data;
33
+ assign struct_z_l[8].op[0] = 0;
34
34
 
35
- assign y0.op = 1'b0;
36
- assign y0.op[0] = 1'd0;
37
- assign y0.op[1] = struct_z.op[1];
38
- assign y0.op[y0.op[3:1]] = struct_z.op;
35
+ assign y0.op = 1'b0;
36
+ assign y0.op[0] = 1'd0;
37
+ assign y0.op[1] = struct_z.op[1];
38
+ assign y0.op[y0.op[3:1]] = struct_z.op;
39
39
 
40
- assign curr_y0 = struct_z;
40
+ assign curr_y0 = struct_z;
41
41
 
42
42
  endmodule
data/lib/tdl/examples/2_hdl_class/tmp/simple_assign_test.sv CHANGED
@@ -22,6 +22,6 @@ data_inf_c #(.DSIZE(8)) c_inf [2:0][6:0][7:0] (.clock(dclk),.rst_n(drstn)) ;
22
22
 
23
23
  //==========================================================================
24
24
  //-------- expression ------------------------------------------------------
25
- assign tmp1 = ( tmp0[0]&"FALSE" && ( c_inf.data==3 || a_inf.valid|1'b0));
25
+ assign tmp1 = tmp0[0]&"FALSE" &&(c_inf.data==3 ||a_inf.valid|1'b0);
26
26
 
27
27
  endmodule
data/lib/tdl/examples/2_hdl_class/tmp/state_case_test.sv CHANGED
@@ -37,39 +37,39 @@ SE_STATE_ctrl_state CSTATE_ctrl_state,NSTATE_ctrl_state;
37
37
  always_comb begin
38
38
  case(CSTATE_ctrl_state)
39
39
  IDLE:begin
40
- NSTATE_ctrl_state = EXEC;
40
+ NSTATE_ctrl_state = EXEC;
41
41
  end
42
42
  EXEC:begin
43
43
  if(90)begin
44
- NSTATE_ctrl_state = DONE;
44
+ NSTATE_ctrl_state = DONE;
45
45
  end
46
46
  else begin
47
- NSTATE_ctrl_state = EXEC;
47
+ NSTATE_ctrl_state = EXEC;
48
48
  end
49
49
  end
50
50
  DONE:begin
51
- NSTATE_ctrl_state = IDLE;
51
+ NSTATE_ctrl_state = IDLE;
52
52
  end
53
53
  default:begin
54
- NSTATE_ctrl_state = IDLE;
54
+ NSTATE_ctrl_state = IDLE;
55
55
  end
56
56
  endcase
57
57
  end
58
58
 
59
- always_ff@(posedge clock,negedge rst_n) begin
59
+ always@(posedge clock,negedge rst_n) begin
60
60
  if(~rst_n)begin
61
- a_inf.data <= '0;
61
+ a_inf.data <= '0;
62
62
  end
63
63
  else begin
64
64
  case(NSTATE_ctrl_state)
65
65
  IDLE:begin
66
- a_inf.data <= 8'd9;
66
+ a_inf.data <= 8'd9;
67
67
  end
68
68
  EXEC:begin
69
- a_inf.data <= 8'h12;
69
+ a_inf.data <= 8'h12;
70
70
  end
71
71
  default:begin
72
- a_inf.data <= ~('0);
72
+ a_inf.data <= ~('0);
73
73
  end
74
74
  endcase
75
75
  end