axi_tdl 0.0.10 → 0.1.0
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- checksums.yaml +4 -4
- data/.github/workflows/gem-push.yml +44 -0
- data/.github/workflows/ruby.yml +35 -0
- data/.gitignore +3 -1
- data/.travis.yml +9 -0
- data/Gemfile +4 -0
- data/README.EN.md +7 -2
- data/README.md +6 -2
- data/Rakefile +2 -6
- data/axi_tdl.gemspec +3 -4
- data/lib/axi/AXI4/axi4_direct_B1.sv +23 -23
- data/lib/axi/AXI4/axi4_dpram_cache.sv +33 -33
- data/lib/axi/AXI4/axis_to_axi4_wr.rb +1 -0
- data/lib/axi/AXI4/axis_to_axi4_wr.sv +20 -20
- data/lib/axi/AXI4/packet_partition/axi4_partition_rd_verb.sv +32 -32
- data/lib/axi/AXI4/packet_partition/data_inf_partition.rb +2 -0
- data/lib/axi/AXI4/packet_partition/data_inf_partition.sv +71 -71
- data/lib/axi/AXI4/wide_axis_to_axi4_wr.rb +2 -1
- data/lib/axi/AXI4/wide_axis_to_axi4_wr.sv +23 -23
- data/lib/axi/AXI_stream/axi_stream_split_channel.rb +7 -1
- data/lib/axi/AXI_stream/axis_head_cut_verb.sv +6 -2
- data/lib/axi/AXI_stream/axis_insert_copy.rb +18 -4
- data/lib/axi/AXI_stream/axis_sim_master_model.rb +28 -0
- data/lib/axi/AXI_stream/axis_sim_slaver_model.rb +26 -0
- data/lib/axi/AXI_stream/axis_sim_verify_by_coe.sv +101 -0
- data/lib/axi/AXI_stream/axis_split_channel_verb.rb +2 -0
- data/lib/axi/common/common_ram_sim_wrapper.sv +9 -9
- data/lib/axi/common/common_ram_wrapper.sv +12 -12
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.sv +26 -26
- data/lib/axi/data_interface/data_inf_c/data_c_sim_master_model.sv +69 -0
- data/lib/axi/data_interface/data_inf_c/data_c_sim_slaver_model.sv +58 -0
- data/lib/axi/data_interface/data_inf_c/logic_sim_model.sv +64 -0
- data/lib/axi/techbench/tb_axi_stream_split_channel.rb +69 -0
- data/lib/axi/techbench/tb_axi_stream_split_channel.sv +149 -0
- data/lib/axi/techbench/tb_axis_split_channel_verb.rb +69 -0
- data/lib/axi/techbench/tb_axis_split_channel_verb.sv +125 -0
- data/lib/axi_tdl.rb +1 -0
- data/lib/axi_tdl/version.rb +1 -1
- data/lib/tdl/auto_script/autogensdl.rb +16 -5
- data/lib/tdl/axi4/axi4_interconnect_verb.rb +4 -2
- data/lib/tdl/basefunc.rb +1 -0
- data/lib/tdl/class_hdl/hdl_always_comb.rb +4 -3
- data/lib/tdl/class_hdl/hdl_always_ff.rb +49 -8
- data/lib/tdl/class_hdl/hdl_assign.rb +5 -3
- data/lib/tdl/class_hdl/hdl_block_ifelse.rb +11 -9
- data/lib/tdl/class_hdl/hdl_foreach.rb +2 -2
- data/lib/tdl/class_hdl/hdl_function.rb +4 -2
- data/lib/tdl/class_hdl/hdl_generate.rb +5 -4
- data/lib/tdl/class_hdl/hdl_initial.rb +11 -10
- data/lib/tdl/class_hdl/hdl_module_def.rb +18 -1
- data/lib/tdl/class_hdl/hdl_redefine_opertor.rb +35 -14
- data/lib/tdl/class_hdl/hdl_struct.rb +1 -1
- data/lib/tdl/class_hdl/hdl_verify.rb +1 -1
- data/lib/tdl/elements/originclass.rb +6 -1
- data/lib/tdl/elements/parameter.rb +1 -1
- data/lib/tdl/examples/10_random/exp_random.sv +3 -3
- data/lib/tdl/examples/11_test_unit/dve.tcl +155 -2
- data/lib/tdl/examples/11_test_unit/exp_test_unit.rb +9 -8
- data/lib/tdl/examples/11_test_unit/exp_test_unit.sv +1 -1
- data/lib/tdl/examples/11_test_unit/modules/sub_md0.rb +6 -3
- data/lib/tdl/examples/11_test_unit/modules/sub_md0.sv +5 -5
- data/lib/tdl/examples/11_test_unit/modules/sub_md1.rb +9 -4
- data/lib/tdl/examples/11_test_unit/modules/sub_md1.sv +5 -5
- data/lib/tdl/examples/11_test_unit/tb_exp_test_unit.sv +1 -3
- data/lib/tdl/examples/11_test_unit/tu0.sv +9 -9
- data/lib/tdl/examples/11_test_unit/tu1.sv +1 -1
- data/lib/tdl/examples/1_define_module/exmple_md.sv +12 -12
- data/lib/tdl/examples/2_hdl_class/tmp/always_comb_test.sv +60 -60
- data/lib/tdl/examples/2_hdl_class/tmp/always_ff_test.sv +2 -2
- data/lib/tdl/examples/2_hdl_class/tmp/case_test.sv +17 -17
- data/lib/tdl/examples/2_hdl_class/tmp/head_pkg_module.sv +9 -9
- data/lib/tdl/examples/2_hdl_class/tmp/simple_assign_test.sv +1 -1
- data/lib/tdl/examples/2_hdl_class/tmp/state_case_test.sv +10 -10
- data/lib/tdl/examples/2_hdl_class/tmp/test_foreach.sv +3 -3
- data/lib/tdl/examples/2_hdl_class/tmp/test_function.sv +7 -7
- data/lib/tdl/examples/2_hdl_class/tmp/test_initial_assert.sv +3 -3
- data/lib/tdl/examples/2_hdl_class/tmp/test_module.sv +2 -2
- data/lib/tdl/examples/2_hdl_class/tmp/test_module_var.sv +1 -1
- data/lib/tdl/examples/2_hdl_class/tmp/test_package.sv +4 -5
- data/lib/tdl/examples/2_hdl_class/tmp/test_package2.sv +4 -4
- data/lib/tdl/examples/2_hdl_class/tmp/test_struct_function.sv +2 -2
- data/lib/tdl/examples/2_hdl_class/tmp/test_vcs_string.sv +1 -1
- data/lib/tdl/examples/2_hdl_class/tmp/text_generate.sv +7 -7
- data/lib/tdl/examples/4_generate/test_generate.sv +11 -11
- data/lib/tdl/examples/5_logic_combin/test_logic_combin.sv +3 -3
- data/lib/tdl/examples/7_module_with_package/body_package.sv +3 -4
- data/lib/tdl/examples/7_module_with_package/example_pkg.sv +4 -4
- data/lib/tdl/examples/7_module_with_package/head_package.sv +3 -4
- data/lib/tdl/examples/8_top_module/tb_test_top.sv +1 -2
- data/lib/tdl/examples/9_itegration/clock_manage/itgt_module_clock_manage.rb +13 -0
- data/lib/tdl/examples/9_itegration/clock_manage/test_clock_bb.sv +34 -0
- data/lib/tdl/examples/9_itegration/tb_test_top.sv +2 -2
- data/lib/tdl/examples/9_itegration/tb_test_tttop.sv +1 -1
- data/lib/tdl/examples/9_itegration/tb_test_tttop_sim.sv +38 -0
- data/lib/tdl/examples/9_itegration/test_top.sv +4 -4
- data/lib/tdl/examples/9_itegration/test_tttop.sv +4 -4
- data/lib/tdl/examples/9_itegration/test_tttop_sim.sv +9 -0
- data/lib/tdl/examples/9_itegration/top.rb +1 -0
- data/lib/tdl/exlib/axis_eth_ex.rb +95 -0
- data/lib/tdl/exlib/axis_verify.rb +264 -0
- data/lib/tdl/exlib/clock_reset_verify.rb +29 -0
- data/lib/tdl/exlib/dve_tcl.rb +30 -11
- data/lib/tdl/exlib/itegration.rb +15 -3
- data/lib/tdl/exlib/itegration_verb.rb +166 -129
- data/lib/tdl/exlib/logic_verify.rb +88 -0
- data/lib/tdl/exlib/test_point.rb +96 -94
- data/lib/tdl/exlib/test_point.rb.bak +293 -0
- data/lib/tdl/rebuild_ele/ele_base.rb +1 -1
- data/lib/tdl/sdlmodule/sdlmodlule_path_db.rb +34 -0
- data/lib/tdl/sdlmodule/sdlmodule.rb +18 -14
- data/lib/tdl/sdlmodule/sdlmodule_draw.rb +81 -16
- data/lib/tdl/sdlmodule/test_unit_module.rb +278 -33
- data/lib/tdl/sdlmodule/test_unit_module.rb.bak +143 -0
- data/lib/tdl/sdlmodule/top_module.rb +62 -58
- data/lib/tdl/sdlmodule/top_module.rb.bak +547 -0
- data/lib/tdl/tdl.rb +18 -3
- metadata +35 -134
- data/Gemfile.lock +0 -28
- data/lib/axi/AXI_stream/axi_stream_split_channel.sv +0 -149
- data/lib/axi/AXI_stream/axis_head_cut_verc.sv +0 -242
- data/lib/axi/AXI_stream/axis_insert_copy.sv +0 -66
- data/lib/axi/AXI_stream/axis_pipe_sync_seam.sv +0 -48
- data/lib/axi/AXI_stream/axis_rom_contect_sim.sv +0 -113
- data/lib/axi/AXI_stream/axis_split_channel_verb.sv +0 -62
checksums.yaml
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data.tar.gz: 183f5a3421d04f6c418fea0c1fa5ec14a91a50a1ffd3902e3decc4cac8cc77b774f8031e6686f4948c6d30b9925618a9062900f30d5312e3464ed36c5763b842
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name: Ruby Gem
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runs-on: ubuntu-latest
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# RELEASE_COMMAND: rake release
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data/.gitignore
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data/Gemfile
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data/README.EN.md
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# AxiTdl
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[](https://badge.fury.io/rb/axi_tdl)
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[](https://travis-ci.com/CookDarwin/axi_tdl)
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## Axi
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  It is a wonderful library of axi4, but it is not full axi4, It is designed by systemverilog. I compact axi4 and add something to it.
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  axi hdl path
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require 'axi_tdl'
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AxiTdl::AXI_PATH
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```
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## Other
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  It contain a simple interface that only define three signals, `valid`, `ready`, and `data`. I think it is useful for design.
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## What is tdl?
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data/README.md
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#
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# AxiTdl
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[](https://badge.fury.io/rb/axi_tdl)
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[](https://travis-ci.com/CookDarwin/axi_tdl)
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## Axi
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  axi是一个 axi4 拓展库，它使用的是删减版的AXI4协议，使用systemverilog开发，除此外我还拓展了AXI4的一些信号。
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  axi hdl 所在路径可以如下Ruby 脚本获取
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require 'axi_tdl'
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AxiTdl::AXI_PATH
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```
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## 其他
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  此库还包含一个简单的接口定义, 接口信号只有 `valid`, `ready`, 和 `data`. 对于一些轻量设计很有帮助。
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## tdl 是什么？
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data/Rakefile
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require "bundler/gem_tasks"
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end
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task :old do
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exec 'ruby -I"lib:test" -I"/home/wmy367/.rvm/gems/ruby-2.6.3/gems/rake-10.5.0/lib" "/home/wmy367/.rvm/gems/ruby-2.6.3/gems/rake-10.5.0/lib/rake/rake_test_loader.rb" "test/*_test.rb" '
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end
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data/axi_tdl.gemspec
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require "axi_tdl/version"
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spec.executables = spec.files.grep(%r{^exe/}) { |f| File.basename(f) }
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# spec.add_development_dependency "bundler", "~> 1.16"
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spec.add_development_dependency "rake", "~> 10.0"
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# spec.add_development_dependency "rspec"
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spec.add_development_dependency "pry"
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spec.add_development_dependency "minitest"
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spec.add_development_dependency "pry","~> 0.11"
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spec.add_development_dependency "minitest","~> 5.10"
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end
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(* axi4 = "true" *)
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module axi4_direct_B1 (
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(* up_stream = "true" *)
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axi_inf.slaver
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axi_inf.slaver slaver_inf,
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(* down_stream = "true" *)
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axi_inf.master
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axi_inf.master master_inf
|
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18
18
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);
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19
19
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20
20
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21
21
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generate
|
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22
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-
if(
|
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22
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+
if(slaver_inf.MODE == "ONLY_READ" && master_inf.MODE == "ONLY_READ")
|
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23
23
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axi4_direct_A1 #(
|
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24
24
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.MODE ("ONLY_READ_to_ONLY_READ") //ONLY_READ to BOTH,ONLY_WRITE to BOTH,BOTH to BOTH,BOTH to ONLY_READ,BOTH to ONLY_WRITE
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25
25
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)axi4_direct_inst_ONLY_READ_to_ONLY_READ(
|
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26
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-
/* axi_inf.slaver */ .slaver (
|
|
27
|
-
/* axi_inf.master */ .master (
|
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26
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+
/* axi_inf.slaver */ .slaver (slaver_inf ),
|
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27
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+
/* axi_inf.master */ .master (master_inf )
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28
28
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);
|
|
29
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-
else if(
|
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29
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+
else if(slaver_inf.MODE == "ONLY_READ" && master_inf.MODE == "BOTH")
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30
30
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axi4_direct_A1 #(
|
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31
31
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.MODE ("ONLY_READ_to_BOTH") //ONLY_READ to BOTH,ONLY_WRITE to BOTH,BOTH to BOTH,BOTH to ONLY_READ,BOTH to ONLY_WRITE
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32
32
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)axi4_direct_inst_ONLY_READ_to_BOTH(
|
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33
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-
/* axi_inf.slaver */ .slaver (
|
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34
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-
/* axi_inf.master */ .master (
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33
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+
/* axi_inf.slaver */ .slaver (slaver_inf ),
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34
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+
/* axi_inf.master */ .master (master_inf )
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35
35
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);
|
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36
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-
else if(
|
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36
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+
else if(slaver_inf.MODE == "ONLY_WRITE" && master_inf.MODE == "BOTH")
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37
37
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axi4_direct_A1 #(
|
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38
38
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.MODE ("ONLY_WRITE_to_BOTH") //ONLY_READ to BOTH,ONLY_WRITE to BOTH,BOTH to BOTH,BOTH to ONLY_READ,BOTH to ONLY_WRITE
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39
39
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)axi4_direct_inst_ONLY_WRITE_to_BOTH(
|
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40
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-
/* axi_inf.slaver */ .slaver (
|
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41
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-
/* axi_inf.master */ .master (
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40
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+
/* axi_inf.slaver */ .slaver (slaver_inf ),
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41
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+
/* axi_inf.master */ .master (master_inf )
|
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42
42
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);
|
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43
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-
else if(
|
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43
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+
else if(slaver_inf.MODE == "ONLY_WRITE" && master_inf.MODE == "ONLY_WRITE")
|
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44
44
|
axi4_direct_A1 #(
|
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45
45
|
.MODE ("ONLY_WRITE_to_ONLY_WRITE") //ONLY_READ to BOTH,ONLY_WRITE to BOTH,BOTH to BOTH,BOTH to ONLY_READ,BOTH to ONLY_WRITE
|
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46
46
|
)axi4_direct_inst_ONLY_WRITE_to_ONLY_WRITE(
|
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47
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-
/* axi_inf.slaver */ .slaver (
|
|
48
|
-
/* axi_inf.master */ .master (
|
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47
|
+
/* axi_inf.slaver */ .slaver (slaver_inf ),
|
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48
|
+
/* axi_inf.master */ .master (master_inf )
|
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49
49
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);
|
|
50
|
-
else if(
|
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50
|
+
else if(slaver_inf.MODE == "BOTH" && master_inf.MODE == "ONLY_WRITE")
|
|
51
51
|
axi4_direct_A1 #(
|
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52
52
|
.MODE ("BOTH_to_ONLY_WRITE") //ONLY_READ to BOTH,ONLY_WRITE to BOTH,BOTH to BOTH,BOTH to ONLY_READ,BOTH to ONLY_WRITE
|
|
53
53
|
)axi4_direct_inst_BOTH_to_ONLY_WRITE(
|
|
54
|
-
/* axi_inf.slaver */ .slaver (
|
|
55
|
-
/* axi_inf.master */ .master (
|
|
54
|
+
/* axi_inf.slaver */ .slaver (slaver_inf ),
|
|
55
|
+
/* axi_inf.master */ .master (master_inf )
|
|
56
56
|
);
|
|
57
|
-
else if(
|
|
57
|
+
else if(slaver_inf.MODE == "BOTH" && master_inf.MODE == "ONLY_READ")
|
|
58
58
|
axi4_direct_A1 #(
|
|
59
59
|
.MODE ("BOTH_to_ONLY_READ") //ONLY_READ to BOTH,ONLY_WRITE to BOTH,BOTH to BOTH,BOTH to ONLY_READ,BOTH to ONLY_WRITE
|
|
60
60
|
)axi4_direct_inst_BOTH_to_ONLY_READ(
|
|
61
|
-
/* axi_inf.slaver */ .slaver (
|
|
62
|
-
/* axi_inf.master */ .master (
|
|
61
|
+
/* axi_inf.slaver */ .slaver (slaver_inf ),
|
|
62
|
+
/* axi_inf.master */ .master (master_inf )
|
|
63
63
|
);
|
|
64
|
-
else if(
|
|
64
|
+
else if(slaver_inf.MODE == "BOTH" && master_inf.MODE == "BOTH")
|
|
65
65
|
axi4_direct_A1 #(
|
|
66
66
|
.MODE ("BOTH_to_BOTH") //ONLY_READ to BOTH,ONLY_WRITE to BOTH,BOTH to BOTH,BOTH to ONLY_READ,BOTH to ONLY_WRITE
|
|
67
67
|
)axi4_direct_inst_BOTH_to_BOTH(
|
|
68
|
-
/* axi_inf.slaver */ .slaver (
|
|
69
|
-
/* axi_inf.master */ .master (
|
|
68
|
+
/* axi_inf.slaver */ .slaver (slaver_inf ),
|
|
69
|
+
/* axi_inf.master */ .master (master_inf )
|
|
70
70
|
);
|
|
71
71
|
|
|
72
72
|
endgenerate
|
|
@@ -20,7 +20,7 @@ module axi4_dpram_cache #(
|
|
|
20
20
|
//==========================================================================
|
|
21
21
|
//-------- define ----------------------------------------------------------
|
|
22
22
|
|
|
23
|
-
cm_ram_inf #(.DSIZE(a_inf.DSIZE),.RSIZE(a_inf.ASIZE),.MSIZE(
|
|
23
|
+
cm_ram_inf #(.DSIZE(a_inf.DSIZE),.RSIZE(a_inf.ASIZE),.MSIZE(a_inf.DSIZE/8)) xram_inf();
|
|
24
24
|
axi_stream_inf #(.DSIZE(a_inf.ASIZE+a_inf.DSIZE+1),.USIZE(1)) a_axis_inf (.aclk(a_inf.axi_aclk),.aresetn(a_inf.axi_aresetn),.aclken(1'b1)) ;
|
|
25
25
|
axi_stream_inf #(.DSIZE(a_inf.DSIZE),.USIZE(1)) a_axis_rd_inf (.aclk(a_inf.axi_aclk),.aresetn(a_inf.axi_aresetn),.aclken(1'b1)) ;
|
|
26
26
|
data_inf_c #(.DSIZE(a_inf.ASIZE+1)) a_datac_rd_inf (.clock(a_inf.axi_aclk),.rst_n(a_inf.axi_aresetn)) ;
|
|
@@ -69,44 +69,44 @@ common_ram_wrapper #(
|
|
|
69
69
|
//==========================================================================
|
|
70
70
|
//-------- expression ------------------------------------------------------
|
|
71
71
|
initial begin
|
|
72
|
-
assert(
|
|
73
|
-
|
|
74
|
-
|
|
72
|
+
assert(a_inf.ASIZE==b_inf.ASIZE)else begin
|
|
73
|
+
$error("a_inf.ASIZE != b_inf.ASIZE");
|
|
74
|
+
$stop;
|
|
75
75
|
end
|
|
76
|
-
assert(
|
|
77
|
-
|
|
78
|
-
|
|
76
|
+
assert(a_inf.DSIZE==b_inf.DSIZE)else begin
|
|
77
|
+
$error("a_inf.ASIZE != b_inf.ASIZE");
|
|
78
|
+
$stop;
|
|
79
79
|
end
|
|
80
80
|
end
|
|
81
81
|
|
|
82
|
-
assign
|
|
83
|
-
assign
|
|
84
|
-
assign
|
|
82
|
+
assign a_axis_inf.axis_tready = a_axis_inf.axis_tdata[a_inf.ASIZE+a_inf.DSIZE+1-1] || (a_datac_rd_inf.ready && !a_axis_inf.axis_tdata[a_inf.ASIZE+a_inf.DSIZE+1-1]);
|
|
83
|
+
assign a_datac_rd_inf.data = {a_axis_inf.axis_tlast,a_axis_inf.axis_tdata[(a_inf.ASIZE+a_inf.DSIZE+1-1)-1:(a_inf.ASIZE+a_inf.DSIZE+1-a_inf.ASIZE)-1]};
|
|
84
|
+
assign a_datac_rd_inf.valid = a_axis_inf.axis_tvalid && !a_axis_inf.axis_tdata[a_inf.ASIZE+a_inf.DSIZE+1-1];
|
|
85
85
|
|
|
86
|
-
assign
|
|
87
|
-
assign
|
|
88
|
-
assign
|
|
89
|
-
assign
|
|
90
|
-
assign
|
|
91
|
-
assign
|
|
92
|
-
assign
|
|
93
|
-
assign
|
|
94
|
-
assign
|
|
95
|
-
assign
|
|
86
|
+
assign a_axis_rd_inf.axis_tvalid = a_datac_rd_rel_inf.valid;
|
|
87
|
+
assign a_axis_rd_inf.axis_tdata = a_datac_rd_rel_inf.data[a_inf.DSIZE-1:0];
|
|
88
|
+
assign a_axis_rd_inf.axis_tlast = a_datac_rd_rel_inf.data[a_inf.ASIZE+a_inf.DSIZE+1-1];
|
|
89
|
+
assign a_datac_rd_rel_inf.ready = a_axis_rd_inf.axis_tready;
|
|
90
|
+
assign xram_inf.addra = a_axis_inf.axis_tdata[(a_inf.ASIZE+a_inf.DSIZE+1-1)-1:(a_inf.ASIZE+a_inf.DSIZE+1-a_inf.ASIZE)-1];
|
|
91
|
+
assign xram_inf.dia = a_axis_inf.axis_tdata[a_inf.DSIZE-1:0];
|
|
92
|
+
assign xram_inf.wea = {xram_inf.MSIZE{a_axis_inf.axis_tdata[a_inf.ASIZE+a_inf.DSIZE+1-1]}};
|
|
93
|
+
assign xram_inf.ena = 1'b1;
|
|
94
|
+
assign xram_inf.clka = a_inf.axi_aclk;
|
|
95
|
+
assign xram_inf.rsta = ~a_inf.axi_aresetn;
|
|
96
96
|
|
|
97
|
-
assign
|
|
98
|
-
assign
|
|
99
|
-
assign
|
|
97
|
+
assign b_axis_inf.axis_tready = b_axis_inf.axis_tdata[b_inf.ASIZE+b_inf.DSIZE+1-1] || (b_datac_rd_inf.ready && !b_axis_inf.axis_tdata[b_inf.ASIZE+b_inf.DSIZE+1-1]);
|
|
98
|
+
assign b_datac_rd_inf.data = {b_axis_inf.axis_tlast,b_axis_inf.axis_tdata[(b_inf.ASIZE+b_inf.DSIZE+1-1)-1:(b_inf.ASIZE+b_inf.DSIZE+1-b_inf.ASIZE)-1]};
|
|
99
|
+
assign b_datac_rd_inf.valid = b_axis_inf.axis_tvalid && !b_axis_inf.axis_tdata[b_inf.ASIZE+b_inf.DSIZE+1-1];
|
|
100
100
|
|
|
101
|
-
assign
|
|
102
|
-
assign
|
|
103
|
-
assign
|
|
104
|
-
assign
|
|
105
|
-
assign
|
|
106
|
-
assign
|
|
107
|
-
assign
|
|
108
|
-
assign
|
|
109
|
-
assign
|
|
110
|
-
assign
|
|
101
|
+
assign b_axis_rd_inf.axis_tvalid = b_datac_rd_rel_inf.valid;
|
|
102
|
+
assign b_axis_rd_inf.axis_tdata = b_datac_rd_rel_inf.data[b_inf.DSIZE-1:0];
|
|
103
|
+
assign b_axis_rd_inf.axis_tlast = b_datac_rd_rel_inf.data[b_inf.ASIZE+b_inf.DSIZE+1-1];
|
|
104
|
+
assign b_datac_rd_rel_inf.ready = b_axis_rd_inf.axis_tready;
|
|
105
|
+
assign xram_inf.addrb = b_axis_inf.axis_tdata[(b_inf.ASIZE+b_inf.DSIZE+1-1)-1:(b_inf.ASIZE+b_inf.DSIZE+1-b_inf.ASIZE)-1];
|
|
106
|
+
assign xram_inf.dib = b_axis_inf.axis_tdata[b_inf.DSIZE-1:0];
|
|
107
|
+
assign xram_inf.web = {xram_inf.MSIZE{b_axis_inf.axis_tdata[b_inf.ASIZE+b_inf.DSIZE+1-1]}};
|
|
108
|
+
assign xram_inf.enb = 1'b1;
|
|
109
|
+
assign xram_inf.clkb = b_inf.axi_aclk;
|
|
110
|
+
assign xram_inf.rstb = ~b_inf.axi_aresetn;
|
|
111
111
|
|
|
112
112
|
endmodule
|
|
@@ -6,6 +6,7 @@ require_hdl 'axis_length_split_with_addr.sv'
|
|
|
6
6
|
require_hdl 'axi_stream_long_fifo.sv'
|
|
7
7
|
require_hdl 'axi4_wr_auxiliary_gen_without_resp.sv'
|
|
8
8
|
require_hdl 'axis_valve_with_pipe.sv'
|
|
9
|
+
require_hdl 'independent_clock_fifo.sv'
|
|
9
10
|
|
|
10
11
|
new_m = SdlModule.new(name:File.basename(__FILE__,".rb"),out_sv_path:__dir__)
|
|
11
12
|
|
|
@@ -56,7 +56,7 @@ logic stream_en;
|
|
|
56
56
|
axi_stream_inf #(.DSIZE(axis_in.DSIZE),.USIZE(1)) split_out (.aclk(axis_in.aclk),.aresetn(axis_in.aresetn),.aclken(1'b1)) ;
|
|
57
57
|
axi_stream_inf #(.DSIZE(axis_in.DSIZE),.USIZE(1)) long_fifo_axis_out (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
|
|
58
58
|
axi_stream_inf #(.DSIZE(axi_wr.IDSIZE + axi_wr.ASIZE + axi_wr.LSIZE),.USIZE(1)) id_add_len_in (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
|
|
59
|
-
axi_inf #(.DSIZE(axi_wr.DSIZE),.IDSIZE(axi_wr.IDSIZE),.ASIZE(axi_wr.ASIZE),.LSIZE(axi_wr.LSIZE),.MODE(axi_wr.MODE),.ADDR_STEP(axi_wr.ADDR_STEP))
|
|
59
|
+
axi_inf #(.DSIZE(axi_wr.DSIZE),.IDSIZE(axi_wr.IDSIZE),.ASIZE(axi_wr.ASIZE),.LSIZE(axi_wr.LSIZE),.MODE(axi_wr.MODE),.ADDR_STEP(axi_wr.ADDR_STEP)) axi_wr_vcs_cp_R1977 (.axi_aclk(axi_wr.axi_aclk),.axi_aresetn(axi_wr.axi_aresetn)) ;
|
|
60
60
|
axi_stream_inf #(.DSIZE(axis_in.DSIZE),.USIZE(1)) pipe_axis (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
|
|
61
61
|
//==========================================================================
|
|
62
62
|
//-------- instance --------------------------------------------------------
|
|
@@ -94,13 +94,13 @@ independent_clock_fifo #(
|
|
|
94
94
|
axi4_wr_auxiliary_gen_without_resp axi4_wr_auxiliary_gen_without_resp_inst(
|
|
95
95
|
/* output */.stream_en (stream_en ),
|
|
96
96
|
/* axi_stream_inf.slaver */.id_add_len_in (id_add_len_in ),
|
|
97
|
-
/* axi_inf.master_wr_aux_no_resp */.axi_wr_aux (
|
|
97
|
+
/* axi_inf.master_wr_aux_no_resp */.axi_wr_aux (axi_wr_vcs_cp_R1977 )
|
|
98
98
|
);
|
|
99
99
|
vcs_axi4_comptable #(
|
|
100
100
|
.ORIGIN ("master_wr_aux_no_resp" ),
|
|
101
101
|
.TO ("master_wr" )
|
|
102
|
-
)
|
|
103
|
-
/* input */.origin (
|
|
102
|
+
)vcs_axi4_comptable_axi_wr_aux_R874_axi_wr_inst(
|
|
103
|
+
/* input */.origin (axi_wr_vcs_cp_R1977 ),
|
|
104
104
|
/* output */.to (axi_wr )
|
|
105
105
|
);
|
|
106
106
|
axis_valve_with_pipe #(
|
|
@@ -112,30 +112,30 @@ axis_valve_with_pipe #(
|
|
|
112
112
|
);
|
|
113
113
|
//==========================================================================
|
|
114
114
|
//-------- expression ------------------------------------------------------
|
|
115
|
-
|
|
115
|
+
always@(posedge axis_in.aclk,negedge axis_in.aresetn) begin
|
|
116
116
|
if(~axis_in.aresetn)begin
|
|
117
|
-
|
|
117
|
+
id <= 0;
|
|
118
118
|
end
|
|
119
119
|
else if(split_out.axis_tvalid && split_out.axis_tready && split_out.axis_tlast)begin
|
|
120
|
-
|
|
120
|
+
id <= (id+1);
|
|
121
121
|
end
|
|
122
122
|
else begin
|
|
123
|
-
|
|
123
|
+
id <= id;
|
|
124
124
|
end
|
|
125
125
|
end
|
|
126
126
|
|
|
127
|
-
assign
|
|
128
|
-
assign
|
|
129
|
-
assign
|
|
130
|
-
assign
|
|
131
|
-
assign
|
|
132
|
-
assign
|
|
127
|
+
assign addr_s = addr_cur;
|
|
128
|
+
assign len_s = split_out.axis_tcnt;
|
|
129
|
+
assign id_add_len_in.axis_tvalid = ~fifo_empty;
|
|
130
|
+
assign id_add_len_in.axis_tdata = fifo_rdata;
|
|
131
|
+
assign id_add_len_in.axis_tlast = "1'b1";
|
|
132
|
+
assign rd_en = id_add_len_in.axis_tready;
|
|
133
133
|
|
|
134
|
-
assign
|
|
135
|
-
assign
|
|
136
|
-
assign
|
|
137
|
-
assign
|
|
138
|
-
assign
|
|
139
|
-
assign
|
|
134
|
+
assign axi_wr.axi_wdata = pipe_axis.axis_tdata;
|
|
135
|
+
assign axi_wr.axi_wstrb = ~pipe_axis.axis_tkeep;
|
|
136
|
+
assign axi_wr.axi_wvalid = pipe_axis.axis_tvalid;
|
|
137
|
+
assign axi_wr.axi_wlast = pipe_axis.axis_tlast;
|
|
138
|
+
assign axi_wr.axi_bready = 1'b1;
|
|
139
|
+
assign pipe_axis.axis_tready = axi_wr.axi_wready;
|
|
140
140
|
|
|
141
141
|
endmodule
|