siliconcompiler 0.28.9__py3-none-any.whl → 0.29.1__py3-none-any.whl

siliconcompiler/tools/openroad/scripts/sc_route.tcl

@@ -1,143 +0,0 @@
-##########################################################
-# ROUTING
-##########################################################
-
-#######################
-# Helper functions
-#######################
-
-proc insert_fillers { } {
-  upvar sc_filler sc_filler
-  global sc_mainlib
-
-  set fillers $sc_filler
-  if { [lindex [sc_cfg_tool_task_get var dpl_use_decap_fillers] 0] == "true" } {
-    lappend fillers {*}[sc_cfg_get library $sc_mainlib asic cells decap]
-  }
-  if { $fillers != "" } {
-    filler_placement $fillers
-  }
-
-  check_placement -verbose
-
-  global_connect
-}
-
-#######################
-# Add Fillers
-#######################
-
-insert_fillers
-
-######################
-# Setup detailed route options
-######################
-
-foreach via $openroad_drt_default_vias {
-  utl::info FLW 1 "Marking $via a default routing via"
-  detailed_route_set_default_via $via
-}
-foreach layer $openroad_drt_unidirectional_layers {
-  utl::info FLW 1 "Marking $layer as a unidirectional routing layer"
-  detailed_route_set_unidirectional_layer $layer
-}
-
-######################
-# GLOBAL ROUTE
-######################
-
-# Pin access
-if { $openroad_grt_use_pin_access == "true" } {
-  set openroad_pin_access_args []
-  if { $openroad_drt_process_node != "false" } {
-    lappend openroad_pin_access_args "-db_process_node" $openroad_drt_process_node
-  }
-
-  pin_access -bottom_routing_layer $sc_minmetal \
-    -top_routing_layer $sc_maxmetal \
-    {*}$openroad_pin_access_args
-}
-
-set sc_grt_arguments []
-if { $openroad_grt_allow_congestion == "true" } {
-  lappend sc_grt_arguments "-allow_congestion"
-}
-if { $openroad_grt_allow_overflow == "true" } {
-  lappend sc_grt_arguments "-allow_overflow"
-}
-
-global_route -guide_file "./route.guide" \
-  -congestion_iterations $openroad_grt_overflow_iter \
-  -congestion_report_file "reports/${sc_design}_congestion.rpt" \
-  -verbose \
-  {*}$sc_grt_arguments
-
-######################
-# Report and Repair Antennas
-######################
-
-estimate_parasitics -global_routing
-if {
-  $openroad_ant_check == "true" &&
-  [check_antennas -report_file "reports/${sc_design}_antenna.rpt"] != 0
-} {
-  if {
-    $openroad_ant_repair == "true" &&
-    [llength [sc_cfg_get library $sc_mainlib asic cells antenna]] != 0
-  } {
-    set sc_antenna [lindex [sc_cfg_get library $sc_mainlib asic cells antenna] 0]
-
-    # Remove filler cells before attempting to repair antennas
-    remove_fillers
-
-    repair_antenna $sc_antenna \
-      -iterations $openroad_ant_iterations \
-      -ratio_margin $openroad_ant_margin
-
-    # Add filler cells back
-    insert_fillers
-
-    # Check antennas again to get final report
-    check_antennas -report_file "reports/${sc_design}_antenna_post_repair.rpt"
-  }
-}
-
-######################
-# Detailed Route
-######################
-
-set openroad_drt_arguments []
-if { $openroad_drt_disable_via_gen == "true" } {
-  lappend openroad_drt_arguments "-disable_via_gen"
-}
-if { $openroad_drt_process_node != "" } {
-  lappend openroad_drt_arguments "-db_process_node" $openroad_drt_process_node
-}
-if { $openroad_drt_via_in_pin_bottom_layer != "" } {
-  lappend openroad_drt_arguments "-via_in_pin_bottom_layer" $openroad_drt_via_in_pin_bottom_layer
-}
-if { $openroad_drt_via_in_pin_top_layer != "" } {
-  lappend openroad_drt_arguments "-via_in_pin_top_layer" $openroad_drt_via_in_pin_top_layer
-}
-if { $openroad_drt_repair_pdn_vias != "" } {
-  lappend openroad_drt_arguments "-repair_pdn_vias" $openroad_drt_repair_pdn_vias
-}
-
-detailed_route -save_guide_updates \
-  -output_drc "reports/${sc_design}_drc.rpt" \
-  -output_maze "reports/${sc_design}_maze.log" \
-  -bottom_routing_layer $sc_minmetal \
-  -top_routing_layer $sc_maxmetal \
-  -verbose 1 \
-  {*}$openroad_drt_arguments
-
-#########################
-# Correct violations with the power grid
-#########################
-
-if { $openroad_drt_via_repair_post_route == "true" } {
-  repair_pdn_vias -all
-}
-
-# estimate for metrics
-estimate_parasitics -global_routing

siliconcompiler/tools/openroad/scripts/sc_screenshot.tcl

@@ -1,18 +0,0 @@
-gui::save_display_controls
-
-set sc_resolution \
-  [lindex [sc_cfg_tool_task_get {var} show_vertical_resolution] 0]
-
-sc_image_setup_default
-
-sc_save_image "screenshot" "outputs/${sc_design}.png" $sc_resolution
-
-gui::restore_display_controls
-
-if {
-  [sc_cfg_tool_task_exists {var} include_report_images] &&
-  [lindex [sc_cfg_tool_task_get {var} include_report_images] 0]
-  == "true"
-} {
-  source -echo "${sc_refdir}/sc_write_images.tcl"
-}

siliconcompiler/tools/openroad/scripts/sc_write_images.tcl

@@ -1,393 +0,0 @@
-# Adopted from https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/blob/3f9740e6b3643835e918d78ae1d377d65af0f0fb/flow/scripts/save_images.tcl
-
-proc sc_image_heatmap { name ident image_name title { allow_bin_adjust 1 } } {
-  global openroad_ord_heatmap_bins_x
-  global openroad_ord_heatmap_bins_y
-
-  file mkdir reports/images/heatmap
-
-  gui::set_heatmap $ident ShowLegend 1
-  gui::set_heatmap $ident ShowNumbers 1
-
-  if { $allow_bin_adjust } {
-    set heatmap_xn $openroad_ord_heatmap_bins_x
-    set heatmap_yn $openroad_ord_heatmap_bins_y
-
-    if { $heatmap_xn < 1 } {
-      set heatmap_xn 1
-    }
-    if { $heatmap_yn < 1 } {
-      set heatmap_yn 1
-    }
-
-    set min_heatmap_bin 1.0
-    set max_heatmap_bin 100.0
-
-    set box [[ord::get_db_block] getDieArea]
-    set heatmap_x [expr { [ord::dbu_to_microns [$box dx]] / $heatmap_xn }]
-    set heatmap_y [expr { [ord::dbu_to_microns [$box dy]] / $heatmap_yn }]
-
-    if { $heatmap_x < $min_heatmap_bin } {
-      set heatmap_x $min_heatmap_bin
-    } elseif { $heatmap_x > $max_heatmap_bin } {
-      set heatmap_x $max_heatmap_bin
-    }
-    if { $heatmap_y < $min_heatmap_bin } {
-      set heatmap_y $min_heatmap_bin
-    } elseif { $heatmap_y > $max_heatmap_bin } {
-      set heatmap_y $max_heatmap_bin
-    }
-    gui::set_heatmap $ident GridX $heatmap_x
-    gui::set_heatmap $ident GridY $heatmap_y
-  }
-
-  gui::set_heatmap $ident rebuild
-
-  if { ![gui::get_heatmap_bool $ident has_data] } {
-    return
-  }
-
-  gui::set_display_controls "Heat Maps/${name}" visible true
-
-  sc_save_image "$title heatmap" reports/images/heatmap/${image_name}
-
-  gui::set_display_controls "Heat Maps/${name}" visible false
-}
-
-proc sc_image_placement { } {
-  if { ![sc_has_placed_instances] } {
-    return
-  }
-
-  global sc_design
-
-  sc_image_setup_default
-
-  # The placement view without routing
-  gui::set_display_controls "Layers/*" visible false
-  gui::set_display_controls "Instances/Physical/*" visible false
-
-  sc_save_image "placement" reports/images/${sc_design}.placement.png
-}
-
-proc sc_image_routing { } {
-  if { ![sc_has_routing] } {
-    return
-  }
-
-  global sc_design
-
-  sc_image_setup_default
-
-  gui::set_display_controls "Nets/Power" visible false
-  gui::set_display_controls "Nets/Ground" visible false
-
-  sc_save_image "routing" reports/images/${sc_design}.routing.png
-}
-
-proc sc_image_everything { } {
-  global sc_design
-
-  sc_image_setup_default
-  sc_save_image "snapshot" reports/images/${sc_design}.png
-}
-
-proc sc_image_irdrop { net corner } {
-  if { ![sc_has_placed_instances] || [sc_has_unplaced_instances] } {
-    return
-  }
-
-  sc_image_setup_default
-
-  file mkdir reports/images/heatmap/irdrop
-
-  # suppress error message related to failed analysis,
-  # that is okay, we just won't take a screenshot
-  set msgs "38 39 69"
-  foreach msg $msgs {
-    suppress_message PSM $msg
-  }
-  set failed [catch { analyze_power_grid -net $net -corner $corner -source_type STRAPS } err]
-  foreach msg $msgs {
-    unsuppress_message PSM $msg
-  }
-  if { $failed } {
-    utl::warn FLW 1 "Unable to generate IR drop heatmap for $net on $corner"
-    return
-  }
-
-  foreach layer [[ord::get_db_tech] getLayers] {
-    if { [$layer getRoutingLevel] == 0 } {
-      continue
-    }
-    set layer_name [$layer getName]
-
-    gui::set_heatmap IRDrop Net $net
-    gui::set_heatmap IRDrop Corner $corner
-    gui::set_heatmap IRDrop Layer $layer_name
-    gui::set_heatmap IRDrop rebuild
-
-    sc_image_heatmap "IR Drop" \
-      "IRDrop" \
-      "irdrop/${net}.${corner}.${layer_name}.png" \
-      "IR drop for $net on $layer_name for $corner"
-  }
-}
-
-proc sc_image_routing_congestion { } {
-  if { ![sc_has_global_routing] } {
-    return
-  }
-
-  sc_image_setup_default
-
-  sc_image_heatmap "Routing Congestion" \
-    "Routing" \
-    "routing_congestion.png" \
-    "routing congestion" \
-    0
-}
-
-proc sc_image_estimated_routing_congestion { } {
-  if { ![sc_has_placed_instances] } {
-    return
-  }
-
-  sc_image_setup_default
-
-  suppress_message GRT 10
-  catch {
-    sc_image_heatmap "Estimated Congestion (RUDY)" \
-      "RUDY" \
-      "estimated_routing_congestion.png" \
-      "estimated routing congestion" \
-      0
-  } err
-  unsuppress_message GRT 10
-}
-
-proc sc_image_power_density { } {
-  if { ![sc_has_placed_instances] } {
-    return
-  }
-
-  sc_image_setup_default
-
-  file mkdir reports/images/heatmap/power_density
-
-  foreach corner [sta::corners] {
-    set corner_name [$corner name]
-
-    gui::set_heatmap Power Corner $corner_name
-    gui::set_heatmap Power rebuild
-
-    sc_image_heatmap "Power Density" \
-      "Power" \
-      "power_density/${corner_name}.png" \
-      "power density for $corner_name"
-  }
-}
-
-proc sc_image_placement_density { } {
-  if { ![sc_has_placed_instances] } {
-    return
-  }
-
-  sc_image_setup_default
-
-  sc_image_heatmap "Placement Density" \
-    "Placement" \
-    "placement_density.png" \
-    "placement density"
-}
-
-proc sc_image_clocks { } {
-  if { ![sc_has_placed_instances] } {
-    return
-  }
-
-  global sc_design
-  sc_image_setup_default
-
-  # The clock view: all clock nets and buffers
-  gui::set_display_controls "Layers/*" visible true
-  gui::set_display_controls "Nets/*" visible false
-  gui::set_display_controls "Nets/Clock" visible true
-  gui::set_display_controls "Instances/*" visible false
-  gui::set_display_controls "Instances/StdCells/Clock tree/*" visible true
-  if { [select -name "clk*" -type Inst] == 0 } {
-    # Nothing selected
-    return
-  }
-
-  sc_save_image "clocks" reports/images/${sc_design}.clocks.png
-}
-
-proc sc_image_clocktree { } {
-  gui::show_widget "Clock Tree Viewer"
-  global sc_scenarios
-  global sc_design
-
-  sc_image_setup_default
-  gui::set_display_controls "Layers/*" visible true
-  gui::set_display_controls "Nets/*" visible false
-  gui::set_display_controls "Nets/Clock" visible true
-
-  set clock_state []
-  foreach clock [all_clocks] {
-    lappend clock_state $clock [$clock is_propagated]
-  }
-  set_propagated_clock [all_clocks]
-
-  file mkdir reports/images/clocks
-  foreach clock [get_clocks *] {
-    if { [llength [get_property $clock sources]] == 0 } {
-      # Skip virtual clocks
-      continue
-    }
-    file mkdir reports/images/clocktree
-
-    set clock_name [get_name $clock]
-    foreach corner $sc_scenarios {
-      set path reports/images/clocktree/${clock_name}.${corner}.png
-      utl::info FLW 1 "Saving \"$clock_name\" clock tree for $corner to $path"
-      save_clocktree_image $path \
-        -clock $clock_name \
-        -width 1024 \
-        -height 1024 \
-        -corner $corner
-    }
-
-    if { [info commands gui::select_clockviewer_clock] != "" } {
-      gui::select_clockviewer_clock ${clock_name}
-      sc_save_image "clock - ${clock_name}" reports/images/clocks/${sc_design}.${clock_name}.png
-    }
-  }
-
-  foreach {clock state} $clock_state {
-    if { $state } {
-      set_propagated_clock $clock
-    } else {
-      unset_propagated_clock $clock
-    }
-  }
-
-  gui::hide_widget "Clock Tree Viewer"
-}
-
-proc sc_image_optimizer { } {
-  global sc_design
-  sc_image_setup_default
-
-  # The resizer view: all instances created by the resizer grouped
-  gui::set_display_controls "Layers/*" visible false
-  gui::set_display_controls "Instances/*" visible true
-  gui::set_display_controls "Instances/Physical/*" visible false
-
-  set hold_count [select -name "hold*" -type Inst -highlight 0] ;# green
-  set input_count [select -name "input*" -type Inst -highlight 1] ;# yellow
-  set output_count [select -name "output*" -type Inst -highlight 1]
-  set repeater_count [select -name "repeater*" -type Inst -highlight 3] ;# magenta
-  set fanout_count [select -name "fanout*" -type Inst -highlight 3]
-  set load_slew_count [select -name "load_slew*" -type Inst -highlight 3]
-  set max_cap_count [select -name "max_cap*" -type Inst -highlight 3]
-  set max_length_count [select -name "max_length*" -type Inst -highlight 3]
-  set wire_count [select -name "wire*" -type Inst -highlight 3]
-  set rebuffer_count [select -name "rebuffer*" -type Inst -highlight 4] ;# red
-  set split_count [select -name "split*" -type Inst -highlight 5] ;# dark green
-
-  set select_count [expr {
-    $hold_count +
-    $input_count +
-    $output_count +
-    $repeater_count +
-    $fanout_count +
-    $load_slew_count +
-    $max_cap_count +
-    $max_length_count +
-    $wire_count +
-    $rebuffer_count +
-    $split_count
-  }]
-
-  if { $select_count == 0 } {
-    # Nothing selected
-    return
-  }
-
-  sc_save_image "optimizer" reports/images/${sc_design}.optimizer.png
-}
-
-proc sc_image_markers { } {
-  global sc_design
-  sc_image_setup_default
-
-  file mkdir reports/images/markers
-  foreach markerdb [[ord::get_db_block] getMarkerCategories] {
-    if { [$markerdb getMarkerCount] == 0 } {
-      continue
-    }
-
-    gui::select_marker_category $markerdb
-
-    sc_save_image \
-      "markers - [$markerdb getName]" \
-      reports/images/markers/${sc_design}.[$markerdb getName].png
-  }
-
-  gui::select_marker_category NULL
-}
-
-# Setup
-file mkdir reports/images
-gui::save_display_controls
-sc_image_setup_default
-
-# General images
-sc_image_everything
-sc_image_placement
-sc_image_routing
-
-# Markers
-sc_image_markers
-
-# Heatmaps
-if { [sc_cfg_tool_task_check_in_list placement_density var reports] } {
-  sc_image_placement_density
-}
-
-if { [sc_cfg_tool_task_check_in_list routing_congestion var reports] } {
-  sc_image_estimated_routing_congestion
-  sc_image_routing_congestion
-}
-
-if { [sc_cfg_tool_task_check_in_list power var reports] } {
-  if { [sc_cfg_tool_task_check_in_list power_density var reports] } {
-    sc_image_power_density
-  }
-
-  if { [sc_cfg_tool_task_check_in_list ir_drop var reports] } {
-    foreach net [sc_psm_check_nets] {
-      foreach corner $sc_scenarios {
-        sc_image_irdrop $net $corner
-      }
-    }
-  }
-}
-
-# Clocks
-if { [sc_cfg_tool_task_check_in_list clock_placement var reports] } {
-  sc_image_clocks
-}
-if { [sc_cfg_tool_task_check_in_list clock_trees var reports] } {
-  sc_image_clocktree
-}
-
-# Optimizations
-if { [sc_cfg_tool_task_check_in_list optimization_placement var reports] } {
-  sc_image_optimizer
-}
-
-# Restore
-sc_image_clear_selection
-gui::restore_display_controls

siliconcompiler/tools/yosys/yosys.py

@@ -1,148 +0,0 @@
-'''
-Yosys is a framework for RTL synthesis that takes synthesizable
-Verilog-2005 design and converts it to BLIF, EDIF, BTOR, SMT,
-Verilog netlist etc. The tool supports logical synthesis and
-tech mapping to ASIC standard cell libraries, FPGA architectures.
-In addition it has built in formal methods for property and
-equivalence checking.
-
-Documentation: https://yosyshq.readthedocs.io/projects/yosys/en/latest/
-
-Sources: https://github.com/YosysHQ/yosys
-
-Installation: https://github.com/YosysHQ/yosys
-'''
-
-import re
-import json
-from siliconcompiler import sc_open
-from siliconcompiler.tools._common import get_tool_task, record_metric
-from siliconcompiler.targets import asap7_demo
-
-
-######################################################################
-# Make Docs
-######################################################################
-def make_docs(chip):
-    chip.use(asap7_demo)
-
-
-################################
-# Setup Tool (pre executable)
-################################
-def setup(chip):
-    ''' Tool specific function to run before step execution
-    '''
-
-    # If the 'lock' bit is set, don't reconfigure.
-    tool = 'yosys'
-    refdir = 'tools/' + tool
-    step = chip.get('arg', 'step')
-    index = chip.get('arg', 'index')
-    _, task = get_tool_task(chip, step, index)
-
-    # Standard Setup
-    chip.set('tool', tool, 'exe', 'yosys')
-    chip.set('tool', tool, 'vswitch', '--version')
-    chip.set('tool', tool, 'version', '>=0.41', clobber=False)
-    chip.set('tool', tool, 'format', 'tcl', clobber=False)
-
-    # Task Setup
-    # common to all
-    option = []
-    if chip.get('option', 'breakpoint', step=step, index=index):
-        option.append('-C')
-    option.append('-c')
-    chip.set('tool', tool, 'task', task, 'option', option, step=step, index=index, clobber=False)
-    chip.set('tool', tool, 'task', task, 'refdir', refdir, step=step, index=index,
-             package='siliconcompiler', clobber=False)
-    chip.set('tool', tool, 'task', task, 'regex', 'warnings', "Warning:",
-             step=step, index=index, clobber=False)
-    chip.set('tool', tool, 'task', task, 'regex', 'errors', "^ERROR",
-             step=step, index=index, clobber=False)
-
-
-################################
-# Version Check
-################################
-def parse_version(stdout):
-    # Yosys 0.9+3672 (git sha1 014c7e26, gcc 7.5.0-3ubuntu1~18.04 -fPIC -Os)
-    return stdout.split()[1]
-
-
-def normalize_version(version):
-    # Replace '+', which represents a "local version label", with '-', which is
-    # an "implicit post release number".
-    return version.replace('+', '-')
-
-
-def syn_setup(chip):
-    ''' Helper method for configs specific to synthesis tasks.
-    '''
-
-    # Generic tool setup.
-    setup(chip)
-
-    tool = 'yosys'
-    step = chip.get('arg', 'step')
-    index = chip.get('arg', 'index')
-    _, task = get_tool_task(chip, step, index)
-    design = chip.top()
-
-    # Set yosys script path.
-    chip.set('tool', tool, 'task', task, 'script', 'sc_syn.tcl',
-             step=step, index=index, clobber=False)
-
-    # Input/output requirements.
-    chip.set('tool', tool, 'task', task, 'input', design + '.v', step=step, index=index)
-    chip.set('tool', tool, 'task', task, 'output', design + '.vg', step=step, index=index)
-
-
-##################################################
-def syn_post_process(chip):
-    ''' Tool specific function to run after step execution
-    '''
-
-    step = chip.get('arg', 'step')
-    index = chip.get('arg', 'index')
-
-    with sc_open("reports/stat.json") as f:
-        metrics = json.load(f)
-        if "design" in metrics:
-            metrics = metrics["design"]
-
-        if "area" in metrics:
-            record_metric(chip, step, index, 'cellarea',
-                          float(metrics["area"]),
-                          "reports/stat.json",
-                          source_unit='um^2')
-        if "num_cells" in metrics:
-            record_metric(chip, step, index, 'cells',
-                          metrics["num_cells"],
-                          "reports/stat.json")
-        if "num_wire_bits" in metrics:
-            record_metric(chip, step, index, 'nets',
-                          metrics["num_wire_bits"],
-                          "reports/stat.json")
-        if "num_port_bits" in metrics:
-            record_metric(chip, step, index, 'pins',
-                          metrics["num_port_bits"],
-                          "reports/stat.json")
-
-    registers = None
-    with sc_open(f"{step}.log") as f:
-        for line in f:
-            line_registers = re.findall(r"^\s*mapped ([0-9]+) \$_DFF.*", line)
-            if line_registers:
-                if registers is None:
-                    registers = 0
-                registers += int(line_registers[0])
-    if registers is not None:
-        record_metric(chip, step, index, 'registers', registers, f"{step}.log")
-
-
-##################################################
-if __name__ == "__main__":
-
-    chip = make_docs()
-    chip.write_manifest("yosys.json")