siliconcompiler 0.28.9__py3-none-any.whl → 0.29.1__py3-none-any.whl

siliconcompiler/tools/openroad/scripts/common/read_input_files.tcl

@@ -0,0 +1,59 @@
+###############################
+# Read design files
+###############################
+
+if { [sc_has_input_files odb "input layout odb"] } {
+    foreach odb_file [sc_get_input_files odb "input layout odb"] {
+        puts "Reading ODB: ${odb_file}"
+        read_db $odb_file
+    }
+} else {
+    set sc_libtype [sc_cfg_get library $sc_mainlib asic libarch]
+    set sc_techlef [sc_cfg_get pdk $sc_pdk aprtech openroad $sc_stackup $sc_libtype lef]
+
+    # Read techlef
+    puts "Reading techlef: ${sc_techlef}"
+    read_lef $sc_techlef
+
+    # Read Lefs
+    foreach lib "$sc_targetlibs $sc_macrolibs" {
+        foreach lef_file [sc_cfg_get library $lib output $sc_stackup lef] {
+            puts "Reading lef: ${lef_file}"
+            read_lef $lef_file
+        }
+    }
+
+    if { [file exists "inputs/${sc_design}.def"] } {
+        # Read DEF
+        # get from previous step
+        puts "Reading DEF: inputs/${sc_design}.def"
+        read_def "inputs/${sc_design}.def"
+    } elseif { [sc_cfg_exists input layout def] } {
+        # Read DEF
+        set sc_def [lindex [sc_cfg_get input layout def] 0]
+        puts "Reading DEF: ${sc_def}"
+        read_def $sc_def
+    } elseif { [file exists "inputs/${sc_design}.vg"] } {
+        # Read Verilog
+        puts "Reading netlist verilog: inputs/${sc_design}.vg"
+        read_verilog "inputs/${sc_design}.vg"
+        link_design $sc_design
+    } elseif { [sc_cfg_exists input netlist verilog] } {
+        # Read Verilog
+        foreach netlist [sc_cfg_get input netlist verilog] {
+            puts "Reading netlist verilog: ${netlist}"
+            read_verilog $netlist
+        }
+        link_design $sc_design
+    } else {
+        utl::error FLW 1 "No input files available"
+    }
+
+    # Handle global connect setup
+    if { [sc_cfg_tool_task_exists {file} global_connect] } {
+        foreach global_connect [sc_cfg_tool_task_get {file} global_connect] {
+            puts "Loading global connect configuration: ${global_connect}"
+            source $global_connect
+        }
+    }
+}

siliconcompiler/tools/openroad/scripts/common/read_liberty.tcl

@@ -0,0 +1,20 @@
+set sc_scenarios [dict keys [sc_cfg_get constraint timing]]
+set sc_delaymodel [sc_cfg_get asic delaymodel]
+
+# Read Liberty
+utl::info FLW 1 "Defining timing corners: $sc_scenarios"
+define_corners {*}$sc_scenarios
+foreach lib "$sc_targetlibs $sc_macrolibs" {
+    #Liberty
+    foreach corner $sc_scenarios {
+        foreach libcorner [sc_cfg_get constraint timing $corner libcorner] {
+            if { [sc_cfg_exists library $lib output $libcorner $sc_delaymodel] } {
+                foreach lib_file [sc_cfg_get library $lib output $libcorner $sc_delaymodel] {
+                    puts "Reading liberty file for ${corner} ($libcorner): ${lib_file}"
+                    read_liberty -corner $corner $lib_file
+                }
+                break
+            }
+        }
+    }
+}

siliconcompiler/tools/openroad/scripts/common/read_timing_constraints.tcl

@@ -0,0 +1,16 @@
+###############################
+# Read timing constraints
+###############################
+
+if { [sc_has_input_files sdc "input constraint sdc"] } {
+    foreach sdc [sc_get_input_files sdc "input constraint sdc"] {
+        puts "Reading SDC: ${sdc}"
+        read_sdc $sdc
+    }
+} else {
+    # fall back on default auto generated constraints file
+    set sdc [sc_cfg_tool_task_get {file} opensta_generic_sdc]
+    puts "Reading SDC: ${sdc}"
+    utl::warn FLW 1 "Defaulting back to default SDC"
+    read_sdc "${sdc}"
+}

siliconcompiler/tools/openroad/scripts/common/reports.tcl

@@ -0,0 +1,180 @@
+###############################
+# Report Metrics
+###############################
+
+# Setup reports directories
+file mkdir reports/timing
+file mkdir reports/power
+file mkdir reports/markers
+
+set fields "{capacitance slew input_pins hierarcial_pins net fanout}"
+set sta_top_n_paths [lindex [sc_cfg_tool_task_get var sta_top_n_paths] 0]
+set PREFIX "SC_METRIC:"
+
+if { [sc_cfg_tool_task_check_in_list setup var reports] } {
+    puts "$PREFIX report_checks -path_delay max"
+    tee -file reports/timing/setup.rpt \
+        "report_checks -fields $fields -path_delay max -format full_clock_expanded"
+    tee -file reports/timing/setup.topN.rpt -quiet \
+        "report_checks -fields $fields -path_delay max -group_count $sta_top_n_paths"
+
+    puts "$PREFIX setupslack"
+    tee -file reports/timing/worst_slack.setup.rpt \
+        "report_worst_slack -max"
+    report_worst_slack_metric -setup
+
+    puts "$PREFIX tns"
+    tee -file reports/timing/total_negative_slack.rpt \
+        "report_tns"
+    report_tns_metric -setup
+}
+
+if { [sc_cfg_tool_task_check_in_list hold var reports] } {
+    puts "$PREFIX report_checks -path_delay min"
+    tee -file reports/timing/hold.rpt \
+        "report_checks -fields $fields -path_delay min -format full_clock_expanded"
+    tee -file reports/timing/hold.topN.rpt -quiet \
+        "report_checks -fields $fields -path_delay min -group_count $sta_top_n_paths"
+
+    puts "$PREFIX holdslack"
+    tee -file reports/timing/worst_slack.hold.rpt \
+        "report_worst_slack -min"
+    report_worst_slack_metric -hold
+
+    report_tns_metric -hold
+}
+
+if { [sc_cfg_tool_task_check_in_list unconstrained var reports] } {
+    puts "$PREFIX unconstrained"
+    tee -file reports/timing/unconstrained.rpt \
+        "report_checks -fields $fields -unconstrained -format full_clock_expanded"
+    tee -file reports/timing/unconstrained.topN.rpt -quiet \
+        "report_checks -fields $fields -unconstrained -group_count $sta_top_n_paths"
+}
+
+if {
+    [sc_cfg_tool_task_check_in_list clock_skew var reports] &&
+    [llength [all_clocks]] > 0
+} {
+    puts "$PREFIX clock_skew"
+    tee -file reports/timing/skew.setup.rpt \
+        "report_clock_skew -setup -digits 4"
+    report_clock_skew_metric -setup
+    tee -file reports/timing/skew.hold.rpt \
+        "report_clock_skew -hold -digits 4"
+    report_clock_skew_metric -hold
+}
+
+if { [sc_cfg_tool_task_check_in_list drv_violations var reports] } {
+    puts "$PREFIX DRV violators"
+    tee -file reports/timing/drv_violators.rpt \
+        "report_check_types -max_slew -max_capacitance -max_fanout -violators"
+    report_erc_metrics
+
+    puts "$PREFIX floating nets"
+    tee -file reports/floating_nets.rpt \
+        "report_floating_nets -verbose"
+}
+
+utl::metric_int "timing__clocks" [llength [all_clocks]]
+
+if { [sc_cfg_tool_task_check_in_list fmax var reports] } {
+    puts "$PREFIX fmax"
+    # Model on: https://github.com/The-OpenROAD-Project/OpenSTA/blob/f913c3ddbb3e7b4364ed4437c65ac78c4da9174b/tcl/Search.tcl#L1078
+    set fmax_metric 0
+    foreach clk [sta::sort_by_name [all_clocks]] {
+        set clk_name [get_name $clk]
+        set min_period [sta::find_clk_min_period $clk 1]
+        if { $min_period == 0.0 } {
+            continue
+        }
+        set fmax [expr { 1.0 / $min_period }]
+        utl::metric_float "timing__fmax__clock:${clk_name}" $fmax
+        puts "$clk_name fmax = [format %.2f [expr { $fmax / 1e6 }]] MHz"
+        set fmax_metric [expr { max($fmax_metric, $fmax) }]
+    }
+    if { $fmax_metric > 0 } {
+        utl::metric_float "timing__fmax" $fmax_metric
+    }
+}
+
+# get logic depth of design
+utl::metric_int "design__logic__depth" [sc_count_logic_depth]
+
+if { [sc_cfg_tool_task_check_in_list power var reports] } {
+    puts "$PREFIX power"
+    foreach corner [sta::corners] {
+        set corner_name [$corner name]
+        puts "Power for corner: $corner_name"
+
+        tee -file reports/power/${corner_name}.rpt \
+            "report_power -corner $corner_name"
+    }
+    report_power_metric -corner [sc_cfg_tool_task_get var power_corner]
+}
+
+puts "$PREFIX cellarea"
+report_design_area
+report_design_area_metrics
+
+# get number of nets in design
+utl::metric_int "design__nets" [llength [[ord::get_db_block] getNets]]
+
+# get number of registers
+utl::metric_int "design__registers" [llength [all_registers]]
+
+# get number of buffers
+set bufs 0
+set invs 0
+foreach inst [get_cells -hierarchical *] {
+    set cell [$inst cell]
+    if { $cell == "NULL" } {
+        continue
+    }
+    set liberty_cell [$cell liberty_cell]
+    if { $liberty_cell == "NULL" } {
+        continue
+    }
+    if { [$liberty_cell is_buffer] } {
+        incr bufs
+    } elseif { [$liberty_cell is_inverter] } {
+        incr invs
+    }
+}
+utl::metric_int "design__buffers" $bufs
+utl::metric_int "design__inverters" $invs
+
+# get number of unconstrained endpoints
+with_output_to_variable endpoints {check_setup -unconstrained_endpoints}
+set unconstrained_endpoints [regexp -all -inline {[0-9]+} $endpoints]
+if { $unconstrained_endpoints == "" } {
+    set unconstrained_endpoints 0
+}
+utl::metric_int "timing__unconstrained" $unconstrained_endpoints
+
+# Write markers
+foreach markerdb [[ord::get_db_block] getMarkerCategories] {
+    if { [$markerdb getMarkerCount] == 0 } {
+        continue
+    }
+
+    $markerdb writeTR "reports/markers/${sc_design}.[$markerdb getName].rpt"
+    $markerdb writeJSON "reports/markers/${sc_design}.[$markerdb getName].json"
+}
+
+utl::push_metrics_stage "sc__cellarea__{}"
+tee -file reports/cell_usage.rpt {report_cell_usage -verbose}
+
+foreach modinst [[ord::get_db_block] getModInsts] {
+    tee -quiet -append -file reports/cell_usage.rpt { puts "" }
+    tee -quiet -append -file reports/cell_usage.rpt {
+    puts "########################################################"
+}
+    tee -quiet -append -file reports/cell_usage.rpt { puts "" }
+
+    utl::metric "design__instance__name__in_module:[[$modinst getMaster] getName]" \
+        [$modinst getHierarchicalName]
+    tee -quiet -append -file reports/cell_usage.rpt \
+        "report_cell_usage -verbose [$modinst getHierarchicalName]"
+}
+utl::pop_metrics_stage

siliconcompiler/tools/openroad/scripts/common/screenshot.tcl

@@ -0,0 +1,18 @@
+gui::save_display_controls
+
+set sc_resolution \
+    [lindex [sc_cfg_tool_task_get {var} show_vertical_resolution] 0]
+
+sc_image_setup_default
+
+sc_save_image "screenshot" "outputs/${sc_design}.png" $sc_resolution
+
+gui::restore_display_controls
+
+if {
+    [sc_cfg_tool_task_exists {var} include_report_images] &&
+    [lindex [sc_cfg_tool_task_get {var} include_report_images] 0]
+    == "true"
+} {
+    source -echo "${sc_refdir}/sc_write_images.tcl"
+}

siliconcompiler/tools/openroad/scripts/common/write_images.tcl

@@ -0,0 +1,395 @@
+# Adopted from https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/blob/3f9740e6b3643835e918d78ae1d377d65af0f0fb/flow/scripts/save_images.tcl
+
+proc sc_image_heatmap { name ident image_name title { allow_bin_adjust 1 } } {
+    set ord_heatmap_bins_x [lindex [sc_cfg_tool_task_get var ord_heatmap_bins_x] 0]
+    set ord_heatmap_bins_y [lindex [sc_cfg_tool_task_get var ord_heatmap_bins_y] 0]
+
+    file mkdir reports/images/heatmap
+
+    gui::set_heatmap $ident ShowLegend 1
+    gui::set_heatmap $ident ShowNumbers 1
+
+    if { $allow_bin_adjust } {
+        set heatmap_xn $ord_heatmap_bins_x
+        set heatmap_yn $ord_heatmap_bins_y
+
+        if { $heatmap_xn < 1 } {
+            set heatmap_xn 1
+        }
+        if { $heatmap_yn < 1 } {
+            set heatmap_yn 1
+        }
+
+        set min_heatmap_bin 1.0
+        set max_heatmap_bin 100.0
+
+        set box [[ord::get_db_block] getDieArea]
+        set heatmap_x [expr { [ord::dbu_to_microns [$box dx]] / $heatmap_xn }]
+        set heatmap_y [expr { [ord::dbu_to_microns [$box dy]] / $heatmap_yn }]
+
+        if { $heatmap_x < $min_heatmap_bin } {
+            set heatmap_x $min_heatmap_bin
+        } elseif { $heatmap_x > $max_heatmap_bin } {
+            set heatmap_x $max_heatmap_bin
+        }
+        if { $heatmap_y < $min_heatmap_bin } {
+            set heatmap_y $min_heatmap_bin
+        } elseif { $heatmap_y > $max_heatmap_bin } {
+            set heatmap_y $max_heatmap_bin
+        }
+        gui::set_heatmap $ident GridX $heatmap_x
+        gui::set_heatmap $ident GridY $heatmap_y
+    }
+
+    gui::set_heatmap $ident rebuild
+
+    if { ![gui::get_heatmap_bool $ident has_data] } {
+        return
+    }
+
+    gui::set_display_controls "Heat Maps/${name}" visible true
+
+    sc_save_image "$title heatmap" reports/images/heatmap/${image_name}
+
+    gui::set_display_controls "Heat Maps/${name}" visible false
+}
+
+proc sc_image_placement { } {
+    if { ![sc_has_placed_instances] } {
+        return
+    }
+
+    global sc_design
+
+    sc_image_setup_default
+
+    # The placement view without routing
+    gui::set_display_controls "Layers/*" visible false
+    gui::set_display_controls "Instances/Physical/*" visible false
+
+    sc_save_image "placement" reports/images/${sc_design}.placement.png
+}
+
+proc sc_image_routing { } {
+    if { ![sc_has_routing] } {
+        return
+    }
+
+    global sc_design
+
+    sc_image_setup_default
+
+    gui::set_display_controls "Nets/Power" visible false
+    gui::set_display_controls "Nets/Ground" visible false
+
+    sc_save_image "routing" reports/images/${sc_design}.routing.png
+}
+
+proc sc_image_everything { } {
+    global sc_design
+
+    sc_image_setup_default
+    sc_save_image "snapshot" reports/images/${sc_design}.png
+}
+
+proc sc_image_irdrop { net corner } {
+    if { ![sc_has_placed_instances] || [sc_has_unplaced_instances] } {
+        return
+    }
+
+    sc_image_setup_default
+
+    file mkdir reports/images/heatmap/irdrop
+
+    # suppress error message related to failed analysis,
+    # that is okay, we just won't take a screenshot
+    set msgs "38 39 69"
+    foreach msg $msgs {
+        suppress_message PSM $msg
+    }
+    set failed [catch { analyze_power_grid -net $net -corner $corner -source_type STRAPS } err]
+    foreach msg $msgs {
+        unsuppress_message PSM $msg
+    }
+    if { $failed } {
+        utl::warn FLW 1 "Unable to generate IR drop heatmap for $net on $corner"
+        return
+    }
+
+    foreach layer [[ord::get_db_tech] getLayers] {
+        if { [$layer getRoutingLevel] == 0 } {
+            continue
+        }
+        set layer_name [$layer getName]
+
+        gui::set_heatmap IRDrop Net $net
+        gui::set_heatmap IRDrop Corner $corner
+        gui::set_heatmap IRDrop Layer $layer_name
+        gui::set_heatmap IRDrop rebuild
+
+        sc_image_heatmap "IR Drop" \
+            "IRDrop" \
+            "irdrop/${net}.${corner}.${layer_name}.png" \
+            "IR drop for $net on $layer_name for $corner"
+    }
+}
+
+proc sc_image_routing_congestion { } {
+    if { ![sc_has_global_routing] } {
+        return
+    }
+
+    sc_image_setup_default
+
+    sc_image_heatmap "Routing Congestion" \
+        "Routing" \
+        "routing_congestion.png" \
+        "routing congestion" \
+        0
+}
+
+proc sc_image_estimated_routing_congestion { } {
+    if { ![sc_has_placed_instances] } {
+        return
+    }
+
+    sc_image_setup_default
+
+    suppress_message GRT 10
+    catch {
+        sc_image_heatmap "Estimated Congestion (RUDY)" \
+            "RUDY" \
+            "estimated_routing_congestion.png" \
+            "estimated routing congestion" \
+            0
+    } err
+    unsuppress_message GRT 10
+}
+
+proc sc_image_power_density { } {
+    if { ![sc_has_placed_instances] } {
+        return
+    }
+
+    sc_image_setup_default
+
+    file mkdir reports/images/heatmap/power_density
+
+    foreach corner [sta::corners] {
+        set corner_name [$corner name]
+
+        gui::set_heatmap Power Corner $corner_name
+        gui::set_heatmap Power rebuild
+
+        sc_image_heatmap "Power Density" \
+            "Power" \
+            "power_density/${corner_name}.png" \
+            "power density for $corner_name"
+    }
+}
+
+proc sc_image_placement_density { } {
+    if { ![sc_has_placed_instances] } {
+        return
+    }
+
+    sc_image_setup_default
+
+    sc_image_heatmap "Placement Density" \
+        "Placement" \
+        "placement_density.png" \
+        "placement density"
+}
+
+proc sc_image_clocks { } {
+    if { ![sc_has_placed_instances] } {
+        return
+    }
+
+    global sc_design
+    sc_image_setup_default
+
+    # The clock view: all clock nets and buffers
+    gui::set_display_controls "Layers/*" visible true
+    gui::set_display_controls "Nets/*" visible false
+    gui::set_display_controls "Nets/Clock" visible true
+    gui::set_display_controls "Instances/*" visible false
+    gui::set_display_controls "Instances/StdCells/Clock tree/*" visible true
+    if { [select -name "clk*" -type Inst] == 0 } {
+        # Nothing selected
+        return
+    }
+
+    sc_save_image "clocks" reports/images/${sc_design}.clocks.png
+}
+
+proc sc_image_clocktree { } {
+    gui::show_widget "Clock Tree Viewer"
+    global sc_design
+    global sc_scenarios
+
+    sc_image_setup_default
+    gui::set_display_controls "Layers/*" visible true
+    gui::set_display_controls "Nets/*" visible false
+    gui::set_display_controls "Nets/Clock" visible true
+
+    set clock_state []
+    foreach clock [all_clocks] {
+        lappend clock_state $clock [$clock is_propagated]
+    }
+    set_propagated_clock [all_clocks]
+
+    file mkdir reports/images/clocks
+    foreach clock [get_clocks *] {
+        if { [llength [get_property $clock sources]] == 0 } {
+            # Skip virtual clocks
+            continue
+        }
+        file mkdir reports/images/clocktree
+
+        set clock_name [get_name $clock]
+        foreach corner $sc_scenarios {
+            set path reports/images/clocktree/${clock_name}.${corner}.png
+            utl::info FLW 1 "Saving \"$clock_name\" clock tree for $corner to $path"
+            save_clocktree_image $path \
+                -clock $clock_name \
+                -width 1024 \
+                -height 1024 \
+                -corner $corner
+        }
+
+        if { [info commands gui::select_clockviewer_clock] != "" } {
+            gui::select_clockviewer_clock ${clock_name}
+            sc_save_image \
+                "clock - ${clock_name}" \
+                reports/images/clocks/${sc_design}.${clock_name}.png
+        }
+    }
+
+    foreach {clock state} $clock_state {
+        if { $state } {
+            set_propagated_clock $clock
+        } else {
+            unset_propagated_clock $clock
+        }
+    }
+
+    gui::hide_widget "Clock Tree Viewer"
+}
+
+proc sc_image_optimizer { } {
+    global sc_design
+    sc_image_setup_default
+
+    # The resizer view: all instances created by the resizer grouped
+    gui::set_display_controls "Layers/*" visible false
+    gui::set_display_controls "Instances/*" visible true
+    gui::set_display_controls "Instances/Physical/*" visible false
+
+    set hold_count [select -name "hold*" -type Inst -highlight 0] ;# green
+    set input_count [select -name "input*" -type Inst -highlight 1] ;# yellow
+    set output_count [select -name "output*" -type Inst -highlight 1]
+    set repeater_count [select -name "repeater*" -type Inst -highlight 3] ;# magenta
+    set fanout_count [select -name "fanout*" -type Inst -highlight 3]
+    set load_slew_count [select -name "load_slew*" -type Inst -highlight 3]
+    set max_cap_count [select -name "max_cap*" -type Inst -highlight 3]
+    set max_length_count [select -name "max_length*" -type Inst -highlight 3]
+    set wire_count [select -name "wire*" -type Inst -highlight 3]
+    set rebuffer_count [select -name "rebuffer*" -type Inst -highlight 4] ;# red
+    set split_count [select -name "split*" -type Inst -highlight 5] ;# dark green
+
+    set select_count [expr {
+        $hold_count +
+        $input_count +
+        $output_count +
+        $repeater_count +
+        $fanout_count +
+        $load_slew_count +
+        $max_cap_count +
+        $max_length_count +
+        $wire_count +
+        $rebuffer_count +
+        $split_count
+    }]
+
+    if { $select_count == 0 } {
+        # Nothing selected
+        return
+    }
+
+    sc_save_image "optimizer" reports/images/${sc_design}.optimizer.png
+}
+
+proc sc_image_markers { } {
+    global sc_design
+    sc_image_setup_default
+
+    file mkdir reports/images/markers
+    foreach markerdb [[ord::get_db_block] getMarkerCategories] {
+        if { [$markerdb getMarkerCount] == 0 } {
+            continue
+        }
+
+        gui::select_marker_category $markerdb
+
+        sc_save_image \
+            "markers - [$markerdb getName]" \
+            reports/images/markers/${sc_design}.[$markerdb getName].png
+    }
+
+    gui::select_marker_category NULL
+}
+
+# Setup
+file mkdir reports/images
+gui::save_display_controls
+sc_image_setup_default
+
+# General images
+sc_image_everything
+sc_image_placement
+sc_image_routing
+
+# Markers
+sc_image_markers
+
+# Heatmaps
+if { [sc_cfg_tool_task_check_in_list placement_density var reports] } {
+    sc_image_placement_density
+}
+
+if { [sc_cfg_tool_task_check_in_list routing_congestion var reports] } {
+    sc_image_estimated_routing_congestion
+    sc_image_routing_congestion
+}
+
+if { [sc_cfg_tool_task_check_in_list power var reports] } {
+    if { [sc_cfg_tool_task_check_in_list power_density var reports] } {
+        sc_image_power_density
+    }
+
+    if { [sc_cfg_tool_task_check_in_list ir_drop var reports] } {
+        foreach net [sc_psm_check_nets] {
+            foreach corner $sc_scenarios {
+                sc_image_irdrop $net $corner
+            }
+        }
+    }
+}
+
+# Clocks
+if { [sc_cfg_tool_task_check_in_list clock_placement var reports] } {
+    sc_image_clocks
+}
+if { [sc_cfg_tool_task_check_in_list clock_trees var reports] } {
+    sc_image_clocktree
+}
+
+# Optimizations
+if { [sc_cfg_tool_task_check_in_list optimization_placement var reports] } {
+    sc_image_optimizer
+}
+
+# Restore
+sc_image_clear_selection
+gui::restore_display_controls