siliconcompiler 0.28.9__py3-none-any.whl → 0.29.1__py3-none-any.whl

siliconcompiler/tools/openroad/scripts/{sc_rcx_bench.tcl → rcx/sc_rcx_bench.tcl}

@@ -1,18 +1,18 @@
 #https://github.com/The-OpenROAD-Project/OpenROAD/blob/9b52b1d9cfb532f9872739ffe482afb5ac9def92/src/rcx/calibration/script/generate_rules.tcl
 
 set openroad_bench_length \
-  [lindex [sc_cfg_tool_task_get {var} bench_length] 0]
+    [lindex [sc_cfg_tool_task_get {var} bench_length] 0]
 
 set sc_maxmetal \
-  [sc_get_layer_name [lindex [sc_cfg_tool_task_get {var} max_layer] 0]]
+    [sc_get_layer_name [lindex [sc_cfg_tool_task_get {var} max_layer] 0]]
 set openroad_top_metal_number [[[ord::get_db_tech] findLayer $sc_maxmetal] getRoutingLevel]
 
 # Creates the patterns and
 # store it in the database
 bench_wires \
-  -len $openroad_bench_length \
-  -met_cnt $openroad_top_metal_number \
-  -all
+    -len $openroad_bench_length \
+    -met_cnt $openroad_top_metal_number \
+    -all
 
 # Writes the verilog netlist
 # of the patterns

siliconcompiler/tools/openroad/scripts/sc_rcx.tcl

@@ -8,16 +8,9 @@ source ./sc_manifest.tcl > /dev/null
 # Schema Helper functions
 ###############################
 
-proc sc_get_layer_name { name } {
-  if { [string is integer $name] } {
-    set layer [[ord::get_db_tech] findRoutingLayer $name]
-    if { $layer == "NULL" } {
-      utl::error FLW 1 "$name is not a valid routing layer."
-    }
-    return [$layer getName]
-  }
-  return $name
-}
+set sc_refdir [sc_cfg_tool_task_get refdir]
+
+source "${sc_refdir}/common/procs.tcl"
 
 ##############################
 # Schema Adapter
@@ -29,8 +22,6 @@ set sc_index [sc_cfg_get arg index]
 set sc_flow [sc_cfg_get option flow]
 set sc_task [sc_cfg_get flowgraph $sc_flow $sc_step $sc_index task]
 
-set sc_refdir [sc_cfg_tool_task_get refdir]
-
 # Design
 set sc_design [sc_top]
 set sc_pdk [sc_cfg_get option pdk]
@@ -42,8 +33,6 @@ set sc_libtype [lindex [sc_cfg_tool_task_get {var} libtype] 0]
 # PDK Design Rules
 set sc_techlef [sc_cfg_get pdk $sc_pdk aprtech openroad $sc_stackup $sc_libtype lef]
 
-set sc_threads [sc_cfg_tool_task_get threads]
-
 ###############################
 # Read Files
 ###############################
@@ -56,8 +45,8 @@ read_lef $sc_techlef
 # Run task
 ###############################
 
-set_thread_count $sc_threads
+set_thread_count [sc_cfg_tool_task_get threads]
 
 utl::set_metrics_stage "sc__step__{}"
-source -echo "${sc_refdir}/sc_${sc_task}.tcl"
+source -echo "${sc_refdir}/rcx/sc_${sc_task}.tcl"
 utl::pop_metrics_stage

siliconcompiler/tools/openroad/scripts/sc_rdlroute.tcl

@@ -40,22 +40,22 @@ set sc_macrolibs [sc_get_asic_libraries macro]
 ###############################
 
 foreach msg [sc_cfg_tool_task_get warningoff] {
-  set or_msg [split $msg "-"]
-  if { [llength $or_msg] != 2 } {
-    utl::warn FLW 1 "$msg is not a valid message id"
-  } else {
-    set or_tool [lindex $or_msg 0]
-    set or_msg_id [expr { int([lindex $or_msg 1]) }]
-    utl::info FLW 1 "Suppressing $msg messages"
-    suppress_message $or_tool $or_msg_id
-  }
+    set or_msg [split $msg "-"]
+    if { [llength $or_msg] != 2 } {
+        utl::warn FLW 1 "$msg is not a valid message id"
+    } else {
+        set or_tool [lindex $or_msg 0]
+        set or_msg_id [expr { int([lindex $or_msg 1]) }]
+        utl::info FLW 1 "Suppressing $msg messages"
+        suppress_message $or_tool $or_msg_id
+    }
 }
 
 ###############################
 # Source helper functions
 ###############################
 
-source "$sc_refdir/sc_procs.tcl"
+source "$sc_refdir/common/procs.tcl"
 
 ###############################
 # Common Setup
@@ -69,21 +69,21 @@ read_lef $sc_techlef
 
 # Read Lefs
 foreach lib "$sc_macrolibs" {
-  foreach lef_file [sc_cfg_get library $lib output $sc_stackup lef] {
-    puts "Reading lef: ${lef_file}"
-    read_lef $lef_file
-  }
+    foreach lef_file [sc_cfg_get library $lib output $sc_stackup lef] {
+        puts "Reading lef: ${lef_file}"
+        read_lef $lef_file
+    }
 }
 
 # Read Verilog
 if { [file exists "inputs/${sc_design}.vg"] } {
-  puts "Reading netlist verilog: inputs/${sc_design}.vg"
-  read_verilog "inputs/${sc_design}.vg"
+    puts "Reading netlist verilog: inputs/${sc_design}.vg"
+    read_verilog "inputs/${sc_design}.vg"
 } else {
-  foreach netlist [sc_cfg_get input netlist verilog] {
-    puts "Reading netlist verilog: ${netlist}"
-    read_verilog $netlist
-  }
+    foreach netlist [sc_cfg_get input netlist verilog] {
+        puts "Reading netlist verilog: ${netlist}"
+        read_verilog $netlist
+    }
 }
 link_design $sc_design
 
@@ -93,10 +93,10 @@ link_design $sc_design
 
 utl::push_metrics_stage "sc__prestep__{}"
 if { [sc_cfg_tool_task_exists prescript] } {
-  foreach sc_pre_script [sc_cfg_tool_task_get prescript] {
-    puts "Sourcing pre script: ${sc_pre_script}"
-    source -echo $sc_pre_script
-  }
+    foreach sc_pre_script [sc_cfg_tool_task_get prescript] {
+        puts "Sourcing pre script: ${sc_pre_script}"
+        source -echo $sc_pre_script
+    }
 }
 utl::pop_metrics_stage
 
@@ -107,23 +107,23 @@ utl::push_metrics_stage "sc__step__{}"
 ###########################
 
 if { [sc_cfg_exists input asic floorplan] } {
-  set def [lindex [sc_cfg_get input asic floorplan] 0]
-  puts "Reading floorplan DEF: ${def}"
-  read_def -floorplan_initialize $def
+    set def [lindex [sc_cfg_get input asic floorplan] 0]
+    puts "Reading floorplan DEF: ${def}"
+    read_def -floorplan_initialize $def
 } else {
-  #NOTE: assuming a two tuple value as lower left, upper right
-  set sc_diearea [sc_cfg_get constraint outline]
+    #NOTE: assuming a two tuple value as lower left, upper right
+    set sc_diearea [sc_cfg_get constraint outline]
 
-  # Use die and core sizes
-  set sc_diesize "[lindex $sc_diearea 0] [lindex $sc_diearea 1]"
+    # Use die and core sizes
+    set sc_diesize "[lindex $sc_diearea 0] [lindex $sc_diearea 1]"
 
-  set outline [odb::Rect]
-  $outline set_xlo [ord::microns_to_dbu [lindex $sc_diesize 0]]
-  $outline set_ylo [ord::microns_to_dbu [lindex $sc_diesize 1]]
-  $outline set_xhi [ord::microns_to_dbu [lindex $sc_diesize 2]]
-  $outline set_yhi [ord::microns_to_dbu [lindex $sc_diesize 3]]
+    set outline [odb::Rect]
+    $outline set_xlo [ord::microns_to_dbu [lindex $sc_diesize 0]]
+    $outline set_ylo [ord::microns_to_dbu [lindex $sc_diesize 1]]
+    $outline set_xhi [ord::microns_to_dbu [lindex $sc_diesize 2]]
+    $outline set_yhi [ord::microns_to_dbu [lindex $sc_diesize 3]]
 
-  [ord::get_db_block] setDieArea $outline
+    [ord::get_db_block] setDieArea $outline
 }
 
 puts "Floorplan information:"
@@ -140,8 +140,8 @@ make_tracks
 # RDL Routing
 ###########################
 foreach rdl_file [sc_cfg_tool_task_get {file} rdlroute] {
-  puts "Sourcing rdlroute: ${rdl_file}"
-  source $rdl_file
+    puts "Sourcing rdlroute: ${rdl_file}"
+    source $rdl_file
 }
 
 ######################
@@ -150,28 +150,28 @@ foreach rdl_file [sc_cfg_tool_task_get {file} rdlroute] {
 
 set removed_obs 0
 foreach obstruction [[ord::get_db_block] getObstructions] {
-  odb::dbObstruction_destroy $obstruction
-  incr removed_obs
+    odb::dbObstruction_destroy $obstruction
+    incr removed_obs
 }
 utl::info FLW 1 "Deleted $removed_obs routing obstructions"
 
 if {
-  [lindex [sc_cfg_tool_task_get var fin_add_fill] 0] == "true" &&
-  [sc_cfg_exists pdk $sc_pdk aprtech openroad $sc_stackup $sc_libtype fill]
+    [lindex [sc_cfg_tool_task_get var fin_add_fill] 0] == "true" &&
+    [sc_cfg_exists pdk $sc_pdk aprtech openroad $sc_stackup $sc_libtype fill]
 } {
-  set sc_fillrules \
-    [lindex [sc_cfg_get pdk $sc_pdk aprtech openroad $sc_stackup $sc_libtype fill] 0]
-  density_fill -rules $sc_fillrules
+    set sc_fillrules \
+        [lindex [sc_cfg_get pdk $sc_pdk aprtech openroad $sc_stackup $sc_libtype fill] 0]
+    density_fill -rules $sc_fillrules
 }
 
 utl::pop_metrics_stage
 
 utl::push_metrics_stage "sc__poststep__{}"
 if { [sc_cfg_tool_task_exists postscript] } {
-  foreach sc_post_script [sc_cfg_tool_task_get postscript] {
-    puts "Sourcing post script: ${sc_post_script}"
-    source -echo $sc_post_script
-  }
+    foreach sc_post_script [sc_cfg_tool_task_get postscript] {
+        puts "Sourcing post script: ${sc_post_script}"
+        source -echo $sc_post_script
+    }
 }
 utl::pop_metrics_stage
 
@@ -180,5 +180,5 @@ utl::pop_metrics_stage
 ###############################
 
 utl::push_metrics_stage "sc__write__{}"
-source "$sc_refdir/sc_write.tcl"
+source "$sc_refdir/common/write_data.tcl"
 utl::pop_metrics_stage

siliconcompiler/tools/openroad/scripts/sc_show.tcl

@@ -0,0 +1,110 @@
+###############################
+# Reading SC Schema
+###############################
+
+source ./sc_manifest.tcl > /dev/null
+
+##############################
+# Schema Adapter
+###############################
+
+set sc_step [sc_cfg_get arg step]
+set sc_index [sc_cfg_get arg index]
+set sc_flow [sc_cfg_get option flow]
+set sc_tool [sc_cfg_get flowgraph $sc_flow $sc_step $sc_index tool]
+set sc_task [sc_cfg_get flowgraph $sc_flow $sc_step $sc_index task]
+
+set sc_refdir [sc_cfg_tool_task_get refdir]
+
+##############################
+# Setup debugging
+###############################
+
+source -echo "$sc_refdir/common/debugging.tcl"
+
+###############################
+# Setup helper functions
+###############################
+
+source "$sc_refdir/common/procs.tcl"
+
+###############################
+# Setup GUI title early
+###############################
+sc_set_gui_title
+
+###############################
+# Design information
+###############################
+
+# Design
+set sc_design [sc_top]
+set sc_optmode [sc_cfg_get option optmode]
+set sc_pdk [sc_cfg_get option pdk]
+set sc_stackup [sc_cfg_get option stackup]
+
+# APR Parameters
+set sc_targetlibs [sc_get_asic_libraries logic]
+set sc_mainlib [lindex $sc_targetlibs 0]
+set sc_delaymodel [sc_cfg_get asic delaymodel]
+
+# Hard macro libraries
+set sc_macrolibs [sc_get_asic_libraries macro]
+
+# Threads
+set_thread_count [sc_cfg_tool_task_get threads]
+
+###############################
+# Read Files
+###############################
+
+source -echo "$sc_refdir/common/read_liberty.tcl"
+
+source -echo "$sc_refdir/common/read_input_files.tcl"
+
+source -echo "$sc_refdir/common/read_timing_constraints.tcl"
+
+###############################
+# Common Setup
+###############################
+
+sc_setup_sta
+
+sc_setup_parasitics
+
+set_dont_use [sc_cfg_get library $sc_mainlib asic cells dontuse]
+
+###############################
+# Source Step Script
+###############################
+
+report_units_metric
+
+utl::push_metrics_stage "sc__prestep__{}"
+if { [sc_cfg_tool_task_exists prescript] } {
+    foreach sc_pre_script [sc_cfg_tool_task_get prescript] {
+        puts "Sourcing pre script: ${sc_pre_script}"
+        source -echo $sc_pre_script
+    }
+}
+utl::pop_metrics_stage
+
+utl::push_metrics_stage "sc__step__{}"
+
+set openroad_dont_touch {}
+if { [sc_cfg_tool_task_exists {var} dont_touch] } {
+    set openroad_dont_touch [sc_cfg_tool_task_get {var} dont_touch]
+}
+
+if { [llength $openroad_dont_touch] > 0 } {
+    # set don't touch list
+    set_dont_touch $openroad_dont_touch
+}
+
+if { $sc_task == "screenshot" } {
+    source -echo "$sc_refdir/common/screenshot.tcl"
+}
+
+if { [lindex [sc_cfg_tool_task_get {var} show_exit] 0] == "true" } {
+    exit
+}

siliconcompiler/tools/openroad/show.py

@@ -1,18 +1,20 @@
 import shutil
 import os
 
-from siliconcompiler.tools.openroad import openroad
-from siliconcompiler.tools.openroad.openroad import setup as setup_tool
-from siliconcompiler.tools.openroad.openroad import build_pex_corners
-from siliconcompiler.tools.openroad.openroad import pre_process as or_pre_process
+from siliconcompiler.tools.openroad import make_docs as or_make_docs
+from siliconcompiler.tools.openroad._apr import setup as tool_setup
+from siliconcompiler.tools.openroad._apr import set_reports
+from siliconcompiler.tools.openroad._apr import build_pex_corners, define_ord_files
 from siliconcompiler.tools._common import find_incoming_ext, input_provides, get_tool_task
+from siliconcompiler.tools.openroad._apr import \
+    define_ord_params, define_sta_params, define_sdc_params
 
 
 ####################################################################
 # Make Docs
 ####################################################################
 def make_docs(chip):
-    openroad.make_docs(chip)
+    or_make_docs(chip)
     chip.set('tool', 'openroad', 'task', 'show', 'var', 'show_filepath', '<path>')
 
 
@@ -20,22 +22,26 @@ def setup(chip):
     '''
     Show a design in openroad
     '''
+    generic_show_setup(chip, False)
 
-    # Generic tool setup.
-    setup_tool(chip)
-
-    generic_show_setup(chip, 'show', False)
 
+def generic_show_setup(chip, exit):
+    # Generic tool setup.
+    tool_setup(chip, exit=exit)
 
-def generic_show_setup(chip, task, exit):
-    tool = 'openroad'
-    design = chip.top()
     step = chip.get('arg', 'step')
     index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+    design = chip.top()
+
+    chip.set('tool', tool, 'task', task, 'script', 'sc_show.tcl',
+             step=step, index=index)
 
-    option = "-no_init -gui"
+    # Add GUI option
+    chip.add('tool', tool, 'task', task, 'option', '-gui',
+             step=step, index=index)
 
-    chip.set('tool', tool, 'task', task, 'var', 'show_exit', "true" if exit else "false",
+    chip.set('tool', tool, 'task', task, 'var', 'show_exit', exit,
              step=step, index=index, clobber=False)
     if chip.valid('tool', tool, 'task', task, 'var', 'show_filepath'):
         chip.add('tool', tool, 'task', task, 'require',
@@ -51,25 +57,24 @@ def generic_show_setup(chip, task, exit):
             chip.add('tool', tool, 'task', task, 'input', f'{design}.sdc',
                      step=step, index=index)
 
-    # Add to option string.
-    cur_options = ' '.join(chip.get('tool', tool, 'task', task, 'option', step=step, index=index))
-    new_options = f'{cur_options} {option}'
-    chip.set('tool', tool, 'task', task, 'option', new_options,
-             step=step, index=index, clobber=True)
+    # set default values for task
+    define_ord_params(chip)
+    define_sta_params(chip)
+    define_sdc_params(chip)
+
+    set_reports(chip, [])
 
 
 def pre_process(chip):
-    or_pre_process(chip)
     copy_show_files(chip)
+    define_ord_files(chip)
     build_pex_corners(chip)
 
 
 def copy_show_files(chip):
-
-    tool = 'openroad'
     step = chip.get('arg', 'step')
     index = chip.get('arg', 'index')
-    _, task = get_tool_task(chip, step, index)
+    tool, task = get_tool_task(chip, step, index)
 
     if chip.valid('tool', tool, 'task', task, 'var', 'show_filepath'):
         show_file = chip.get('tool', tool, 'task', task, 'var', 'show_filepath',

siliconcompiler/tools/openroad/{export.py → write_data.py}

@@ -1,41 +1,46 @@
-
-from siliconcompiler.tools.openroad.openroad import setup as setup_tool
-from siliconcompiler.tools.openroad.openroad import build_pex_corners
-from siliconcompiler.tools.openroad.openroad import post_process as or_post_process
-from siliconcompiler.tools.openroad.openroad import pre_process as or_pre_process
-from siliconcompiler.tools._common.asic import set_tool_task_var, get_libraries
-from siliconcompiler.tools.openroad.openroad import _set_reports, set_pnr_inputs, set_pnr_outputs
 from siliconcompiler.tools._common import get_tool_task
+from siliconcompiler.tools._common.asic import get_libraries, set_tool_task_var
+from siliconcompiler.tools.openroad._apr import setup as apr_setup
+from siliconcompiler.tools.openroad._apr import set_reports, set_pnr_inputs, set_pnr_outputs
+from siliconcompiler.tools.openroad._apr import \
+    define_ord_params, define_sta_params, define_sdc_params, \
+    define_pex_params, define_psm_params
+from siliconcompiler.tools.openroad._apr import build_pex_corners, define_ord_files
+from siliconcompiler.tools.openroad._apr import extract_metrics
 
 
 def setup(chip):
     '''
-    Generate abstract views (LEF), timing libraries (liberty files),
-    circuit descriptions (CDL), and parasitic annotation files (SPEF)
+    Write output files
     '''
 
-    # Generic tool setup.
-    setup_tool(chip)
+    # Generic apr tool setup.
+    apr_setup(chip)
 
-    set_pnr_inputs(chip)
-    set_pnr_outputs(chip)
-
-    tool = 'openroad'
+    # Task setup
     design = chip.top()
     step = chip.get('arg', 'step')
     index = chip.get('arg', 'index')
-    _, task = get_tool_task(chip, step, index)
+    tool, task = get_tool_task(chip, step, index)
 
-    # Set thread count to 1 while issue related to write_timing_model segfaulting
-    # when multiple threads are on is resolved.
-    chip.set('tool', tool, 'task', task, 'threads', 1,
-             step=step, index=index, clobber=True)
+    chip.set('tool', tool, 'task', task, 'script', 'apr/sc_write_data.tcl',
+             step=step, index=index)
 
-    stackup = chip.get('option', 'stackup')
-    pdk = chip.get('option', 'pdk')
+    # Setup task IO
+    set_pnr_inputs(chip)
+    set_pnr_outputs(chip)
 
+    # set default values for openroad
+    define_ord_params(chip)
+    define_sta_params(chip)
+    define_sdc_params(chip)
+    define_pex_params(chip)
+    define_psm_params(chip)
+
+    pdkname = chip.get('option', 'pdk')
     targetlibs = get_libraries(chip, 'logic')
     macrolibs = get_libraries(chip, 'macro')
+    stackup = chip.get('option', 'stackup')
 
     # Determine if exporting the cdl
     set_tool_task_var(chip, param_key='write_cdl',
@@ -65,7 +70,7 @@ def setup(chip):
         for corner in chip.get('tool', tool, 'task', task, 'var', 'pex_corners',
                                step=step, index=index):
             chip.add('tool', tool, 'task', task, 'require',
-                     ",".join(['pdk', pdk, 'pexmodel', 'openroad-openrcx', stackup, corner]),
+                     ",".join(['pdk', pdkname, 'pexmodel', 'openroad-openrcx', stackup, corner]),
                      step=step, index=index)
 
         # Add outputs SPEF in the format {design}.{pexcorner}.spef
@@ -102,7 +107,7 @@ def setup(chip):
             chip.add('tool', tool, 'task', task, 'output', design + '.' + corner + '.sdf',
                      step=step, index=index)
 
-    _set_reports(chip, [
+    set_reports(chip, [
         'setup',
         'hold',
         'unconstrained',
@@ -123,9 +128,9 @@ def setup(chip):
 
 
 def pre_process(chip):
-    or_pre_process(chip)
+    define_ord_files(chip)
     build_pex_corners(chip)
 
 
 def post_process(chip):
-    or_post_process(chip)
+    extract_metrics(chip)

siliconcompiler/tools/opensta/__init__.py

@@ -9,16 +9,16 @@ Installation: https://github.com/The-OpenROAD-Project/OpenSTA (also installed wi
 '''
 
 import os
-from siliconcompiler.tools.openroad.openroad import get_library_timing_keypaths
+from siliconcompiler.tools.openroad._apr import get_library_timing_keypaths
 from siliconcompiler.tools._common import get_tool_task
 from siliconcompiler.tools._common.asic import get_libraries
-from siliconcompiler.targets import asap7_demo
 
 
 ####################################################################
 # Make Docs
 ####################################################################
 def make_docs(chip):
+    from siliconcompiler.targets import asap7_demo
     chip.use(asap7_demo)
 
 

siliconcompiler/tools/opensta/check_library.py

@@ -0,0 +1,27 @@
+from siliconcompiler.tools.opensta import setup as tool_setup
+from siliconcompiler.tools.opensta import runtime_options as tool_runtime_options
+from siliconcompiler.tools._common import get_tool_task
+
+
+def setup(chip):
+    '''
+    Check setup information about the timing libraries.
+    '''
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+
+    tool_setup(chip)
+
+    chip.set('tool', tool, 'task', task, 'script', 'sc_check_library.tcl',
+             step=step, index=index, clobber=False)
+
+    chip.set('tool', tool, 'task', task, 'threads', 1,
+             step=step, index=index)
+
+
+################################
+# Runtime options
+################################
+def runtime_options(chip):
+    return tool_runtime_options(chip)