siliconcompiler 0.28.9__py3-none-any.whl → 0.29.1__py3-none-any.whl

siliconcompiler/tools/opensta/scripts/sc_check_library.tcl

@@ -0,0 +1,255 @@
+###############################
+# Reading SC Schema
+###############################
+
+source ./sc_manifest.tcl > /dev/null
+
+##############################
+# Schema Adapter
+###############################
+
+set sc_tool opensta
+set sc_step [sc_cfg_get arg step]
+set sc_index [sc_cfg_get arg index]
+set sc_flow [sc_cfg_get option flow]
+set sc_task [sc_cfg_get flowgraph $sc_flow $sc_step $sc_index task]
+
+set sc_refdir [sc_cfg_tool_task_get refdir]
+
+# Design
+set sc_design [sc_top]
+
+# APR Parameters
+set sc_targetlibs [sc_get_asic_libraries logic]
+set sc_delaymodel [sc_cfg_get asic delaymodel]
+set sc_scenarios [dict keys [sc_cfg_get constraint timing]]
+
+###############################
+# Optional
+###############################
+
+# MACROS
+set sc_macrolibs [sc_get_asic_libraries macro]
+
+###############################
+# Read Files
+###############################
+
+# Read Liberty
+puts "Defining timing corners: $sc_scenarios"
+define_corners {*}$sc_scenarios
+foreach lib "$sc_targetlibs $sc_macrolibs" {
+    #Liberty
+    foreach corner $sc_scenarios {
+        foreach libcorner [sc_cfg_get constraint timing $corner libcorner] {
+            if { [sc_cfg_exists library $lib output $libcorner $sc_delaymodel] } {
+                foreach lib_file [sc_cfg_get library $lib output $libcorner $sc_delaymodel] {
+                    puts "Reading liberty file for ${corner} ($libcorner): ${lib_file}"
+                    read_liberty -corner $corner $lib_file
+                }
+                break
+            }
+        }
+    }
+}
+
+proc assert_glob { str } {
+    if { [string first "*" $str] != -1 } {
+        puts "\[ERROR] Regex detected: $str"
+    }
+}
+
+# Check cells
+# check for globbing and report list if globs are detected
+# check each cell
+foreach lib $sc_targetlibs {
+    dict for {cell_type cells} [sc_cfg_get library $lib asic cells] {
+        if { [llength $cells] == 0 } {
+            continue
+        }
+
+        puts "Checking: $lib / asic / cells / $cell_type"
+
+        foreach cell $cells {
+            puts "  $cell:"
+
+            if { $cell_type != "dontuse" } {
+                assert_glob $cell
+            }
+            set libcells [get_lib_cells $cell]
+            foreach libcell $libcells {
+                puts "    [get_full_name $libcell]"
+            }
+        }
+    }
+}
+
+# Check yosys setup
+# yosys_driver_cell
+foreach lib $sc_targetlibs {
+    puts "Checking $lib yosys_driver_cell"
+    assert_glob [sc_cfg_get library $lib option var yosys_driver_cell]
+    if { [get_lib_cells [sc_cfg_get library $lib option var yosys_driver_cell]] == 0 } {
+        puts "\[ERROR] missing"
+    }
+}
+# yosys_buffer_cell
+foreach lib $sc_targetlibs {
+    puts "Checking $lib yosys_buffer_cell"
+    assert_glob [sc_cfg_get library $lib option var yosys_buffer_cell]
+    if { [get_lib_cells [sc_cfg_get library $lib option var yosys_buffer_cell]] == 0 } {
+        puts "\[ERROR] missing"
+    }
+}
+# yosys_buffer_input
+foreach lib $sc_targetlibs {
+    puts "Checking $lib yosys_buffer_input"
+    assert_glob [sc_cfg_get library $lib option var yosys_buffer_input]
+    set cellname [sc_cfg_get library $lib option var yosys_buffer_cell]
+    set pins [get_lib_pins $cellname/[sc_cfg_get library $lib option var yosys_buffer_input]]
+    if { [llength $pins] != [llength [sta::corners]] } {
+        puts "\[ERROR] mismatch"
+    }
+    foreach pin $pins {
+        if { [get_property $pin direction] != "input" } {
+            puts "\[ERROR] [get_full_name $pin] incorrect direction"
+        }
+    }
+}
+# yosys_buffer_output
+foreach lib $sc_targetlibs {
+    puts "Checking $lib yosys_buffer_output"
+    assert_glob [sc_cfg_get library $lib option var yosys_buffer_output]
+    set cellname [sc_cfg_get library $lib option var yosys_buffer_cell]
+    set pins [get_lib_pins $cellname/[sc_cfg_get library $lib option var yosys_buffer_output]]
+    if { [llength $pins] != [llength [sta::corners]] } {
+        puts "\[ERROR] mismatch"
+    }
+    foreach pin $pins {
+        if { [get_property $pin direction] != "output" } {
+            puts "\[ERROR] [get_full_name $pin] incorrect direction"
+        }
+    }
+}
+# yosys_tiehigh_cell
+foreach lib $sc_targetlibs {
+    puts "Checking $lib yosys_tiehigh_cell"
+    assert_glob [sc_cfg_get library $lib option var yosys_tiehigh_cell]
+    if { [get_lib_cells [sc_cfg_get library $lib option var yosys_tiehigh_cell]] == 0 } {
+        puts "\[ERROR] missing"
+    }
+}
+# yosys_tiehigh_port
+foreach lib $sc_targetlibs {
+    puts "Checking $lib yosys_tiehigh_port"
+    assert_glob [sc_cfg_get library $lib option var yosys_tiehigh_port]
+    set cellname [sc_cfg_get library $lib option var yosys_tiehigh_cell]
+    set pins [get_lib_pins $cellname/[sc_cfg_get library $lib option var yosys_tiehigh_port]]
+    if { [llength $pins] != [llength [sta::corners]] } {
+        puts "\[ERROR] mismatch"
+    }
+    foreach pin $pins {
+        if { [get_property $pin direction] != "output" } {
+            puts "\[ERROR] [get_full_name $pin] incorrect direction"
+        }
+    }
+}
+# yosys_tielow_cell
+foreach lib $sc_targetlibs {
+    puts "Checking $lib yosys_tielow_cell"
+    assert_glob [sc_cfg_get library $lib option var yosys_tielow_cell]
+    if { [get_lib_cells [sc_cfg_get library $lib option var yosys_tielow_cell]] == 0 } {
+        puts "\[ERROR] missing"
+    }
+}
+# yosys_tielow_port
+foreach lib $sc_targetlibs {
+    puts "Checking $lib yosys_tielow_port"
+    assert_glob [sc_cfg_get library $lib option var yosys_tielow_port]
+    set cellname [sc_cfg_get library $lib option var yosys_tielow_cell]
+    set pins [get_lib_pins $cellname/[sc_cfg_get library $lib option var yosys_tielow_port]]
+    if { [llength $pins] != [llength [sta::corners]] } {
+        puts "\[ERROR] mismatch"
+    }
+    foreach pin $pins {
+        if { [get_property $pin direction] != "output" } {
+            puts "\[ERROR] [get_full_name $pin] incorrect direction"
+        }
+    }
+}
+# yosys_abc_constraint_load
+foreach lib $sc_targetlibs {
+    set cap 0.0
+    puts "Checking $lib yosys_abc_constraint_load"
+    set cellname [sc_cfg_get library $lib option var yosys_buffer_cell]
+    set pins [get_lib_pins $cellname/[sc_cfg_get library $lib option var yosys_buffer_input]]
+    foreach pin $pins {
+        set cap [expr { max($cap, [get_property $pin capacitance]) }]
+    }
+    set lib_cap [sc_cfg_get library $lib option var yosys_abc_constraint_load]
+    set cap [expr { 4 * $cap }]
+    set cap "[format "%.3f" $cap][sta::unit_scaled_suffix capacitance]"
+
+    if { $lib_cap != $cap } {
+        puts "\[ERROR] mismatch, should be $cap, not $lib_cap"
+    }
+}
+
+# yosys_abc_clock_multiplier
+foreach lib $sc_targetlibs {
+    puts "Checking $lib yosys_abc_clock_multiplier"
+    set ps_convert [expr { round(1.0 / [sta::time_sta_ui 1e-12]) }]
+    set convert [sc_cfg_get library $lib option var yosys_abc_clock_multiplier]
+    if { $convert != $ps_convert } {
+        puts "\[ERROR] incorrect multiplier: should be $ps_convert, not $convert"
+    }
+}
+
+# Check openroad setup
+# openroad_tiehigh_cell
+foreach lib $sc_targetlibs {
+    puts "Checking $lib openroad_tiehigh_cell"
+    assert_glob [sc_cfg_get library $lib option var openroad_tiehigh_cell]
+    if { [get_lib_cells [sc_cfg_get library $lib option var openroad_tiehigh_cell]] == 0 } {
+        puts "\[ERROR] missing"
+    }
+}
+# openroad_tiehigh_port
+foreach lib $sc_targetlibs {
+    puts "Checking $lib openroad_tiehigh_port"
+    assert_glob [sc_cfg_get library $lib option var openroad_tiehigh_port]
+    set cellname [sc_cfg_get library $lib option var openroad_tiehigh_cell]
+    set pins [get_lib_pins $cellname/[sc_cfg_get library $lib option var openroad_tiehigh_port]]
+    if { [llength $pins] != [llength [sta::corners]] } {
+        puts "\[ERROR] mismatch"
+    }
+    foreach pin $pins {
+        if { [get_property $pin direction] != "output" } {
+            puts "\[ERROR] [get_full_name $pin] incorrect direction"
+        }
+    }
+}
+
+# openroad_tielow_cell
+foreach lib $sc_targetlibs {
+    puts "Checking $lib openroad_tielow_cell"
+    assert_glob [sc_cfg_get library $lib option var openroad_tielow_cell]
+    if { [get_lib_cells [sc_cfg_get library $lib option var openroad_tielow_cell]] == 0 } {
+        puts "\[ERROR] missing"
+    }
+}
+# openroad_tielow_port
+foreach lib $sc_targetlibs {
+    puts "Checking $lib openroad_tielow_port"
+    assert_glob [sc_cfg_get library $lib option var openroad_tielow_port]
+    set cellname [sc_cfg_get library $lib option var openroad_tielow_cell]
+    set pins [get_lib_pins $cellname/[sc_cfg_get library $lib option var openroad_tielow_port]]
+    if { [llength $pins] != [llength [sta::corners]] } {
+        puts "\[ERROR] mismatch"
+    }
+    foreach pin $pins {
+        if { [get_property $pin direction] != "output" } {
+            puts "\[ERROR] [get_full_name $pin] incorrect direction"
+        }
+    }
+}

siliconcompiler/tools/opensta/scripts/sc_timing.tcl

@@ -128,7 +128,7 @@ source "$sc_refdir/sc_procs.tcl"
 
 set opensta_top_n_paths [lindex [sc_cfg_tool_task_get var top_n_paths] 0]
 
-set fields "{capacitance slew input_pins nets fanout}"
+set fields "{capacitance slew input_pins hierarcial_pins net fanout}"
 set PREFIX "SC_METRIC:"
 
 puts "$PREFIX timeunit"

siliconcompiler/tools/sv2v/sv2v.py

@@ -14,13 +14,12 @@ Sources: https://github.com/zachjs/sv2v
 Installation: https://github.com/zachjs/sv2v
 '''
 
-from siliconcompiler.tools.sv2v import convert
-
 
 ####################################################################
 # Make Docs
 ####################################################################
 def make_docs(chip):
+    from siliconcompiler.tools.sv2v import convert
     convert.setup(chip)
     return chip
 

siliconcompiler/tools/verilator/verilator.py

@@ -32,13 +32,13 @@ from siliconcompiler.tools._common import (
     get_tool_task,
     input_provides
 )
-from siliconcompiler.targets import freepdk45_demo
 
 
 ####################################################################
 # Make Docs
 ####################################################################
 def make_docs(chip):
+    from siliconcompiler.targets import freepdk45_demo
     chip.use(freepdk45_demo)
 
 
@@ -71,10 +71,8 @@ def setup(chip):
     chip.set('tool', tool, 'task', task, 'file', 'config',
              'Verilator configuration file',
              field='help')
-    if chip.get('tool', tool, 'task', task, 'file', 'config', step=step, index=index):
-        chip.add('tool', tool, 'task', task, 'require',
-                 ','.join(['tool', tool, 'task', task, 'file', 'config']),
-                 step=step, index=index)
+    add_require_input(chip, 'tool', tool, 'task', task, 'file', 'config')
+    add_require_input(chip, 'option', 'file', 'verilator_config')
 
     chip.set('tool', tool, 'task', task, 'var', 'enable_assert',
              'true/false, when true assertions are enabled in Verilator.',
@@ -132,8 +130,9 @@ def runtime_options(chip):
         cmdlist.append(libext_option)
 
     # Verilator docs recommend this file comes first in CLI arguments
-    for value in chip.find_files('tool', tool, 'task', task, 'file', 'config',
-                                 step=step, index=index):
+    for value in get_input_files(chip, 'tool', tool, 'task', task, 'file', 'config'):
+        cmdlist.append(value)
+    for value in get_input_files(chip, 'option', 'file', 'verilator_config'):
         cmdlist.append(value)
 
     for param, value in frontend_opts['param']:

siliconcompiler/tools/vivado/vivado.py

@@ -10,10 +10,10 @@ import os
 import re
 from siliconcompiler import sc_open
 from siliconcompiler.tools._common import record_metric
-from siliconcompiler.targets import fpgaflow_demo
 
 
 def make_docs(chip):
+    from siliconcompiler.targets import fpgaflow_demo
     chip.set('fpga', 'partname', 'ice40up5k-sg48')
     chip.use(fpgaflow_demo)
 

siliconcompiler/tools/yosys/__init__.py

@@ -0,0 +1,149 @@
+'''
+Yosys is a framework for RTL synthesis that takes synthesizable
+Verilog-2005 design and converts it to BLIF, EDIF, BTOR, SMT,
+Verilog netlist etc. The tool supports logical synthesis and
+tech mapping to ASIC standard cell libraries, FPGA architectures.
+In addition it has built in formal methods for property and
+equivalence checking.
+
+Documentation: https://yosyshq.readthedocs.io/projects/yosys/en/latest/
+
+Sources: https://github.com/YosysHQ/yosys
+
+Installation: https://github.com/YosysHQ/yosys
+'''
+
+import re
+import json
+from siliconcompiler import sc_open
+from siliconcompiler.tools._common import get_tool_task, record_metric
+
+
+######################################################################
+# Make Docs
+######################################################################
+def make_docs(chip):
+    from siliconcompiler.targets import asap7_demo
+    chip.use(asap7_demo)
+
+
+################################
+# Setup Tool (pre executable)
+################################
+def setup(chip):
+    ''' Tool specific function to run before step execution
+    '''
+
+    # If the 'lock' bit is set, don't reconfigure.
+    tool = 'yosys'
+    refdir = 'tools/' + tool
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    _, task = get_tool_task(chip, step, index)
+
+    # Standard Setup
+    chip.set('tool', tool, 'exe', 'yosys')
+    chip.set('tool', tool, 'vswitch', '--version')
+    chip.set('tool', tool, 'version', '>=0.48', clobber=False)
+    chip.set('tool', tool, 'format', 'tcl', clobber=False)
+
+    # Task Setup
+    # common to all
+    option = []
+    if chip.get('option', 'breakpoint', step=step, index=index):
+        option.append('-C')
+    option.append('-c')
+    chip.set('tool', tool, 'task', task, 'option', option, step=step, index=index, clobber=False)
+    chip.set('tool', tool, 'task', task, 'refdir', refdir, step=step, index=index,
+             package='siliconcompiler', clobber=False)
+    chip.set('tool', tool, 'task', task, 'regex', 'warnings', "Warning:",
+             step=step, index=index, clobber=False)
+    chip.set('tool', tool, 'task', task, 'regex', 'errors', "^ERROR",
+             step=step, index=index, clobber=False)
+
+
+################################
+# Version Check
+################################
+def parse_version(stdout):
+    # Yosys 0.9+3672 (git sha1 014c7e26, gcc 7.5.0-3ubuntu1~18.04 -fPIC -Os)
+    return stdout.split()[1]
+
+
+def normalize_version(version):
+    # Replace '+', which represents a "local version label", with '-', which is
+    # an "implicit post release number".
+    return version.replace('+', '-')
+
+
+def syn_setup(chip):
+    ''' Helper method for configs specific to synthesis tasks.
+    '''
+
+    # Generic tool setup.
+    setup(chip)
+
+    tool = 'yosys'
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    _, task = get_tool_task(chip, step, index)
+    design = chip.top()
+
+    # Set yosys script path.
+    chip.set('tool', tool, 'task', task, 'script', 'sc_syn.tcl',
+             step=step, index=index, clobber=False)
+
+    # Input/output requirements.
+    chip.set('tool', tool, 'task', task, 'input', design + '.v', step=step, index=index)
+    chip.set('tool', tool, 'task', task, 'output', design + '.vg', step=step, index=index)
+    chip.add('tool', tool, 'task', task, 'output', design + '.netlist.json', step=step, index=index)
+
+
+##################################################
+def syn_post_process(chip):
+    ''' Tool specific function to run after step execution
+    '''
+
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+
+    with sc_open("reports/stat.json") as f:
+        metrics = json.load(f)
+        if "design" in metrics:
+            metrics = metrics["design"]
+
+        if "area" in metrics:
+            record_metric(chip, step, index, 'cellarea',
+                          float(metrics["area"]),
+                          "reports/stat.json",
+                          source_unit='um^2')
+        if "num_cells" in metrics:
+            record_metric(chip, step, index, 'cells',
+                          metrics["num_cells"],
+                          "reports/stat.json")
+        if "num_wire_bits" in metrics:
+            record_metric(chip, step, index, 'nets',
+                          metrics["num_wire_bits"],
+                          "reports/stat.json")
+        if "num_port_bits" in metrics:
+            record_metric(chip, step, index, 'pins',
+                          metrics["num_port_bits"],
+                          "reports/stat.json")
+
+    registers = None
+    with sc_open(f"{step}.log") as f:
+        for line in f:
+            line_registers = re.findall(r"^\s*mapped ([0-9]+) \$_DFF.*", line)
+            if line_registers:
+                if registers is None:
+                    registers = 0
+                registers += int(line_registers[0])
+    if registers is not None:
+        record_metric(chip, step, index, 'registers', registers, f"{step}.log")
+
+
+##################################################
+if __name__ == "__main__":
+
+    chip = make_docs()
+    chip.write_manifest("yosys.json")

siliconcompiler/tools/yosys/lec.py

@@ -1,9 +1,9 @@
 import re
 
-from siliconcompiler.tools.yosys.yosys import setup as setup_tool
-from siliconcompiler.tools.yosys.syn_asic import setup_asic
+from siliconcompiler.tools.yosys import setup as setup_tool
+from siliconcompiler.tools.yosys.syn_asic import setup_asic, prepare_synthesis_libraries
 from siliconcompiler import sc_open
-from siliconcompiler.tools._common import get_tool_task, record_metric
+from siliconcompiler.tools._common import get_tool_task, record_metric, input_provides
 
 
 def setup(chip):
@@ -28,12 +28,25 @@ def setup(chip):
              step=step, index=index, clobber=False)
 
     # Input/output requirements.
-    if not chip.valid('input', 'netlist', 'verilog') or \
-       not chip.get('input', 'netlist', 'verilog', step=step, index=index):
-        chip.set('tool', tool, 'task', task, 'input', design + '.vg', step=step, index=index)
-    # if not chip.get('input', 'rtl', 'verilog'):
-        # TODO: Not sure this logic makes sense? Seems like reverse of tcl
-        # chip.set('tool', tool, 'task', task, 'input', design + '.v', step=step, index=index)
+    if f"{design}.lec.vg" in input_provides(chip, step, index):
+        chip.set('tool', tool, 'task', task, 'input', design + '.lec.vg',
+                 step=step, index=index)
+    elif f"{design}.vg" in input_provides(chip, step, index):
+        chip.set('tool', tool, 'task', task, 'input', design + '.vg',
+                 step=step, index=index)
+    else:
+        chip.add('tool', tool, 'task', task, 'require', 'input,netlist,verilog',
+                 step=step, index=index)
+
+    chip.set('tool', tool, 'task', task, 'var', 'induction_steps', '10',
+             step=step, index=index, clobber=False)
+    chip.set('tool', tool, 'task', task, 'var', 'induction_steps',
+             'Number of induction steps for yosys equivalence checking',
+             field='help')
+
+
+def pre_process(chip):
+    prepare_synthesis_libraries(chip)
 
 
 ##################################################