siliconcompiler 0.28.9__py3-none-any.whl → 0.29.1__py3-none-any.whl

siliconcompiler/tools/yosys/sc_lec.tcl

@@ -1,5 +1,5 @@
 # Script adapted from
-# https://github.com/The-OpenROAD-Project/OpenLane/blob/d052a918f4a46ddbae0ad09812f6cd0b8eb4a1e5/scripts/logic_equiv_check.tcl
+# https://github.com/The-OpenROAD-Project/OpenLane/blob/2264b1240bacca90f8dfd74b8f5d62b7d618038e/scripts/yosys/logic_equiv_check.tcl
 
 source ./sc_manifest.tcl
 set sc_tool yosys
@@ -10,71 +10,116 @@ set sc_step [sc_cfg_get arg step]
 set sc_index [sc_cfg_get arg index]
 set sc_flow [sc_cfg_get option flow]
 set sc_task [sc_cfg_get flowgraph $sc_flow $sc_step $sc_index task]
-set sc_refdir [sc_cfg_tool_task_get refdir]
 
 set sc_design [sc_top]
-set sc_targetlibs [sc_get_asic_libraries logic]
-
-# TODO: properly handle complexity here
-set lib [lindex $sc_targetlibs 0]
-set sc_delaymodel [sc_cfg_get asic delaymodel]
-set sc_scenarios [dict keys [sc_cfg_get constraint timing]]
-set sc_libcorner [sc_cfg_get constraint timing [lindex $sc_scenarios 0] libcorner]
-set sc_liberty [sc_cfg_get library $lib output $sc_libcorner $sc_delaymodel]
-
-if { [sc_cfg_tool_task_exists "variable" induction_steps] } {
-    set sc_induction_steps \
-        [lindex [sc_cfg_tool_task_get "variable" induction_steps] 0]
+
+set sc_libraries [sc_cfg_tool_task_get {file} synthesis_libraries]
+if { [dict exists $sc_cfg tool $sc_tool task $sc_task {file} synthesis_libraries_macros] } {
+    set sc_macro_libraries [sc_cfg_tool_task_get {file} synthesis_libraries_macros]
 } else {
-    # Yosys default
-    set sc_induction_steps 4
+    set sc_macro_libraries []
+}
+set sc_blackboxes []
+foreach lib [sc_cfg_get asic macrolib] {
+    if { [sc_cfg_exists library $lib output blackbox verilog] } {
+        foreach lib_f [sc_cfg_get library $lib output blackbox verilog] {
+            lappend sc_blackboxes $lib_f
+        }
+    }
 }
 
-# Gold netlist
-yosys read_liberty -ignore_miss_func $sc_liberty
-if { [file exists "inputs/$sc_design.v"] } {
-    set source "inputs/$sc_design.v"
-} else {
-    set source [lindex [sc_cfg_get input rtl verilog] 0]
+set sc_induction_steps [lindex [sc_cfg_tool_task_get {var} induction_steps] 0]
+
+proc prepare_libraries { } {
+    global sc_libraries
+    global sc_macro_libraries
+    global sc_blackboxes
+
+    foreach lib_file "$sc_libraries $sc_macro_libraries" {
+        yosys read_liberty -ignore_miss_func -ignore_miss_dir $lib_file
+    }
+    foreach bb_file $sc_blackboxes {
+        puts "Reading blackbox model file: $bb_file"
+        yosys read_verilog -sv $bb_file
+    }
+
+    set sc_logiclibs [sc_cfg_get asic logiclib]
+    set sc_macrolibs [sc_cfg_get asic macrolib]
+
+    foreach lib "$sc_logiclibs $sc_macrolibs" {
+        foreach phy_type "filler decap antenna tap" {
+            if { [sc_cfg_exists library $lib asic cells $phy_type] } {
+                foreach cells [sc_cfg_get library $lib asic cells $phy_type] {
+                    puts "Generating $cells for $lib"
+                    yosys hierarchy -generate $cells
+                }
+            }
+        }
+    }
 }
-yosys read_verilog $source
 
-yosys proc
-yosys rmports
-yosys splitnets -ports
-yosys hierarchy -auto-top
-yosys flatten
+proc prepare_design { type v_files } {
+    global sc_cfg
+    global sc_design
 
-yosys setattr -set keep 1
-yosys stat
-yosys rename -top gold
-yosys design -stash gold
+    puts "Preparing \"$type\" design"
+    foreach f_file $v_files {
+        puts "Reading verilog file: $f_file"
+        yosys read_verilog -sv $f_file
+    }
 
-# Gate netlist
-yosys read_liberty -ignore_miss_func $sc_liberty
-if { [sc_cfg_exists input netlist verilog] } {
-    set netlist [lindex [sc_cfg_get input netlist verilog] 0]
-} else {
-    set netlist "inputs/$sc_design.vg"
+    ########################################################
+    # Override top level parameters
+    ########################################################
+
+    yosys chparam -list
+    if { [dict exists $sc_cfg option param] } {
+        dict for {key value} [sc_cfg_get option param] {
+            if { ![string is integer $value] } {
+                set value [concat \"$value\"]
+            }
+            yosys chparam -set $key $value $sc_design
+        }
+    }
+
+    prepare_libraries
+
+    yosys proc
+    yosys rmports
+    yosys splitnets -ports
+    yosys hierarchy -top $sc_design
+    yosys async2sync
+    yosys flatten
+
+    yosys setattr -set keep 1
+    yosys stat
+    yosys rename -top $type
+    yosys design -stash $type
 }
-yosys read_verilog $netlist
 
-yosys proc
-yosys rmports
-yosys splitnets -ports
-yosys hierarchy -auto-top
-yosys flatten
+# Gold netlist
+if { [file exists "inputs/${sc_design}.v"] } {
+    set gold_source "inputs/${sc_design}.v"
+} else {
+    set gold_source [sc_cfg_get input rtl verilog]
+}
+prepare_design gold $gold_source
 
-yosys setattr -set keep 1
-yosys stat
-yosys rename -top gate
-yosys design -stash gate
+# Gate netlist
+if { [file exists "inputs/${sc_design}.lec.vg"] } {
+    set gate_source "inputs/${sc_design}.lec.vg"
+} elseif { [file exists "inputs/${sc_design}.vg"] } {
+    set gate_source "inputs/${sc_design}.vg"
+} else {
+    set gate_source [sc_cfg_get input netlist verilog]
+}
+prepare_design gate $gate_source
 
 yosys design -copy-from gold -as gold gold
 yosys design -copy-from gate -as gate gate
 
 # Rebuild the database due to -stash
-yosys read_liberty -ignore_miss_func $sc_liberty
+prepare_libraries
 
 yosys equiv_make gold gate equiv
 

siliconcompiler/tools/yosys/sc_syn.tcl

@@ -75,3 +75,4 @@ source "$sc_refdir/${sc_task}.tcl"
 # Write Netlist
 ########################################################
 yosys write_verilog -noexpr -nohex -nodec "outputs/${sc_design}.vg"
+yosys write_json "outputs/${sc_design}.netlist.json"

siliconcompiler/tools/yosys/screenshot.py

@@ -1,12 +1,12 @@
-from siliconcompiler.tools.yosys.yosys import setup as tool_setup
+from siliconcompiler.tools.yosys import setup as tool_setup
 import os
 import siliconcompiler.tools.yosys.prepareLib as prepareLib
 from siliconcompiler.tools._common.asic import get_libraries
 from siliconcompiler.tools._common import get_tool_task
-from siliconcompiler.targets import asap7_demo
 
 
 def make_docs(chip):
+    from siliconcompiler.targets import asap7_demo
     chip.use(asap7_demo)
 
 

siliconcompiler/tools/yosys/syn_asic.py

@@ -1,16 +1,18 @@
 
-from siliconcompiler.tools.yosys.yosys import syn_setup, syn_post_process
+from siliconcompiler.tools.yosys import syn_setup, syn_post_process
 import os
+import json
 import re
-import siliconcompiler.tools.yosys.prepareLib as prepareLib
+from siliconcompiler.tools.yosys.prepareLib import processLibertyFile
 from siliconcompiler import sc_open
 from siliconcompiler import utils
-from siliconcompiler.tools._common.asic import set_tool_task_var, get_libraries, get_mainlib
+from siliconcompiler.tools._common.asic import set_tool_task_var, get_libraries, get_mainlib, \
+    CellArea
 from siliconcompiler.tools._common import get_tool_task
-from siliconcompiler.targets import asap7_demo
 
 
 def make_docs(chip):
+    from siliconcompiler.targets import asap7_demo
     chip.use(asap7_demo)
 
 
@@ -108,6 +110,13 @@ def setup_asic(chip):
         chip.add('tool', tool, 'task', task, 'require',
                  ",".join(['library', mainlib, 'option', 'file', 'yosys_addermap']),
                  step=step, index=index)
+    library_has_tbufmap = \
+        chip.valid('library', mainlib, 'option', 'file', 'yosys_tbufmap') and \
+        chip.get('library', mainlib, 'option', 'file', 'yosys_tbufmap')
+    if library_has_tbufmap:
+        chip.add('tool', tool, 'task', task, 'require',
+                 ",".join(['library', mainlib, 'option', 'file', 'yosys_tbufmap']),
+                 step=step, index=index)
 
     for var0, var1 in [('memory_libmap', 'memory_techmap')]:
         key0 = ['tool', tool, 'tak', task, 'file', var0]
@@ -151,9 +160,6 @@ def setup_asic(chip):
              'true/false, techmap adders in Yosys', field='help')
     chip.set('tool', tool, 'task', task, 'var', 'synthesis_corner',
              'Timing corner to use for synthesis', field='help')
-    chip.set('tool', tool, 'task', task, 'file', 'dff_liberty',
-             'Liberty file to use for flip-flop mapping, if not specified the first in the '
-             'logiclib is used', field='help')
     chip.set('tool', tool, 'task', task, 'var', 'abc_constraint_driver',
              'Buffer that drives the abc techmapping, defaults to first buffer specified',
              field='help')
@@ -167,8 +173,6 @@ def setup_asic(chip):
              'values between 0 and 1', field='help')
     chip.set('tool', tool, 'task', task, 'file', 'techmap',
              'File to use for techmapping in Yosys', field='help')
-    chip.set('tool', tool, 'task', task, 'file', 'dff_liberty_file',
-             'File to use for the DFF mapping stage of Yosys', field='help')
     chip.set('tool', tool, 'task', task, 'var', 'add_buffers',
              'true/false, flag to indicate whether to add buffers or not.', field='help')
 
@@ -181,6 +185,14 @@ def setup_asic(chip):
              'Instance limit for the number of cells in a module to preserve.',
              field='help')
 
+    set_tool_task_var(chip, 'map_clockgates',
+                      default_value=False,
+                      schelp='Map clockgates during synthesis.')
+
+    set_tool_task_var(chip, 'min_clockgate_fanout',
+                      default_value=8,
+                      schelp='Minimum clockgate fanout.')
+
     chip.set('tool', tool, 'task', task, 'var', 'strategy',
              'ABC synthesis strategy. Allowed values are DELAY0-4, AREA0-3, or if the strategy '
              'starts with a + it is assumed to be actual commands for ABC.',
@@ -209,22 +221,13 @@ def prepare_synthesis_libraries(chip):
     corners = chip.get('tool', tool, 'task', task, 'var', 'synthesis_corner',
                        step=step, index=index)
 
-    # mark dff libery file with dont use
-    dff_liberty_file = chip.find_files('tool', tool, 'task', task, 'file', 'dff_liberty',
-                                       step=step, index=index)[0]
-    yosys_dff_file = chip.get('tool', tool, 'task', task, 'file', 'dff_liberty_file',
-                              step=step, index=index)[0]
-
-    with open(yosys_dff_file, 'w') as f:
-        f.write(prepareLib.processLibertyFile(
-            dff_liberty_file,
-            logger=None if chip.get('option', 'quiet', step=step, index=index) else chip.logger
-        ))
+    logger = None if chip.get('option', 'quiet', step=step, index=index) else chip.logger
 
     # Clear in case of rerun
     for libtype in ('synthesis_libraries', 'synthesis_libraries_macros'):
         chip.set('tool', tool, 'task', task, 'file', libtype, [],
                  step=step, index=index)
+        chip.set('tool', tool, 'task', task, 'file', libtype, False, field='copy')
 
     # Generate synthesis_libraries and synthesis_macro_libraries for Yosys use
 
@@ -237,9 +240,11 @@ def prepare_synthesis_libraries(chip):
             return chip.find_files(*keypath, step=step, index=index)
         return []
 
+    lib_file_map = {}
     for libtype in ('logic', 'macro'):
         for lib in get_libraries(chip, libtype):
             lib_content = {}
+            lib_map = {}
             # Mark dont use
             for lib_file in get_synthesis_libraries(lib):
                 # Ensure a unique name is used for library
@@ -255,15 +260,11 @@ def prepare_synthesis_libraries(chip):
                     lib_file_name = f'{lib_file_name_base}_{unique_ident}'
                     unique_ident += 1
 
-                if lib_file == dff_liberty_file:
-                    with sc_open(yosys_dff_file) as f:
-                        lib_content[lib_file_name] = f.read()
-                    continue
-
-                lib_content[lib_file_name] = prepareLib.processLibertyFile(
-                        lib_file,
-                        logger=None if chip.get('option', 'quiet',
-                                                step=step, index=index) else chip.logger)
+                lib_content[lib_file_name] = processLibertyFile(
+                    lib_file,
+                    logger=logger
+                )
+                lib_map[lib_file_name] = lib_file
 
             if not lib_content:
                 continue
@@ -278,6 +279,7 @@ def prepare_synthesis_libraries(chip):
                     'inputs',
                     f'sc_{libtype}_{lib}_{file}.lib'
                 )
+                lib_file_map[lib_map[file]] = output_file
 
                 with open(output_file, 'w') as f:
                     f.write(content)
@@ -376,42 +378,6 @@ def _get_synthesis_library_key(chip, lib, corners):
     return ('library', lib, 'output', corners[0], delaymodel)
 
 
-def get_dff_liberty_file(chip):
-    tool = 'yosys'
-    step = chip.get('arg', 'step')
-    index = chip.get('arg', 'index')
-    _, task = get_tool_task(chip, step, index)
-
-    dff_liberty = None
-    if chip.valid('tool', tool, 'task', task, 'file', 'dff_liberty'):
-        dff_liberty = chip.find_files('tool', tool, 'task', task, 'file', 'dff_liberty',
-                                      step=step, index=index)
-        if dff_liberty:
-            return dff_liberty[0]
-
-    mainlib = get_mainlib(chip)
-    if chip.valid('library', mainlib, 'option', 'file', 'yosys_dff_liberty'):
-        dff_liberty = chip.find_files('library', mainlib, 'option', 'file', 'yosys_dff_liberty')
-        if dff_liberty:
-            return dff_liberty[0]
-
-    corners = get_synthesis_corner(chip)
-    if corners is None:
-        return None
-
-    # if dff liberty file is not set, use the first liberty file defined
-    for lib in get_libraries(chip, 'logic'):
-        if not chip.valid(*_get_synthesis_library_key(chip, lib, corners)):
-            continue
-
-        lib_files = chip.find_files(*_get_synthesis_library_key(chip, lib, corners),
-                                    step=step, index=index)
-        if len(lib_files) > 0:
-            return lib_files[0]
-
-    return None
-
-
 def get_abc_period(chip):
 
     tool = 'yosys'
@@ -543,17 +509,10 @@ def pre_process(chip):
             chip.add('tool', tool, 'task', task, 'file', 'techmap', techmap, step=step, index=index)
 
     # Constants needed by yosys, do not allow overriding of values so force clobbering
-    chip.set('tool', tool, 'task', task, 'file', 'dff_liberty_file',
-             f"{chip.getworkdir(step=step, index=index)}/inputs/sc_dff_library.lib",
-             step=step, index=index, clobber=True)
     chip.set('tool', tool, 'task', task, 'file', 'abc_constraint_file',
              f"{chip.getworkdir(step=step, index=index)}/inputs/sc_abc.constraints",
              step=step, index=index, clobber=True)
-
-    dff_liberty_file = get_dff_liberty_file(chip)
-    if dff_liberty_file:
-        chip.set('tool', tool, 'task', task, 'file', 'dff_liberty', dff_liberty_file,
-                 step=step, index=index, clobber=False)
+    chip.set('tool', tool, 'task', task, 'file', 'abc_constraint_file', False, field='copy')
 
     abc_clock_period = get_abc_period(chip)
     if abc_clock_period:
@@ -562,8 +521,80 @@ def pre_process(chip):
 
     prepare_synthesis_libraries(chip)
     create_abc_synthesis_constraints(chip)
-    return
 
 
 def post_process(chip):
     syn_post_process(chip)
+    _generate_cell_area_report(chip)
+
+
+def _generate_cell_area_report(chip):
+    design = "gcd"
+    if not os.path.exists('reports/stat.json'):
+        return
+    if not os.path.exists(f'outputs/{design}.netlist.json'):
+        return
+
+    with sc_open('reports/stat.json') as fd:
+        stat = json.load(fd)
+
+    with sc_open(f'outputs/{design}.netlist.json') as fd:
+        netlist = json.load(fd)
+    modules = []
+    for module in stat["modules"].keys():
+        if module[0] == "\\":
+            modules.append(module[1:])
+
+    cellarea_report = CellArea()
+
+    def get_area_count(module):
+        if f"\\{module}" not in stat["modules"]:
+            return 0.0, 0
+        info = stat["modules"][f"\\{module}"]
+
+        count = info["num_cells"]
+        area = 0.0
+        if "area" in info:
+            area = info["area"]
+
+        for cell, inst_count in info["num_cells_by_type"].items():
+            # print(module, cell, inst_count)
+
+            cell_area, cell_count = get_area_count(cell)
+
+            count += cell_count * inst_count
+            if cell_count > 0:
+                count -= inst_count
+            area += cell_area * inst_count
+
+        return area, count
+
+    def handle_heir(level_info, prefix):
+        cells = list(level_info["cells"])
+
+        for cell in cells:
+            cell_type = level_info["cells"][cell]["type"]
+            if cell_type in modules:
+                area, count = get_area_count(cell_type)
+                cellarea_report.addCell(
+                    name=f"{prefix}{cell}",
+                    module=cell_type,
+                    cellcount=count,
+                    cellarea=area)
+                handle_heir(netlist["modules"][cell_type], f"{prefix}{cell}.")
+
+    count = stat["design"]["num_cells"]
+    area = 0.0
+    if "area" in stat["design"]:
+        area = stat["design"]["area"]
+    cellarea_report.addCell(
+        name=design,
+        module=design,
+        cellarea=area,
+        cellcount=count
+    )
+
+    handle_heir(netlist["modules"][design], "")
+
+    if cellarea_report.size() > 0:
+        cellarea_report.writeReport("reports/hierarchical_cell_area.json")

siliconcompiler/tools/yosys/syn_asic.tcl

@@ -92,8 +92,6 @@ if { [sc_cfg_tool_task_exists {file} synthesis_libraries_macros] } {
 }
 set sc_mainlib [lindex $sc_logiclibs 0]
 
-set sc_dff_library \
-    [lindex [sc_cfg_tool_task_get {file} dff_liberty_file] 0]
 set sc_abc_constraints \
     [lindex [sc_cfg_tool_task_get {file} abc_constraint_file] 0]
 
@@ -120,7 +118,7 @@ if { [sc_cfg_tool_task_exists file memory_techmap] } {
 # Schema helper functions
 #########################
 
-proc has_tie_cell { type } {
+proc sc_has_tie_cell { type } {
     upvar sc_cfg sc_cfg
     upvar sc_mainlib sc_mainlib
     upvar sc_tool sc_tool
@@ -131,7 +129,7 @@ proc has_tie_cell { type } {
     }]
 }
 
-proc get_tie_cell { type } {
+proc sc_get_tie_cell { type } {
     upvar sc_cfg sc_cfg
     upvar sc_mainlib sc_mainlib
     upvar sc_tool sc_tool
@@ -209,6 +207,18 @@ yosys hierarchy -top $sc_design
 # Mark modules to keep from getting removed in flattening
 preserve_modules
 
+# Handle tristate buffers
+set sc_tbuf "false"
+if {
+    [sc_cfg_exists library $sc_mainlib option file yosys_tbufmap] &&
+    [llength [sc_cfg_get library $sc_mainlib option file yosys_tbufmap]] != 0
+} {
+    set sc_tbuf "true"
+
+    yosys tribuf
+    yosys stat
+}
+
 set flatten_design [expr {
     [lindex [sc_cfg_tool_task_get var flatten] 0]
     == "true"
@@ -253,6 +263,10 @@ yosys synth {*}$synth_args -top $sc_design -run fine:check
 # Some place and route tools cannot handle these in the output Verilog,
 # so remove them here.
 yosys delete {*/t:$print}
+yosys chformal -remove
+
+# Recheck hierarchy to remove all unused modules
+yosys hierarchy -top $sc_design
 
 yosys opt -purge
 
@@ -260,6 +274,15 @@ yosys opt -purge
 # Technology Mapping
 ########################################################
 
+# Handle tristate buffers
+if { $sc_tbuf == "true" } {
+    set sc_tbuf_techmap \
+        [lindex [sc_cfg_get library $sc_mainlib option file yosys_tbufmap] 0]
+    # Map tristate buffers
+    yosys techmap -map $sc_tbuf_techmap
+    post_techmap -fast
+}
+
 if { [sc_cfg_tool_task_get var map_adders] == "true" } {
     set sc_adder_techmap \
         [lindex [sc_cfg_get library $sc_mainlib option {file} yosys_addermap] 0]
@@ -284,14 +307,36 @@ if { [sc_cfg_tool_task_get var autoname] == "true" } {
     yosys rename -wire
 }
 
+if { [lindex [sc_cfg_tool_task_get var map_clockgates] 0] == "true" } {
+    set clockgate_dont_use []
+    foreach lib "$sc_logiclibs $sc_macrolibs" {
+        foreach cell [sc_cfg_get library $lib asic cells dontuse] {
+            lappend clockgate_dont_use -dont_use $cell
+        }
+    }
+    set clockgate_liberty []
+    foreach lib_file "$sc_libraries $sc_macro_libraries" {
+        lappend clockgate_dont_use "-liberty" $lib_file
+    }
+
+    yosys clockgate \
+        {*}$clockgate_dont_use \
+        {*}$clockgate_liberty \
+        -min_net_size [lindex [sc_cfg_tool_task_get var min_clockgate_fanout] 0]
+}
+
 set dfflibmap_dont_use []
 foreach lib "$sc_logiclibs $sc_macrolibs" {
     foreach cell [sc_cfg_get library $lib asic cells dontuse] {
         lappend dfflibmap_dont_use -dont_use $cell
     }
 }
+set dfflibmap_liberty []
+foreach lib_file "$sc_libraries $sc_macro_libraries" {
+    lappend dfflibmap_liberty "-liberty" $lib_file
+}
 
-yosys dfflibmap {*}$dfflibmap_dont_use -liberty $sc_dff_library
+yosys dfflibmap {*}$dfflibmap_dont_use {*}$dfflibmap_liberty
 
 # perform final techmap and opt in case previous techmaps introduced constructs that need
 # techmapping
@@ -337,8 +382,10 @@ foreach lib_file $sc_libraries {
 }
 set abc_dont_use []
 foreach lib "$sc_logiclibs $sc_macrolibs" {
-    foreach cell [sc_cfg_get library $lib asic cells dontuse] {
-        lappend abc_dont_use -dont_use $cell
+    foreach group "dontuse hold clkbuf clkgate clklogic" {
+        foreach cell [sc_cfg_get library $lib asic cells $group] {
+            lappend abc_dont_use -dont_use $cell
+        }
     }
 }
 
@@ -356,11 +403,11 @@ yosys splitnets
 yosys clean -purge
 
 set yosys_hilomap_args []
-if { [has_tie_cell low] } {
-    lappend yosys_hilomap_args -locell {*}[get_tie_cell low]
+if { [sc_has_tie_cell low] } {
+    lappend yosys_hilomap_args -locell {*}[sc_get_tie_cell low]
 }
-if { [has_tie_cell high] } {
-    lappend yosys_hilomap_args -hicell {*}[get_tie_cell high]
+if { [sc_has_tie_cell high] } {
+    lappend yosys_hilomap_args -hicell {*}[sc_get_tie_cell high]
 }
 if { [llength $yosys_hilomap_args] != 0 } {
     yosys hilomap -singleton {*}$yosys_hilomap_args
@@ -376,7 +423,6 @@ if {
 yosys clean -purge
 
 set stat_libs []
-lappend stat_libs "-liberty" $sc_dff_library
 foreach lib_file "$sc_libraries $sc_macro_libraries" {
     lappend stat_libs "-liberty" $lib_file
 }

siliconcompiler/tools/yosys/syn_fpga.py

@@ -1,14 +1,14 @@
-from siliconcompiler.tools.yosys.yosys import syn_setup, syn_post_process
+from siliconcompiler.tools.yosys import syn_setup, syn_post_process
 import json
 from siliconcompiler import sc_open
 from siliconcompiler.tools._common import get_tool_task, record_metric
-from siliconcompiler.targets import fpgaflow_demo
 
 
 ######################################################################
 # Make Docs
 ######################################################################
 def make_docs(chip):
+    from siliconcompiler.targets import fpgaflow_demo
     chip.set('fpga', 'partname', 'ice40up5k-sg48')
     chip.use(fpgaflow_demo)
 
@@ -93,7 +93,6 @@ def setup_fpga(chip):
                  ",".join(['fpga', part_name, 'file', 'yosys_memory_techmap']),
                  step=step, index=index)
 
-    chip.add('tool', tool, 'task', task, 'output', design + '.netlist.json', step=step, index=index)
     chip.add('tool', tool, 'task', task, 'output', design + '.blif', step=step, index=index)