siliconcompiler 0.28.9__py3-none-any.whl → 0.29.1__py3-none-any.whl
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- siliconcompiler/_metadata.py +1 -1
- siliconcompiler/apps/__init__.py +26 -0
- siliconcompiler/apps/sc_remote.py +15 -14
- siliconcompiler/apps/sc_show.py +5 -5
- siliconcompiler/apps/utils/replay.py +194 -0
- siliconcompiler/checklists/__init__.py +12 -0
- siliconcompiler/core.py +89 -22
- siliconcompiler/flows/__init__.py +34 -0
- siliconcompiler/flows/_common.py +11 -13
- siliconcompiler/flows/asicflow.py +83 -42
- siliconcompiler/flows/showflow.py +1 -1
- siliconcompiler/libs/__init__.py +5 -0
- siliconcompiler/optimizer/__init__.py +199 -0
- siliconcompiler/optimizer/vizier.py +259 -0
- siliconcompiler/pdks/__init__.py +5 -0
- siliconcompiler/remote/__init__.py +11 -0
- siliconcompiler/remote/client.py +753 -815
- siliconcompiler/report/report.py +2 -0
- siliconcompiler/report/summary_table.py +1 -1
- siliconcompiler/scheduler/__init__.py +118 -58
- siliconcompiler/scheduler/send_messages.py +1 -1
- siliconcompiler/schema/schema_cfg.py +16 -4
- siliconcompiler/schema/schema_obj.py +29 -10
- siliconcompiler/schema/utils.py +2 -0
- siliconcompiler/sphinx_ext/__init__.py +85 -0
- siliconcompiler/sphinx_ext/dynamicgen.py +19 -34
- siliconcompiler/sphinx_ext/schemagen.py +3 -2
- siliconcompiler/targets/__init__.py +26 -0
- siliconcompiler/targets/gf180_demo.py +3 -3
- siliconcompiler/templates/replay/replay.py.j2 +62 -0
- siliconcompiler/templates/replay/requirements.txt +7 -0
- siliconcompiler/templates/replay/setup.sh +130 -0
- siliconcompiler/tools/__init__.py +60 -0
- siliconcompiler/tools/_common/__init__.py +15 -1
- siliconcompiler/tools/_common/asic.py +17 -9
- siliconcompiler/tools/builtin/concatenate.py +1 -1
- siliconcompiler/tools/ghdl/ghdl.py +1 -2
- siliconcompiler/tools/klayout/convert_drc_db.py +1 -1
- siliconcompiler/tools/klayout/drc.py +1 -1
- siliconcompiler/tools/klayout/export.py +8 -1
- siliconcompiler/tools/klayout/klayout.py +2 -2
- siliconcompiler/tools/klayout/klayout_convert_drc_db.py +2 -2
- siliconcompiler/tools/klayout/klayout_export.py +7 -5
- siliconcompiler/tools/klayout/klayout_operations.py +4 -3
- siliconcompiler/tools/klayout/klayout_show.py +3 -2
- siliconcompiler/tools/klayout/klayout_utils.py +1 -1
- siliconcompiler/tools/klayout/operations.py +8 -0
- siliconcompiler/tools/klayout/screenshot.py +6 -1
- siliconcompiler/tools/klayout/show.py +8 -1
- siliconcompiler/tools/magic/magic.py +1 -1
- siliconcompiler/tools/openroad/__init__.py +103 -0
- siliconcompiler/tools/openroad/{openroad.py → _apr.py} +415 -423
- siliconcompiler/tools/openroad/antenna_repair.py +78 -0
- siliconcompiler/tools/openroad/clock_tree_synthesis.py +64 -0
- siliconcompiler/tools/openroad/detailed_placement.py +59 -0
- siliconcompiler/tools/openroad/detailed_route.py +62 -0
- siliconcompiler/tools/openroad/endcap_tapcell_insertion.py +52 -0
- siliconcompiler/tools/openroad/fillercell_insertion.py +58 -0
- siliconcompiler/tools/openroad/{dfm.py → fillmetal_insertion.py} +35 -19
- siliconcompiler/tools/openroad/global_placement.py +58 -0
- siliconcompiler/tools/openroad/global_route.py +63 -0
- siliconcompiler/tools/openroad/init_floorplan.py +103 -0
- siliconcompiler/tools/openroad/macro_placement.py +65 -0
- siliconcompiler/tools/openroad/metrics.py +23 -8
- siliconcompiler/tools/openroad/pin_placement.py +56 -0
- siliconcompiler/tools/openroad/power_grid.py +65 -0
- siliconcompiler/tools/openroad/rcx_bench.py +7 -4
- siliconcompiler/tools/openroad/rcx_extract.py +2 -1
- siliconcompiler/tools/openroad/rdlroute.py +4 -4
- siliconcompiler/tools/openroad/repair_design.py +59 -0
- siliconcompiler/tools/openroad/repair_timing.py +63 -0
- siliconcompiler/tools/openroad/screenshot.py +9 -20
- siliconcompiler/tools/openroad/scripts/apr/postamble.tcl +44 -0
- siliconcompiler/tools/openroad/scripts/apr/preamble.tcl +95 -0
- siliconcompiler/tools/openroad/scripts/apr/sc_antenna_repair.tcl +51 -0
- siliconcompiler/tools/openroad/scripts/apr/sc_clock_tree_synthesis.tcl +66 -0
- siliconcompiler/tools/openroad/scripts/apr/sc_detailed_placement.tcl +41 -0
- siliconcompiler/tools/openroad/scripts/apr/sc_detailed_route.tcl +71 -0
- siliconcompiler/tools/openroad/scripts/apr/sc_endcap_tapcell_insertion.tcl +55 -0
- siliconcompiler/tools/openroad/scripts/apr/sc_fillercell_insertion.tcl +27 -0
- siliconcompiler/tools/openroad/scripts/apr/sc_fillmetal_insertion.tcl +36 -0
- siliconcompiler/tools/openroad/scripts/apr/sc_global_placement.tcl +26 -0
- siliconcompiler/tools/openroad/scripts/apr/sc_global_route.tcl +61 -0
- siliconcompiler/tools/openroad/scripts/apr/sc_init_floorplan.tcl +333 -0
- siliconcompiler/tools/openroad/scripts/apr/sc_macro_placement.tcl +123 -0
- siliconcompiler/tools/openroad/scripts/apr/sc_metrics.tcl +22 -0
- siliconcompiler/tools/openroad/scripts/apr/sc_pin_placement.tcl +41 -0
- siliconcompiler/tools/openroad/scripts/apr/sc_power_grid.tcl +60 -0
- siliconcompiler/tools/openroad/scripts/apr/sc_repair_design.tcl +68 -0
- siliconcompiler/tools/openroad/scripts/apr/sc_repair_timing.tcl +83 -0
- siliconcompiler/tools/openroad/scripts/apr/sc_write_data.tcl +125 -0
- siliconcompiler/tools/openroad/scripts/common/debugging.tcl +28 -0
- siliconcompiler/tools/openroad/scripts/common/procs.tcl +727 -0
- siliconcompiler/tools/openroad/scripts/common/read_input_files.tcl +59 -0
- siliconcompiler/tools/openroad/scripts/common/read_liberty.tcl +20 -0
- siliconcompiler/tools/openroad/scripts/common/read_timing_constraints.tcl +16 -0
- siliconcompiler/tools/openroad/scripts/common/reports.tcl +180 -0
- siliconcompiler/tools/openroad/scripts/common/screenshot.tcl +18 -0
- siliconcompiler/tools/openroad/scripts/common/write_images.tcl +395 -0
- siliconcompiler/tools/openroad/scripts/{sc_rcx_bench.tcl → rcx/sc_rcx_bench.tcl} +5 -5
- siliconcompiler/tools/openroad/scripts/{sc_rcx_extract.tcl → rcx/sc_rcx_extract.tcl} +0 -0
- siliconcompiler/tools/openroad/scripts/sc_rcx.tcl +5 -16
- siliconcompiler/tools/openroad/scripts/sc_rdlroute.tcl +51 -51
- siliconcompiler/tools/openroad/scripts/sc_show.tcl +110 -0
- siliconcompiler/tools/openroad/show.py +28 -23
- siliconcompiler/tools/openroad/{export.py → write_data.py} +31 -26
- siliconcompiler/tools/opensta/__init__.py +2 -2
- siliconcompiler/tools/opensta/check_library.py +27 -0
- siliconcompiler/tools/opensta/scripts/sc_check_library.tcl +255 -0
- siliconcompiler/tools/opensta/scripts/sc_timing.tcl +1 -1
- siliconcompiler/tools/sv2v/sv2v.py +1 -2
- siliconcompiler/tools/verilator/verilator.py +6 -7
- siliconcompiler/tools/vivado/vivado.py +1 -1
- siliconcompiler/tools/yosys/__init__.py +149 -0
- siliconcompiler/tools/yosys/lec.py +22 -9
- siliconcompiler/tools/yosys/sc_lec.tcl +94 -49
- siliconcompiler/tools/yosys/sc_syn.tcl +1 -0
- siliconcompiler/tools/yosys/screenshot.py +2 -2
- siliconcompiler/tools/yosys/syn_asic.py +105 -74
- siliconcompiler/tools/yosys/syn_asic.tcl +58 -12
- siliconcompiler/tools/yosys/syn_fpga.py +2 -3
- siliconcompiler/tools/yosys/syn_fpga.tcl +26 -19
- siliconcompiler/toolscripts/_tools.json +5 -5
- siliconcompiler/utils/__init__.py +7 -3
- {siliconcompiler-0.28.9.dist-info → siliconcompiler-0.29.1.dist-info}/METADATA +22 -17
- {siliconcompiler-0.28.9.dist-info → siliconcompiler-0.29.1.dist-info}/RECORD +131 -114
- {siliconcompiler-0.28.9.dist-info → siliconcompiler-0.29.1.dist-info}/WHEEL +1 -1
- {siliconcompiler-0.28.9.dist-info → siliconcompiler-0.29.1.dist-info}/entry_points.txt +13 -0
- siliconcompiler/libs/asap7sc7p5t.py +0 -8
- siliconcompiler/libs/gf180mcu.py +0 -8
- siliconcompiler/libs/interposer.py +0 -8
- siliconcompiler/libs/nangate45.py +0 -8
- siliconcompiler/libs/sg13g2_stdcell.py +0 -8
- siliconcompiler/libs/sky130hd.py +0 -8
- siliconcompiler/libs/sky130io.py +0 -8
- siliconcompiler/pdks/asap7.py +0 -8
- siliconcompiler/pdks/freepdk45.py +0 -8
- siliconcompiler/pdks/gf180.py +0 -8
- siliconcompiler/pdks/ihp130.py +0 -8
- siliconcompiler/pdks/interposer.py +0 -8
- siliconcompiler/pdks/skywater130.py +0 -8
- siliconcompiler/tools/openroad/cts.py +0 -45
- siliconcompiler/tools/openroad/floorplan.py +0 -75
- siliconcompiler/tools/openroad/physyn.py +0 -27
- siliconcompiler/tools/openroad/place.py +0 -41
- siliconcompiler/tools/openroad/route.py +0 -45
- siliconcompiler/tools/openroad/scripts/__init__.py +0 -0
- siliconcompiler/tools/openroad/scripts/sc_apr.tcl +0 -514
- siliconcompiler/tools/openroad/scripts/sc_cts.tcl +0 -68
- siliconcompiler/tools/openroad/scripts/sc_dfm.tcl +0 -22
- siliconcompiler/tools/openroad/scripts/sc_export.tcl +0 -100
- siliconcompiler/tools/openroad/scripts/sc_floorplan.tcl +0 -456
- siliconcompiler/tools/openroad/scripts/sc_metrics.tcl +0 -1
- siliconcompiler/tools/openroad/scripts/sc_physyn.tcl +0 -6
- siliconcompiler/tools/openroad/scripts/sc_place.tcl +0 -84
- siliconcompiler/tools/openroad/scripts/sc_procs.tcl +0 -494
- siliconcompiler/tools/openroad/scripts/sc_report.tcl +0 -189
- siliconcompiler/tools/openroad/scripts/sc_route.tcl +0 -143
- siliconcompiler/tools/openroad/scripts/sc_screenshot.tcl +0 -18
- siliconcompiler/tools/openroad/scripts/sc_write_images.tcl +0 -393
- siliconcompiler/tools/yosys/yosys.py +0 -148
- /siliconcompiler/tools/openroad/scripts/{sc_write.tcl → common/write_data.tcl} +0 -0
- {siliconcompiler-0.28.9.dist-info → siliconcompiler-0.29.1.dist-info}/LICENSE +0 -0
- {siliconcompiler-0.28.9.dist-info → siliconcompiler-0.29.1.dist-info}/top_level.txt +0 -0
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yosys proc
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yosys flatten
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# Note there are two possibilities for how macro mapping might be done:
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# using the extract command (to pattern match user RTL against
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# the techmap) or using the techmap command. The latter is better
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# for mapping simple multipliers; the former is better (for now)
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# for mapping more complex DSP blocks (MAC, pipelined blocks, etc).
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# and is also more easily extensible to arbitrary hard macros.
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# otherwise yosys can transform its internal model into something
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if { [sc_cfg_exists fpga $sc_partname file yosys_extractlib] } {
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set sc_syn_extractlibs \
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[sc_cfg_get fpga $sc_partname file yosys_extractlib]
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foreach extractlib $sc_syn_extractlibs {
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#into other primitives
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# the techmap) or using the techmap command. The latter is better
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########################################################
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Name: siliconcompiler
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Version: 0.
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Version: 0.29.1
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Summary: A compiler framework that automates translation from source code to silicon.
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Author-email: Andreas Olofsson <andreas.d.olofsson@gmail.com>
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License: Apache License 2.0
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Requires-Dist: Pillow==11.1.0; python_version >= "3.9"
|
|
40
|
+
Requires-Dist: GitPython==3.1.44
|
|
41
|
+
Requires-Dist: lambdapdk>=0.1.44
|
|
42
42
|
Requires-Dist: PyGithub==2.5.0
|
|
43
43
|
Requires-Dist: urllib3>=1.26.0
|
|
44
44
|
Requires-Dist: fasteners==0.19
|
|
45
|
-
Requires-Dist: fastjsonschema==2.
|
|
45
|
+
Requires-Dist: fastjsonschema==2.21.1
|
|
46
46
|
Requires-Dist: docker==7.1.0
|
|
47
47
|
Requires-Dist: importlib_metadata; python_version < "3.10"
|
|
48
48
|
Requires-Dist: sc-surelog==1.84.1
|
|
49
|
-
Requires-Dist: orjson==3.10.
|
|
50
|
-
Requires-Dist: streamlit==1.40.1;
|
|
49
|
+
Requires-Dist: orjson==3.10.13
|
|
50
|
+
Requires-Dist: streamlit==1.40.1; python_version <= "3.8"
|
|
51
|
+
Requires-Dist: streamlit==1.41.1; python_version >= "3.9" and python_full_version != "3.9.7"
|
|
51
52
|
Requires-Dist: streamlit_agraph==0.0.45; python_full_version != "3.9.7"
|
|
52
53
|
Requires-Dist: streamlit-antd-components==0.3.2; python_full_version != "3.9.7"
|
|
53
54
|
Requires-Dist: streamlit_javascript==0.1.5; python_full_version != "3.9.7"
|
|
54
55
|
Requires-Dist: streamlit-autorefresh==1.0.1; python_full_version != "3.9.7"
|
|
55
56
|
Provides-Extra: test
|
|
56
|
-
Requires-Dist: pytest==8.3.
|
|
57
|
+
Requires-Dist: pytest==8.3.4; extra == "test"
|
|
57
58
|
Requires-Dist: pytest-xdist==3.6.1; extra == "test"
|
|
58
59
|
Requires-Dist: pytest-timeout==2.3.1; extra == "test"
|
|
59
|
-
Requires-Dist: pytest-asyncio==0.24.0; extra == "test"
|
|
60
|
+
Requires-Dist: pytest-asyncio==0.24.0; python_version <= "3.8" and extra == "test"
|
|
61
|
+
Requires-Dist: pytest-asyncio==0.25.1; python_version >= "3.9" and extra == "test"
|
|
60
62
|
Requires-Dist: pytest-cov==5.0.0; python_version <= "3.8" and extra == "test"
|
|
61
63
|
Requires-Dist: pytest-cov==6.0.0; python_version >= "3.9" and extra == "test"
|
|
62
64
|
Requires-Dist: responses==0.25.3; extra == "test"
|
|
63
65
|
Requires-Dist: PyVirtualDisplay==3.0; extra == "test"
|
|
64
|
-
|
|
65
|
-
Requires-Dist:
|
|
66
|
-
Requires-Dist:
|
|
66
|
+
Provides-Extra: lint
|
|
67
|
+
Requires-Dist: flake8==7.1.1; extra == "lint"
|
|
68
|
+
Requires-Dist: tclint==0.5.0; extra == "lint"
|
|
69
|
+
Requires-Dist: codespell==2.3.0; extra == "lint"
|
|
67
70
|
Provides-Extra: docs
|
|
68
71
|
Requires-Dist: Sphinx==8.1.3; extra == "docs"
|
|
69
72
|
Requires-Dist: pip-licenses==5.0.0; extra == "docs"
|
|
70
|
-
Requires-Dist: pydata-sphinx-theme==0.16.
|
|
73
|
+
Requires-Dist: pydata-sphinx-theme==0.16.1; extra == "docs"
|
|
71
74
|
Requires-Dist: sc-leflib>=0.2.0; extra == "docs"
|
|
72
75
|
Provides-Extra: profile
|
|
73
76
|
Requires-Dist: gprof2dot==2024.6.6; extra == "profile"
|
|
74
77
|
Provides-Extra: examples
|
|
75
78
|
Requires-Dist: migen==0.9.2; extra == "examples"
|
|
76
|
-
Requires-Dist: lambdalib==0.3.
|
|
79
|
+
Requires-Dist: lambdalib==0.3.2; extra == "examples"
|
|
80
|
+
Provides-Extra: optimizer
|
|
81
|
+
Requires-Dist: google-vizier[jax]==0.1.20; python_version >= "3.10" and extra == "optimizer"
|
|
77
82
|
|
|
78
83
|

|
|
79
84
|
|