siliconcompiler 0.28.9__py3-none-any.whl → 0.29.1__py3-none-any.whl

This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
Files changed (164) hide show
  1. siliconcompiler/_metadata.py +1 -1
  2. siliconcompiler/apps/__init__.py +26 -0
  3. siliconcompiler/apps/sc_remote.py +15 -14
  4. siliconcompiler/apps/sc_show.py +5 -5
  5. siliconcompiler/apps/utils/replay.py +194 -0
  6. siliconcompiler/checklists/__init__.py +12 -0
  7. siliconcompiler/core.py +89 -22
  8. siliconcompiler/flows/__init__.py +34 -0
  9. siliconcompiler/flows/_common.py +11 -13
  10. siliconcompiler/flows/asicflow.py +83 -42
  11. siliconcompiler/flows/showflow.py +1 -1
  12. siliconcompiler/libs/__init__.py +5 -0
  13. siliconcompiler/optimizer/__init__.py +199 -0
  14. siliconcompiler/optimizer/vizier.py +259 -0
  15. siliconcompiler/pdks/__init__.py +5 -0
  16. siliconcompiler/remote/__init__.py +11 -0
  17. siliconcompiler/remote/client.py +753 -815
  18. siliconcompiler/report/report.py +2 -0
  19. siliconcompiler/report/summary_table.py +1 -1
  20. siliconcompiler/scheduler/__init__.py +118 -58
  21. siliconcompiler/scheduler/send_messages.py +1 -1
  22. siliconcompiler/schema/schema_cfg.py +16 -4
  23. siliconcompiler/schema/schema_obj.py +29 -10
  24. siliconcompiler/schema/utils.py +2 -0
  25. siliconcompiler/sphinx_ext/__init__.py +85 -0
  26. siliconcompiler/sphinx_ext/dynamicgen.py +19 -34
  27. siliconcompiler/sphinx_ext/schemagen.py +3 -2
  28. siliconcompiler/targets/__init__.py +26 -0
  29. siliconcompiler/targets/gf180_demo.py +3 -3
  30. siliconcompiler/templates/replay/replay.py.j2 +62 -0
  31. siliconcompiler/templates/replay/requirements.txt +7 -0
  32. siliconcompiler/templates/replay/setup.sh +130 -0
  33. siliconcompiler/tools/__init__.py +60 -0
  34. siliconcompiler/tools/_common/__init__.py +15 -1
  35. siliconcompiler/tools/_common/asic.py +17 -9
  36. siliconcompiler/tools/builtin/concatenate.py +1 -1
  37. siliconcompiler/tools/ghdl/ghdl.py +1 -2
  38. siliconcompiler/tools/klayout/convert_drc_db.py +1 -1
  39. siliconcompiler/tools/klayout/drc.py +1 -1
  40. siliconcompiler/tools/klayout/export.py +8 -1
  41. siliconcompiler/tools/klayout/klayout.py +2 -2
  42. siliconcompiler/tools/klayout/klayout_convert_drc_db.py +2 -2
  43. siliconcompiler/tools/klayout/klayout_export.py +7 -5
  44. siliconcompiler/tools/klayout/klayout_operations.py +4 -3
  45. siliconcompiler/tools/klayout/klayout_show.py +3 -2
  46. siliconcompiler/tools/klayout/klayout_utils.py +1 -1
  47. siliconcompiler/tools/klayout/operations.py +8 -0
  48. siliconcompiler/tools/klayout/screenshot.py +6 -1
  49. siliconcompiler/tools/klayout/show.py +8 -1
  50. siliconcompiler/tools/magic/magic.py +1 -1
  51. siliconcompiler/tools/openroad/__init__.py +103 -0
  52. siliconcompiler/tools/openroad/{openroad.py → _apr.py} +415 -423
  53. siliconcompiler/tools/openroad/antenna_repair.py +78 -0
  54. siliconcompiler/tools/openroad/clock_tree_synthesis.py +64 -0
  55. siliconcompiler/tools/openroad/detailed_placement.py +59 -0
  56. siliconcompiler/tools/openroad/detailed_route.py +62 -0
  57. siliconcompiler/tools/openroad/endcap_tapcell_insertion.py +52 -0
  58. siliconcompiler/tools/openroad/fillercell_insertion.py +58 -0
  59. siliconcompiler/tools/openroad/{dfm.py → fillmetal_insertion.py} +35 -19
  60. siliconcompiler/tools/openroad/global_placement.py +58 -0
  61. siliconcompiler/tools/openroad/global_route.py +63 -0
  62. siliconcompiler/tools/openroad/init_floorplan.py +103 -0
  63. siliconcompiler/tools/openroad/macro_placement.py +65 -0
  64. siliconcompiler/tools/openroad/metrics.py +23 -8
  65. siliconcompiler/tools/openroad/pin_placement.py +56 -0
  66. siliconcompiler/tools/openroad/power_grid.py +65 -0
  67. siliconcompiler/tools/openroad/rcx_bench.py +7 -4
  68. siliconcompiler/tools/openroad/rcx_extract.py +2 -1
  69. siliconcompiler/tools/openroad/rdlroute.py +4 -4
  70. siliconcompiler/tools/openroad/repair_design.py +59 -0
  71. siliconcompiler/tools/openroad/repair_timing.py +63 -0
  72. siliconcompiler/tools/openroad/screenshot.py +9 -20
  73. siliconcompiler/tools/openroad/scripts/apr/postamble.tcl +44 -0
  74. siliconcompiler/tools/openroad/scripts/apr/preamble.tcl +95 -0
  75. siliconcompiler/tools/openroad/scripts/apr/sc_antenna_repair.tcl +51 -0
  76. siliconcompiler/tools/openroad/scripts/apr/sc_clock_tree_synthesis.tcl +66 -0
  77. siliconcompiler/tools/openroad/scripts/apr/sc_detailed_placement.tcl +41 -0
  78. siliconcompiler/tools/openroad/scripts/apr/sc_detailed_route.tcl +71 -0
  79. siliconcompiler/tools/openroad/scripts/apr/sc_endcap_tapcell_insertion.tcl +55 -0
  80. siliconcompiler/tools/openroad/scripts/apr/sc_fillercell_insertion.tcl +27 -0
  81. siliconcompiler/tools/openroad/scripts/apr/sc_fillmetal_insertion.tcl +36 -0
  82. siliconcompiler/tools/openroad/scripts/apr/sc_global_placement.tcl +26 -0
  83. siliconcompiler/tools/openroad/scripts/apr/sc_global_route.tcl +61 -0
  84. siliconcompiler/tools/openroad/scripts/apr/sc_init_floorplan.tcl +333 -0
  85. siliconcompiler/tools/openroad/scripts/apr/sc_macro_placement.tcl +123 -0
  86. siliconcompiler/tools/openroad/scripts/apr/sc_metrics.tcl +22 -0
  87. siliconcompiler/tools/openroad/scripts/apr/sc_pin_placement.tcl +41 -0
  88. siliconcompiler/tools/openroad/scripts/apr/sc_power_grid.tcl +60 -0
  89. siliconcompiler/tools/openroad/scripts/apr/sc_repair_design.tcl +68 -0
  90. siliconcompiler/tools/openroad/scripts/apr/sc_repair_timing.tcl +83 -0
  91. siliconcompiler/tools/openroad/scripts/apr/sc_write_data.tcl +125 -0
  92. siliconcompiler/tools/openroad/scripts/common/debugging.tcl +28 -0
  93. siliconcompiler/tools/openroad/scripts/common/procs.tcl +727 -0
  94. siliconcompiler/tools/openroad/scripts/common/read_input_files.tcl +59 -0
  95. siliconcompiler/tools/openroad/scripts/common/read_liberty.tcl +20 -0
  96. siliconcompiler/tools/openroad/scripts/common/read_timing_constraints.tcl +16 -0
  97. siliconcompiler/tools/openroad/scripts/common/reports.tcl +180 -0
  98. siliconcompiler/tools/openroad/scripts/common/screenshot.tcl +18 -0
  99. siliconcompiler/tools/openroad/scripts/common/write_images.tcl +395 -0
  100. siliconcompiler/tools/openroad/scripts/{sc_rcx_bench.tcl → rcx/sc_rcx_bench.tcl} +5 -5
  101. siliconcompiler/tools/openroad/scripts/{sc_rcx_extract.tcl → rcx/sc_rcx_extract.tcl} +0 -0
  102. siliconcompiler/tools/openroad/scripts/sc_rcx.tcl +5 -16
  103. siliconcompiler/tools/openroad/scripts/sc_rdlroute.tcl +51 -51
  104. siliconcompiler/tools/openroad/scripts/sc_show.tcl +110 -0
  105. siliconcompiler/tools/openroad/show.py +28 -23
  106. siliconcompiler/tools/openroad/{export.py → write_data.py} +31 -26
  107. siliconcompiler/tools/opensta/__init__.py +2 -2
  108. siliconcompiler/tools/opensta/check_library.py +27 -0
  109. siliconcompiler/tools/opensta/scripts/sc_check_library.tcl +255 -0
  110. siliconcompiler/tools/opensta/scripts/sc_timing.tcl +1 -1
  111. siliconcompiler/tools/sv2v/sv2v.py +1 -2
  112. siliconcompiler/tools/verilator/verilator.py +6 -7
  113. siliconcompiler/tools/vivado/vivado.py +1 -1
  114. siliconcompiler/tools/yosys/__init__.py +149 -0
  115. siliconcompiler/tools/yosys/lec.py +22 -9
  116. siliconcompiler/tools/yosys/sc_lec.tcl +94 -49
  117. siliconcompiler/tools/yosys/sc_syn.tcl +1 -0
  118. siliconcompiler/tools/yosys/screenshot.py +2 -2
  119. siliconcompiler/tools/yosys/syn_asic.py +105 -74
  120. siliconcompiler/tools/yosys/syn_asic.tcl +58 -12
  121. siliconcompiler/tools/yosys/syn_fpga.py +2 -3
  122. siliconcompiler/tools/yosys/syn_fpga.tcl +26 -19
  123. siliconcompiler/toolscripts/_tools.json +5 -5
  124. siliconcompiler/utils/__init__.py +7 -3
  125. {siliconcompiler-0.28.9.dist-info → siliconcompiler-0.29.1.dist-info}/METADATA +22 -17
  126. {siliconcompiler-0.28.9.dist-info → siliconcompiler-0.29.1.dist-info}/RECORD +131 -114
  127. {siliconcompiler-0.28.9.dist-info → siliconcompiler-0.29.1.dist-info}/WHEEL +1 -1
  128. {siliconcompiler-0.28.9.dist-info → siliconcompiler-0.29.1.dist-info}/entry_points.txt +13 -0
  129. siliconcompiler/libs/asap7sc7p5t.py +0 -8
  130. siliconcompiler/libs/gf180mcu.py +0 -8
  131. siliconcompiler/libs/interposer.py +0 -8
  132. siliconcompiler/libs/nangate45.py +0 -8
  133. siliconcompiler/libs/sg13g2_stdcell.py +0 -8
  134. siliconcompiler/libs/sky130hd.py +0 -8
  135. siliconcompiler/libs/sky130io.py +0 -8
  136. siliconcompiler/pdks/asap7.py +0 -8
  137. siliconcompiler/pdks/freepdk45.py +0 -8
  138. siliconcompiler/pdks/gf180.py +0 -8
  139. siliconcompiler/pdks/ihp130.py +0 -8
  140. siliconcompiler/pdks/interposer.py +0 -8
  141. siliconcompiler/pdks/skywater130.py +0 -8
  142. siliconcompiler/tools/openroad/cts.py +0 -45
  143. siliconcompiler/tools/openroad/floorplan.py +0 -75
  144. siliconcompiler/tools/openroad/physyn.py +0 -27
  145. siliconcompiler/tools/openroad/place.py +0 -41
  146. siliconcompiler/tools/openroad/route.py +0 -45
  147. siliconcompiler/tools/openroad/scripts/__init__.py +0 -0
  148. siliconcompiler/tools/openroad/scripts/sc_apr.tcl +0 -514
  149. siliconcompiler/tools/openroad/scripts/sc_cts.tcl +0 -68
  150. siliconcompiler/tools/openroad/scripts/sc_dfm.tcl +0 -22
  151. siliconcompiler/tools/openroad/scripts/sc_export.tcl +0 -100
  152. siliconcompiler/tools/openroad/scripts/sc_floorplan.tcl +0 -456
  153. siliconcompiler/tools/openroad/scripts/sc_metrics.tcl +0 -1
  154. siliconcompiler/tools/openroad/scripts/sc_physyn.tcl +0 -6
  155. siliconcompiler/tools/openroad/scripts/sc_place.tcl +0 -84
  156. siliconcompiler/tools/openroad/scripts/sc_procs.tcl +0 -494
  157. siliconcompiler/tools/openroad/scripts/sc_report.tcl +0 -189
  158. siliconcompiler/tools/openroad/scripts/sc_route.tcl +0 -143
  159. siliconcompiler/tools/openroad/scripts/sc_screenshot.tcl +0 -18
  160. siliconcompiler/tools/openroad/scripts/sc_write_images.tcl +0 -393
  161. siliconcompiler/tools/yosys/yosys.py +0 -148
  162. /siliconcompiler/tools/openroad/scripts/{sc_write.tcl → common/write_data.tcl} +0 -0
  163. {siliconcompiler-0.28.9.dist-info → siliconcompiler-0.29.1.dist-info}/LICENSE +0 -0
  164. {siliconcompiler-0.28.9.dist-info → siliconcompiler-0.29.1.dist-info}/top_level.txt +0 -0
siliconcompiler/tools/openroad/cts.py DELETED
@@ -1,45 +0,0 @@
1
-
2
- from siliconcompiler.tools.openroad.openroad import setup as setup_tool
3
- from siliconcompiler.tools.openroad.openroad import build_pex_corners
4
- from siliconcompiler.tools.openroad.openroad import post_process as or_post_process
5
- from siliconcompiler.tools.openroad.openroad import pre_process as or_pre_process
6
- from siliconcompiler.tools.openroad.openroad import _set_reports, set_pnr_inputs, set_pnr_outputs
7
-
8
-
9
- def setup(chip):
10
- '''
11
- Perform clock tree synthesis and timing repair
12
- '''
13
-
14
- # Generic tool setup.
15
- setup_tool(chip)
16
-
17
- set_pnr_inputs(chip)
18
- set_pnr_outputs(chip)
19
-
20
- _set_reports(chip, [
21
- 'setup',
22
- 'hold',
23
- 'unconstrained',
24
- 'clock_skew',
25
- 'power',
26
- 'drv_violations',
27
- 'fmax',
28
-
29
- # Images
30
- 'placement_density',
31
- 'routing_congestion',
32
- 'power_density',
33
- 'clock_placement',
34
- 'clock_trees',
35
- 'optimization_placement'
36
- ])
37
-
38
-
39
- def pre_process(chip):
40
- or_pre_process(chip)
41
- build_pex_corners(chip)
42
-
43
-
44
- def post_process(chip):
45
- or_post_process(chip)
siliconcompiler/tools/openroad/floorplan.py DELETED
@@ -1,75 +0,0 @@
1
- from siliconcompiler.tools._common import input_provides, add_common_file, get_tool_task
2
- from siliconcompiler.tools._common.asic import set_tool_task_var
3
- from siliconcompiler.tools.openroad.openroad import setup as setup_tool
4
- from siliconcompiler.tools.openroad.openroad import build_pex_corners
5
- from siliconcompiler.tools.openroad.openroad import post_process as or_post_process
6
- from siliconcompiler.tools.openroad.openroad import pre_process as or_pre_process
7
- from siliconcompiler.tools.openroad.openroad import _set_reports, set_pnr_inputs, set_pnr_outputs
8
-
9
-
10
- def setup(chip):
11
- '''
12
- Perform floorplanning, pin placements, macro placements and power grid generation
13
- '''
14
-
15
- # Generic tool setup.
16
- setup_tool(chip)
17
-
18
- tool = 'openroad'
19
- design = chip.top()
20
- step = chip.get('arg', 'step')
21
- index = chip.get('arg', 'index')
22
- _, task = get_tool_task(chip, step, index)
23
-
24
- if chip.valid('input', 'asic', 'floorplan') and \
25
- chip.get('input', 'asic', 'floorplan', step=step, index=index):
26
- chip.add('tool', tool, 'task', task, 'require',
27
- ",".join(['input', 'asic', 'floorplan']),
28
- step=step, index=index)
29
-
30
- if f'{design}.vg' in input_provides(chip, step, index):
31
- chip.add('tool', tool, 'task', task, 'input', design + '.vg',
32
- step=step, index=index)
33
- else:
34
- chip.add('tool', tool, 'task', task, 'require', 'input,netlist,verilog',
35
- step=step, index=index)
36
-
37
- set_pnr_inputs(chip)
38
- set_pnr_outputs(chip)
39
-
40
- if chip.valid('tool', tool, 'task', task, 'file', 'padring') and \
41
- chip.get('tool', tool, 'task', task, 'file', 'padring',
42
- step=step, index=index):
43
- chip.add('tool', tool, 'task', task, 'require',
44
- ','.join(['tool', tool, 'task', task, 'file', 'padring']),
45
- step=step, index=index)
46
- chip.set('tool', tool, 'task', task, 'file', 'padring',
47
- 'script to insert the padring',
48
- field='help')
49
-
50
- set_tool_task_var(chip, param_key='remove_synth_buffers',
51
- default_value=True,
52
- schelp='remove buffers inserted by synthesis')
53
-
54
- snap = chip.get('tool', tool, 'task', task, 'var', 'ifp_snap_strategy',
55
- step=step, index=index)[0]
56
- snaps_allowed = ('none', 'site', 'manufacturing_grid')
57
- if snap not in snaps_allowed:
58
- chip.error(f'{snap} is not a supported snapping strategy. Allowed values: {snaps_allowed}')
59
-
60
- add_common_file(chip, 'sc_pin_constraint', 'tcl/sc_pin_constraints.tcl')
61
-
62
- _set_reports(chip, [
63
- 'setup',
64
- 'unconstrained',
65
- 'power'
66
- ])
67
-
68
-
69
- def pre_process(chip):
70
- or_pre_process(chip)
71
- build_pex_corners(chip)
72
-
73
-
74
- def post_process(chip):
75
- or_post_process(chip)
siliconcompiler/tools/openroad/physyn.py DELETED
@@ -1,27 +0,0 @@
1
-
2
- from siliconcompiler.tools.openroad.openroad import setup as setup_tool
3
- from siliconcompiler.tools.openroad.openroad import build_pex_corners
4
- from siliconcompiler.tools.openroad.openroad import post_process as or_post_process
5
- from siliconcompiler.tools.openroad.openroad import pre_process as or_pre_process
6
- from siliconcompiler.tools.openroad.openroad import set_pnr_inputs, set_pnr_outputs
7
-
8
-
9
- def setup(chip):
10
- '''
11
- Not implemented yet
12
- '''
13
-
14
- # Generic tool setup.
15
- setup_tool(chip)
16
-
17
- set_pnr_inputs(chip)
18
- set_pnr_outputs(chip)
19
-
20
-
21
- def pre_process(chip):
22
- or_pre_process(chip)
23
- build_pex_corners(chip)
24
-
25
-
26
- def post_process(chip):
27
- or_post_process(chip)
siliconcompiler/tools/openroad/place.py DELETED
@@ -1,41 +0,0 @@
1
-
2
- from siliconcompiler.tools.openroad.openroad import setup as setup_tool
3
- from siliconcompiler.tools.openroad.openroad import build_pex_corners
4
- from siliconcompiler.tools.openroad.openroad import post_process as or_post_process
5
- from siliconcompiler.tools.openroad.openroad import pre_process as or_pre_process
6
- from siliconcompiler.tools.openroad.openroad import _set_reports, set_pnr_inputs, set_pnr_outputs
7
-
8
-
9
- def setup(chip):
10
- '''
11
- Perform global and detail placements along with design violation repairs
12
- '''
13
-
14
- # Generic tool setup.
15
- setup_tool(chip)
16
-
17
- set_pnr_inputs(chip)
18
- set_pnr_outputs(chip)
19
-
20
- _set_reports(chip, [
21
- 'setup',
22
- 'unconstrained',
23
- 'power',
24
- 'drv_violations',
25
- 'fmax',
26
-
27
- # Images
28
- 'placement_density',
29
- 'routing_congestion',
30
- 'power_density',
31
- 'optimization_placement'
32
- ])
33
-
34
-
35
- def pre_process(chip):
36
- or_pre_process(chip)
37
- build_pex_corners(chip)
38
-
39
-
40
- def post_process(chip):
41
- or_post_process(chip)
siliconcompiler/tools/openroad/route.py DELETED
@@ -1,45 +0,0 @@
1
-
2
- from siliconcompiler.tools.openroad.openroad import setup as setup_tool
3
- from siliconcompiler.tools.openroad.openroad import build_pex_corners
4
- from siliconcompiler.tools.openroad.openroad import post_process as or_post_process
5
- from siliconcompiler.tools.openroad.openroad import pre_process as or_pre_process
6
- from siliconcompiler.tools.openroad.openroad import _set_reports, set_pnr_inputs, set_pnr_outputs
7
-
8
-
9
- def setup(chip):
10
- '''
11
- Performs filler insertion, global routing, antenna repair, and detailed routing
12
- '''
13
-
14
- # Generic tool setup.
15
- setup_tool(chip)
16
-
17
- set_pnr_inputs(chip)
18
- set_pnr_outputs(chip)
19
-
20
- _set_reports(chip, [
21
- 'setup',
22
- 'hold',
23
- 'unconstrained',
24
- 'clock_skew',
25
- 'power',
26
- 'drv_violations',
27
- 'fmax',
28
-
29
- # Images
30
- 'placement_density',
31
- 'routing_congestion',
32
- 'power_density',
33
- 'clock_placement',
34
- 'clock_trees',
35
- 'optimization_placement'
36
- ])
37
-
38
-
39
- def pre_process(chip):
40
- or_pre_process(chip)
41
- build_pex_corners(chip)
42
-
43
-
44
- def post_process(chip):
45
- or_post_process(chip)
siliconcompiler/tools/openroad/scripts/__init__.py DELETED
File without changes