digsim-logic-simulator 0.22.0__py3-none-any.whl

digsim/circuit/components/_dip_switch.py

@@ -0,0 +1,73 @@
+# Copyright (c) Fredrik Andersson, 2023-2025
+# All rights reserved
+
+"""A Dip-switch component"""
+
+from .atoms import CallbackComponent, PortOutImmediate
+
+
+class DipSwitch(CallbackComponent):
+    """On/Off Switch  component class"""
+
+    def __init__(self, circuit, name=None, bits=8):
+        super().__init__(circuit, name)
+        self._bits = bits
+        self.parameter_set("bits", bits)
+        self._select = None
+        for index in range(0, self._bits):
+            portout = PortOutImmediate(self, f"{index}")
+            self.add_port(portout)
+
+    def bits(self):
+        """Get number of bits in dipswitch"""
+        return self._bits
+
+    def is_set(self, bit):
+        """Test if dip switch bit is set"""
+        return self.port(f"{bit}").value == 1
+
+    def default_state(self):
+        for port in self.outports():
+            port.value = 0
+
+    def select(self, idx):
+        """Select bit in dipswitch (for toggle)"""
+        self._select = idx
+
+    def selected(self):
+        """Get selected bit in dipswitch (for gui)"""
+        return self._select
+
+    def _toggle_bit(self, bit):
+        if bit >= self._bits:
+            return
+        port = self.port(f"{bit}")
+        if port.value == 1:
+            port.value = 0
+        else:
+            port.value = 1
+
+    def toggle(self):
+        """Toggle the switch"""
+        if self._select is None:
+            return
+        self._toggle_bit(self._select)
+
+    def onpress(self):
+        self.toggle()
+
+    @property
+    def has_action(self):
+        return True
+
+    @classmethod
+    def get_parameters(cls):
+        return {
+            "bits": {
+                "type": "int",
+                "min": 2,
+                "max": 8,
+                "default": 8,
+                "description": "Number of bits",
+            },
+        }

digsim/circuit/components/_flip_flops.py

@@ -0,0 +1,99 @@
+# Copyright (c) Fredrik Andersson, 2023-2025
+# All rights reserved
+
+"""Module with flip flops and latches"""
+
+from .atoms import Component, PortIn, PortOutDelta, PortWire
+
+
+class FlipFlop(Component):
+    """FlipFlip factory component"""
+
+    @classmethod
+    def get_parameters(cls):
+        return {
+            "name": {
+                "type": "component_name",
+                "component_list": {
+                    "SRFF": "SR FlipFlop",
+                    "ClockedSRFF": "SR FlipFlop (Edge triggered)",
+                    "ClockedJKFF": "JK FlipFlop (Edge triggered)",
+                    "ClockedTFF": "T FlipFlop (Edge triggered)",
+                },
+                "description": "Select flip-flop",
+            }
+        }
+
+
+class SRFF(Component):
+    """SR-FlipFlop"""
+
+    def __init__(self, circuit, name=None):
+        super().__init__(circuit, name, display_name="SR")
+        self.add_port(PortIn(self, "S"))
+        self.add_port(PortIn(self, "R"))
+        self.add_port(PortOutDelta(self, "Q"))
+
+    def update(self):
+        if self.S.value == 1:
+            self.Q.value = 1
+        if self.R.value == 1:
+            self.Q.value = 0
+
+
+class ClockedJKFF(Component):
+    """Clocked JK-FlipFlop"""
+
+    def __init__(self, circuit, name=None):
+        super().__init__(circuit, name, display_name="JK-FlipFlop")
+        self.add_port(PortWire(self, "J"))
+        self.add_port(PortIn(self, "C"))
+        self.add_port(PortWire(self, "K"))
+        self.add_port(PortOutDelta(self, "Q"))
+
+    def update(self):
+        rising_edge = self.C.is_rising_edge()
+        if rising_edge:
+            if self.J.value == 1 and self.K.value:
+                self.Q.value = 1 if self.Q.value == 0 else 0
+            elif self.J.value == 1:
+                self.Q.value = 1
+            elif self.K.value == 1:
+                self.Q.value = 0
+
+
+class ClockedSRFF(Component):
+    """Clocked SR-FlipFlop"""
+
+    def __init__(self, circuit, name=None):
+        super().__init__(circuit, name, display_name="SR-FlipFlop")
+        self.add_port(PortWire(self, "S"))
+        self.add_port(PortIn(self, "C"))
+        self.add_port(PortWire(self, "R"))
+        self.add_port(PortOutDelta(self, "Q"))
+
+    def update(self):
+        rising_edge = self.C.is_rising_edge()
+        if rising_edge:
+            if self.S.value == 1:
+                self.Q.value = 1
+            if self.R.value == 1:
+                self.Q.value = 0
+
+
+class ClockedTFF(Component):
+    """Clocked T-FlipFlop"""
+
+    def __init__(self, circuit, name=None):
+        super().__init__(circuit, name, display_name="T-FlipFlop")
+        self.add_port(PortWire(self, "T"))
+        self.add_port(PortIn(self, "C"))
+        self.add_port(PortOutDelta(self, "Q"))
+
+    def init(self):
+        self.T.value = 0
+
+    def update(self):
+        rising_edge = self.C.is_rising_edge()
+        if rising_edge and self.T.value == 1:
+            self.Q.value = 1 if self.Q.value == 0 else 0

digsim/circuit/components/_gates.py

@@ -0,0 +1,246 @@
+# Copyright (c) Fredrik Andersson, 2023-2024
+# All rights reserved
+
+"""Module with the basic logic gates"""
+
+import math
+
+from .atoms import Component, ComponentException, MultiComponent, PortIn, PortOutDelta, PortWire
+
+
+class NOT(Component):
+    """NOT logic gate"""
+
+    def __init__(self, circuit, name=None):
+        super().__init__(circuit, name)
+        self.add_port(PortIn(self, "A"))
+        self.add_port(PortOutDelta(self, "Y"))
+
+    def update(self):
+        if self.A.value == 0:
+            self.Y.value = 1
+        elif self.A.value == 1:
+            self.Y.value = 0
+        else:
+            self.Y.value = "X"
+
+
+class ConfigPortsComponent(Component):
+    """Base class for components with configurable input ports"""
+
+    def __init__(self, circuit, name, ports):
+        super().__init__(circuit, name)
+        self._inports = []
+        portname = "A"
+        for _ in range(ports):
+            port = PortIn(self, portname)
+            self._inports.append(port)
+            self.add_port(port)
+            portname = chr(ord(portname) + 1)
+        self.add_port(PortOutDelta(self, "Y"))
+        self.parameter_set("ports", ports)
+
+    @classmethod
+    def get_parameters(cls):
+        return {
+            "ports": {
+                "type": "int",
+                "min": 2,
+                "max": 8,
+                "default": 2,
+                "description": "Number of input ports",
+            },
+        }
+
+
+class OR(ConfigPortsComponent):
+    """OR logic gate"""
+
+    def __init__(self, circuit, name=None, ports=2):
+        super().__init__(circuit, name, ports)
+
+    def update(self):
+        if any(port.value == 1 for port in self._inports):
+            self.Y.value = 1
+        elif all(port.value == 0 for port in self._inports):
+            self.Y.value = 0
+        else:
+            self.Y.value = "X"
+
+
+class AND(ConfigPortsComponent):
+    """AND logic gate"""
+
+    def __init__(self, circuit, name=None, ports=2):
+        super().__init__(circuit, name, ports)
+
+    def update(self):
+        if all(port.value == 1 for port in self._inports):
+            self.Y.value = 1
+        elif any(port.value == 0 for port in self._inports):
+            self.Y.value = 0
+        else:
+            self.Y.value = "X"
+
+
+class XOR(ConfigPortsComponent):
+    """XOR logic gate"""
+
+    def __init__(self, circuit, name=None, ports=2):
+        super().__init__(circuit, name, ports)
+
+    def update(self):
+        if any(port.value == "X" for port in self._inports):
+            self.Y.value = "X"
+        else:
+            count = 0
+            for port in self._inports:
+                count += port.value
+            self.Y.value = count % 2
+
+
+class NAND(ConfigPortsComponent):
+    """NAND logic gate"""
+
+    def __init__(self, circuit, name=None, ports=2):
+        super().__init__(circuit, name, ports)
+
+    def update(self):
+        if all(port.value == 1 for port in self._inports):
+            self.Y.value = 0
+        elif any(port.value == 0 for port in self._inports):
+            self.Y.value = 1
+        else:
+            self.Y.value = "X"
+
+
+class NOR(ConfigPortsComponent):
+    """NOR logic gate"""
+
+    def __init__(self, circuit, name=None, ports=2):
+        super().__init__(circuit, name, ports)
+
+    def update(self):
+        if any(port.value == 1 for port in self._inports):
+            self.Y.value = 0
+        elif all(port.value == 0 for port in self._inports):
+            self.Y.value = 1
+        else:
+            self.Y.value = "X"
+
+
+class DFF(Component):
+    """D-FlipFlop"""
+
+    def __init__(self, circuit, name=None, async_reset=False, clock_enable=False, width=1):
+        super().__init__(circuit, name)
+        self._async_reset = async_reset
+        self._clock_enable = clock_enable
+        self.add_port(PortWire(self, "D", width=width))
+        if self._async_reset:
+            self.add_port(PortIn(self, "R"))
+        if self._clock_enable:
+            self.add_port(PortWire(self, "E"))
+        self.add_port(PortIn(self, "C"))
+        self.add_port(PortOutDelta(self, "Q", width=width))
+        self.parameter_set("width", width)
+        self.parameter_set("async_reset", async_reset)
+        self.parameter_set("clock_enable", clock_enable)
+
+    def update(self):
+        rising_edge = self.C.is_rising_edge()
+        if self._async_reset and self.R.value == 1:
+            self.Q.value = 0
+        elif rising_edge:
+            if self._clock_enable and self.E.value == 0:
+                # No clock enable
+                return
+            self.Q.value = self.D.value
+
+    @classmethod
+    def get_parameters(cls):
+        return {
+            "async_reset": {
+                "type": "bool",
+                "default": False,
+                "description": "Use asynchronous reset",
+            },
+            "clock_enable": {
+                "type": "bool",
+                "default": False,
+                "description": "Use clock enable",
+            },
+            "width": {
+                "type": "int",
+                "min": 1,
+                "max": 32,
+                "default": 1,
+                "description": "Bitwidth of D and Q ports",
+            },
+        }
+
+
+class MUX(Component):
+    """MUX"""
+
+    def __init__(self, circuit, name=None, ports=2, width=1):
+        super().__init__(circuit, name)
+        if ports not in [2, 4, 8]:
+            raise ComponentException(f"Mux cannot have {ports} number of ports")
+        self._inports = []
+        portname = "A"
+        for _ in range(ports):
+            port = PortIn(self, portname, width=width)
+            self._inports.append(port)
+            self.add_port(port)
+            portname = chr(ord(portname) + 1)
+        self.add_port(PortIn(self, "S", width=int(math.log2(ports))))
+        self.add_port(PortOutDelta(self, "Y", width=width))
+        self.parameter_set("ports", ports)
+        self.parameter_set("width", width)
+
+    def update(self):
+        if self.S.value == "X":
+            self.Y.value = "X"
+            return
+        self.Y.value = self._inports[self.S.value].value
+
+    @classmethod
+    def get_parameters(cls):
+        return {
+            "ports": {
+                "type": "intrange",
+                "range": [2, 4, 8],
+                "default_index": 0,
+                "description": "Number of input ports",
+            },
+            "width": {
+                "type": "int",
+                "min": 1,
+                "max": 32,
+                "default": 1,
+                "description": "Bitwidth of mux ports",
+            },
+        }
+
+
+class SR(MultiComponent):
+    """SR logic gate composed of two NAND gates"""
+
+    def __init__(self, circuit, name=None):
+        super().__init__(circuit, name)
+        _nands = NOR(circuit)
+        _nandr = NOR(circuit)
+        self.add(_nands)
+        self.add(_nandr)
+        _nands.Y.wire = _nandr.A
+        _nandr.Y.wire = _nands.B
+        self.add_port(PortWire(self, "S"))
+        self.add_port(PortWire(self, "R"))
+        self.add_port(PortWire(self, "Q"))
+        self.add_port(PortWire(self, "nQ"))
+
+        self.S.wire = _nands.A
+        self.R.wire = _nandr.B
+        _nands.Y.wire = self.nQ
+        _nandr.Y.wire = self.Q

digsim/circuit/components/_hexdigit.py

@@ -0,0 +1,82 @@
+# Copyright (c) Fredrik Andersson, 2023-2025
+# All rights reserved
+
+"""HexDigit component module"""
+
+from .atoms import CallbackComponent, PortIn
+
+
+class HexDigit(CallbackComponent):
+    """HexDigit component class"""
+
+    VAL_TO_SEGMENTS = {
+        0: "ABCDEF",
+        1: "BC",
+        2: "ABDEG",
+        3: "ABCDG",
+        4: "BCFG",
+        5: "ACDFG",
+        6: "ACDEFG",
+        7: "ABC",
+        8: "ABCDEFG",
+        9: "ABCDFG",
+        10: "ABCEFG",
+        11: "CDEFG",
+        12: "ADEF",
+        13: "BCDEG",
+        14: "ADEFG",
+        15: "AEFG",
+    }
+
+    def __init__(self, circuit, name=None, digits=1, dot=True):
+        super().__init__(circuit, name)
+        self.add_port(PortIn(self, "val", width=4 * digits))
+        self.parameter_set("digits", digits)
+        self.parameter_set("dot", dot)
+        if dot:
+            self.add_port(PortIn(self, "dot", width=digits))
+
+    def get_digits(self):
+        """Get the number of digits"""
+        return self.parameter_get("digits")
+
+    def value(self):
+        """Get value"""
+        return self.val.value
+
+    def dot_active(self, digit_id=1):
+        """Is the dot active for the selected digit_id?"""
+        if not self.parameter_get("dot"):
+            return False
+        if self.dot.value == "X":
+            return False
+        dot_value = self.dot.value >> (self.dot.width - (digit_id + 1)) & 1
+        return dot_value == 1
+
+    def segments(self, digit_id=0):
+        """Which segments are active for the selected digit_id?"""
+        if self.value() == "X":
+            segments = ""
+        else:
+            digit_value = (self.value() >> (self.val.width - (digit_id + 1) * 4)) & 0xF
+            segments = self.VAL_TO_SEGMENTS.get(digit_value, "")
+        if self.dot_active(digit_id):
+            segments += "."
+        return segments
+
+    @classmethod
+    def get_parameters(cls):
+        return {
+            "digits": {
+                "type": "int",
+                "min": 1,
+                "max": 8,
+                "default": 1,
+                "description": "Number of digits",
+            },
+            "dot": {
+                "type": "bool",
+                "default": False,
+                "description": "Use decimal dot",
+            },
+        }

digsim/circuit/components/_ic.py

@@ -0,0 +1,36 @@
+# Copyright (c) Fredrik Andersson, 2023-2025
+# All rights reserved
+
+"""
+Module for creating a yosys component in the ic folder
+"""
+
+from pathlib import Path
+
+from ._yosys_component import YosysComponent
+
+
+class IntegratedCircuit(YosysComponent):
+    """IC component class (predefined yosys module)"""
+
+    def __init__(self, circuit, name="IC", ic_name=None):
+        path = f"{self.folder()}/{ic_name}.json"
+        super().__init__(circuit, name=name, path=path)
+        self.parameter_set("ic_name", ic_name)
+
+    @classmethod
+    def folder(cls):
+        """Get predefined IC folder"""
+        return str(Path(__file__).parent / "ic")
+
+    def settings_to_dict(self):
+        return {"ic_name": self.parameter_get("ic_name")}
+
+    @classmethod
+    def get_parameters(cls):
+        return {
+            "ic_name": {
+                "type": "ic_name",
+                "description": "Select IC",
+            }
+        }

digsim/circuit/components/_label_wire.py

@@ -0,0 +1,167 @@
+# Copyright (c) Fredrik Andersson, 2023-2025
+# All rights reserved
+
+"""Label Wire components module"""
+
+from .atoms import Component, DigsimException, PortIn, PortWire
+
+
+class _LabelWireStorage:
+    """Singleton class with label wires"""
+
+    _instance = None
+    _wire_drivers: dict[str, PortWire] = {}
+    _wire_sinks: dict[str, PortIn] = {}
+
+    def __new__(cls):
+        if cls._instance is None:
+            if not cls._instance:
+                cls._instance = super(_LabelWireStorage, cls).__new__(cls)
+        return cls._instance
+
+    def clear(self):
+        """Remove all wires"""
+        self._wire_drivers = {}
+        self._wire_sinks = {}
+
+    def get_labels(self):
+        """Get label list"""
+        return list(self._wire_drivers.keys())
+
+    def get_wire_width(self, label):
+        """Get width of wire"""
+        driver_port = self._wire_drivers.get(label)
+        if driver_port is None:
+            return None
+        return driver_port.width
+
+    def add_driver(self, label, driver_port):
+        """Add driver port with label"""
+        if label in self._wire_drivers:
+            raise DigsimException(f"Wire Driver '{label}' already added")
+        self._wire_drivers[label] = driver_port
+
+    def _get_driver(self, label):
+        driver_port = self._wire_drivers.get(label)
+        if driver_port is None:
+            raise DigsimException(f"Wire Driver '{label}' not found")
+        return driver_port
+
+    def remove_driver(self, label):
+        """Remove driver"""
+        driver_port = self._get_driver(label)
+        for sink_port, sink_label in self._wire_sinks.items():
+            if label == sink_label:
+                driver_port.disconnect(sink_port)
+        del self._wire_drivers[label]
+
+    def add_sink(self, label, sink_port):
+        """Add driver port with label"""
+        if sink_port in self._wire_sinks:
+            raise DigsimException(f"Wire Sink '{label}' already added")
+        self._wire_sinks[sink_port] = label
+
+    def remove_sink(self, sink_port):
+        """Remove sink"""
+        del self._wire_sinks[sink_port]
+
+    def connect(self, sink_port):
+        """Connect sink port if needed"""
+        if not sink_port.has_driver():
+            label = self._wire_sinks.get(sink_port)
+            if label is None:
+                raise DigsimException("Wire Sink not found")
+            driver_port = self._get_driver(label)
+            driver_port.wire = sink_port
+
+
+class LabelWireIn(Component):
+    """LabelWireIn component class"""
+
+    def __init__(self, circuit, name=None, label=None, width=1):
+        super().__init__(circuit, name)
+        self._label = label
+        self._port_in = PortWire(self, self._label, width=width)
+        self.add_port(self._port_in)
+        self.parameter_set("label", self._label)
+        self.parameter_set("width", width)
+        self._label_wires = _LabelWireStorage()
+        self._label_wires.add_driver(self._label, self._port_in)
+
+    def clear(self):
+        self._label_wires.clear()
+
+    def label(self):
+        """Return Label"""
+        return self._label
+
+    def remove_connections(self):
+        self._label_wires.remove_driver(self._label)
+        super().remove_connections()
+
+    @classmethod
+    def get_parameters(cls):
+        label_wires = _LabelWireStorage()
+        label_list = label_wires.get_labels()
+
+        return {
+            "label": {
+                "type": "str",
+                "single_line": True,
+                "default": "WireLabel",
+                "description": "Label name",
+                "invalid_list": label_list,
+            },
+            "width": {
+                "type": "int",
+                "min": 1,
+                "max": 32,
+                "default": 1,
+                "description": "Bitwidth of wire",
+            },
+        }
+
+
+class LabelWireOut(Component):
+    """LabelWireOut component class"""
+
+    def __init__(self, circuit, name=None, label=None, width=1):
+        super().__init__(circuit, name)
+        self._label_wires = _LabelWireStorage()
+        label_width = self._label_wires.get_wire_width(label)
+        width = label_width if label_width is not None else width
+        self._label = label
+        self._port_out = PortWire(self, self._label, width=width, output=True)
+        self.add_port(self._port_out)
+        self.parameter_set("label", self._label)
+        self.parameter_set("width", width)
+        self._label_wires = _LabelWireStorage()
+        self._label_wires.add_sink(self._label, self._port_out)
+
+    def clear(self):
+        self._label_wires.clear()
+
+    def label(self):
+        """Return Label"""
+        return self._label
+
+    def init(self):
+        self._label_wires.connect(self._port_out)
+        super().init()
+
+    def remove_connections(self):
+        self._label_wires.remove_sink(self._port_out)
+        super().remove_connections()
+
+    @classmethod
+    def get_parameters(cls):
+        label_wires = _LabelWireStorage()
+        label_list = label_wires.get_labels()
+
+        return {
+            "label": {
+                "type": "list",
+                "items": label_list,
+                "description": "Select label",
+            }
+        }