digsim-logic-simulator 0.22.0__py3-none-any.whl

digsim/circuit/components/_yosys_component.py

@@ -0,0 +1,232 @@
+# Copyright (c) Fredrik Andersson, 2023-2025
+# All rights reserved
+
+"""
+Module with classes to create a yosys component
+from a yosys json netlist.
+"""
+
+import json
+
+import digsim.circuit.components._yosys_atoms
+from digsim.synth import Synthesis
+from digsim.utils import YosysCell, YosysModule, YosysNetlist
+
+from ._static_level import GND, VDD
+from .atoms import Component, DigsimException, MultiComponent, PortMultiBitWire
+
+
+class YosysComponentException(DigsimException):
+    """Yosys component exception class"""
+
+
+class YosysComponent(MultiComponent):
+    """Class to create a yosys component from a yosys json netlist"""
+
+    def __init__(self, circuit, path=None, name=None, nets=True):
+        super().__init__(circuit, name)
+        self._circuit = circuit
+        self._path = str(path)
+        self._gates_comp = None
+        self._net_comp = None
+        self._netlist_module = None
+        self._netlist_nets = None
+        self._setup_base()
+
+        if nets:
+            self._net_comp = Component(self._circuit, "nets")
+            self.add(self._net_comp)
+
+        if path is not None:
+            self._load_file()
+
+    def _setup_base(self):
+        self._gates_comp = MultiComponent(self._circuit, "gates")
+        self.add(self._gates_comp)
+
+    def create_from_netlist(self, netlist_object):
+        """Create component from netlist object"""
+        modules = netlist_object.get_modules()
+        module_name = list(modules.keys())[0]
+        self._netlist_module = netlist_object.get_modules()[module_name]
+        self._netlist_nets = self._netlist_module.get_nets()
+
+        # Set Name
+        self.set_name(module_name)
+        self.set_display_name(module_name)
+        # Add External Ports
+        for portname, port_dict in self._netlist_module.ports.items():
+            external_port = PortMultiBitWire(
+                self, portname, width=len(port_dict.bits), output=port_dict.is_output
+            )
+            self.add_port(external_port)
+        # Create component
+        self._create_component()
+
+    def reload_from_netlist(self, netlist_object):
+        """Reload netlist from netlist object"""
+        modules = netlist_object.get_modules()
+        module_name = list(modules.keys())[0]
+        reload_module = netlist_object.get_modules()[module_name]
+        reload_nets = reload_module.get_nets()
+
+        if not self._netlist_module.is_same_interface(reload_module):
+            raise YosysComponentException("Yosys component interface differs")
+
+        # Disconnect ports
+        self._disconnect_external_ports()
+        # Remove yosys atoms
+        self._gates_comp.remove_all_components()
+        # Remove nets
+        if self._net_comp is not None:
+            self._net_comp.delete_all_ports()
+        # Setup netlist
+        self._netlist_module = reload_module
+        self._netlist_nets = reload_nets
+        # Create component
+        self._create_component()
+
+    def _create_cells(self):
+        """Create cells in component"""
+        components_dict = {}
+        for cellname, cell in self._netlist_module.cells.items():
+            if cell.type == "$scopeinfo":
+                continue
+            component_class = getattr(
+                digsim.circuit.components._yosys_atoms, cell.component_type()
+            )
+            component = component_class(self._circuit, name=cell.component_name(cellname))
+            self._gates_comp.add(component)
+            components_dict[cellname] = component
+
+        vdd = VDD(self._circuit)
+        self._gates_comp.add(vdd)
+        components_dict["VDD"] = vdd
+        gnd = GND(self._circuit)
+        self._gates_comp.add(gnd)
+        components_dict["GND"] = gnd
+
+        return components_dict
+
+    def _connect_sinks(self, components_dict, src_comp_port, sinks):
+        """Connect a source port to multiple sinks"""
+        for sink_port in sinks:
+            if isinstance(sink_port.parent, YosysModule):
+                # Connect cell output to module top
+                dst_port = self.port(sink_port.name).get_bit(sink_port.bit_index)
+                src_comp_port.wire = dst_port
+            else:
+                # Connect cell output to cell input
+                dst_comp = components_dict[sink_port.parent_name]
+                src_comp_port.wire = dst_comp.port(sink_port.name)
+
+    def _connect_cells(self, components_dict):
+        """Connect all cells"""
+        for net, source in self._netlist_nets.source.items():
+            if isinstance(source.parent, YosysModule):
+                # Only connect cells here
+                continue
+            if isinstance(source.parent, YosysCell):
+                src_comp = components_dict[source.parent_name]
+                self._connect_sinks(
+                    components_dict, src_comp.port(source.name), self._netlist_nets.sinks[net]
+                )
+
+        gnd_sinks = self._netlist_nets.sinks.get("0", [])
+        self._connect_sinks(components_dict, components_dict["GND"].port("O"), gnd_sinks)
+        vdd_sinks = self._netlist_nets.sinks.get("1", [])
+        self._connect_sinks(components_dict, components_dict["VDD"].port("O"), vdd_sinks)
+
+    def _connect_external_input_port(self, components_dict, portname, port_dict):
+        """Connect external input port"""
+        for bit_idx, net in enumerate(port_dict.bits):
+            for sink_port in self._netlist_nets.sinks[net]:
+                if isinstance(sink_port.parent, YosysModule):
+                    # Connect module input to module output
+                    dst_port = self.port(sink_port.name).get_bit(sink_port.bit_index)
+                    self.port(portname).get_bit(bit_idx).wire = dst_port
+                else:
+                    # Connect module input to cell input
+                    self._connect_sinks(
+                        components_dict, self.port(portname).get_bit(bit_idx), [sink_port]
+                    )
+
+    def _connect_external_input(self, components_dict):
+        """Connect all external input ports"""
+        for portname, port_dict in self._netlist_module.ports.items():
+            if port_dict.direction == "output":
+                continue
+            self._connect_external_input_port(components_dict, portname, port_dict)
+
+    def _create_component(self):
+        """Create yosys component"""
+        # Create cells
+        components_dict = self._create_cells()
+        # Connect cells
+        self._connect_cells(components_dict)
+        # Connect external input ports
+        self._connect_external_input(components_dict)
+
+    def _synth_verilog(self):
+        """Synthesize verilog to netlist"""
+        modules = Synthesis.list_modules(self._path)
+        if len(modules) == 1:
+            toplevel = modules[0]
+        else:
+            raise YosysComponentException("Current only one module per verilog file is supported")
+
+        synthesis = Synthesis(self._path, toplevel)
+        return synthesis.synth_to_dict(silent=True)
+
+    def _load_netlist_dict(self):
+        """Load yosys netlist dict"""
+        if self._path.endswith(".json"):
+            with open(self._path, encoding="utf-8") as json_file:
+                netlist_dict = json.load(json_file)
+        elif self._path.endswith(".v"):
+            netlist_dict = self._synth_verilog()
+        else:
+            raise YosysComponentException(f"Unknown file extension '{self._path}'")
+
+        yosys_netlist = YosysNetlist(**netlist_dict)
+        modules = yosys_netlist.get_modules()
+
+        if len(modules) > 1:
+            raise YosysComponentException("Only one module per file is supported")
+
+        return yosys_netlist
+
+    def _load_file(self):
+        """Load yosys verilog/json-netlist file"""
+        yosys_netlist = self._load_netlist_dict()
+        self.create_from_netlist(yosys_netlist)
+
+    def reload_file(self):
+        """Reload yosys verilog/json-netlist file"""
+        yosys_netlist = self._load_netlist_dict()
+        self.reload_from_netlist(yosys_netlist)
+
+    def _disconnect_external_ports(self):
+        """Disconnect external ports before reload"""
+        for port in self.inports():
+            for bit_id in range(port.width):
+                bit_port = port.get_bit(bit_id)
+                bit_port.remove_wires()
+        for port in self.outports():
+            for bit_id in range(port.width):
+                bit_port = port.get_bit(bit_id)
+                bit_port.set_driver(None)
+
+    def settings_to_dict(self):
+        path = self.circuit.store_path(self._path)
+        return {"path": path}
+
+    @classmethod
+    def get_parameters(cls):
+        return {
+            "path": {
+                "type": "path",
+                "fileinfo": "Yosys JSON Netlist (*.json);;Verilog File (*.v)",
+                "description": "Select verilog file or Yosys json netlist",
+            }
+        }

digsim/circuit/components/atoms/__init__.py

@@ -0,0 +1,23 @@
+# Copyright (c) Fredrik Andersson, 2023-2025
+# All rights reserved
+
+"""All classes within digsim.circuit.components.atoms namespace"""
+
+from ._component import (  # noqa: F401
+    CallbackComponent,
+    Component,
+    ComponentException,
+    MultiComponent,
+)
+from ._digsim_exception import DigsimException  # noqa: F401
+from ._port import (  # noqa: F401
+    VALUE_TYPE,
+    Port,
+    PortConnectionError,
+    PortIn,
+    PortMultiBitWire,
+    PortOutDelta,
+    PortOutImmediate,
+    PortWire,
+    PortWireBit,
+)

digsim/circuit/components/atoms/_component.py

@@ -0,0 +1,280 @@
+# Copyright (c) Fredrik Andersson, 2023-2025
+# All rights reserved
+
+"""This module contains the base classes for all component types"""
+
+from __future__ import annotations
+
+import abc
+import copy
+from typing import Callable
+
+from ._digsim_exception import DigsimException
+from ._port import Port
+
+
+class ComponentException(DigsimException):
+    """Component error exception class"""
+
+
+class Component(abc.ABC):
+    """The component base class"""
+
+    def __init__(self, circuit, name: str | None = None, display_name: str | None = None):
+        self._circuit = circuit
+        self._name: str = name or self.__class__.__name__
+        self._parent: Component | None = None
+        self._ports: list[Port] = []
+        self._circuit.add_component(self)
+        self._display_name: str = display_name or self.__class__.__name__
+        self._parameters: dict[str, int | str | bool] = {}
+
+    def init(self):
+        """Initialize port, will be called when circuit is initialized"""
+        for port in self._ports:
+            port.init()
+
+    def default_state(self):
+        """Setup default state, for example port outputs"""
+
+    def clear(self):
+        """Remove static state within the component class"""
+
+    def parameter_set(self, parameter: str, value: int | str | bool):
+        """Set component parameter"""
+        self._parameters[parameter] = value
+
+    def parameter_get(self, parameter: str) -> int | str | bool:
+        """Get component parameter"""
+        return self._parameters[parameter]
+
+    def add_port(self, port: Port):
+        """
+        Add port to component,
+        also add a 'portname' variable to the component with help of the 'self.__dict__'
+        """
+        self.__dict__[port.name()] = port
+        self._ports.append(port)
+
+    def delete_all_ports(self):
+        """
+        Deleta all component ports
+        """
+        self._ports = []
+
+    def path(self) -> str:
+        """Get component path (iterative)"""
+        path_parts = []
+        current_component = self
+        while current_component is not None:
+            name = current_component.name()
+            if not isinstance(name, str):
+                raise TypeError(
+                    f"Component name is not a string: "
+                    f"{name} ({type(name)}), "
+                    f"component: {current_component.__class__.__name__}"
+                )
+            path_parts.append(name)
+            current_component = current_component._parent
+        return ".".join(reversed(path_parts))
+
+    @property
+    def ports(self):
+        """Get component ports"""
+        return self._ports
+
+    def _get_ports(self, output) -> list[Port]:
+        sel_ports = []
+        for port in self._ports:
+            if port.is_output() == output:
+                sel_ports.append(port)
+        return sel_ports
+
+    def inports(self) -> list[Port]:
+        """Get component input ports"""
+        return self._get_ports(False)
+
+    def outports(self) -> list[Port]:
+        """Get component output ports"""
+        return self._get_ports(True)
+
+    def port(self, portname: str) -> Port:
+        """Get port with name 'portname'"""
+        for port in self._ports:
+            if port.name() == portname:
+                return port
+        raise ComponentException(f"Port '{self.name()}:{portname}' not found")
+
+    @property
+    def circuit(self):
+        """Get the circuit for the current component"""
+        return self._circuit
+
+    def name(self) -> str:
+        """Get the component name"""
+        return self._name
+
+    def set_name(self, name: str, update_circuit: bool = True):
+        """Set the component name"""
+        if update_circuit:
+            self.circuit.change_component_name(self, name)
+        else:
+            self._name = name
+
+    def display_name(self) -> str:
+        """Get the component display name"""
+        return self._display_name
+
+    def set_display_name(self, display_name: str):
+        """Set the component display name"""
+        self._display_name = display_name
+
+    @property
+    def parent(self) -> Component | None:
+        """Get parent component"""
+        return self._parent
+
+    @parent.setter
+    def parent(self, parent: Component):
+        """Set component parent"""
+        self._parent = parent
+
+    def is_toplevel(self) -> bool:
+        """Return True if this component is a toplevel component"""
+        return self._parent is None
+
+    @property
+    def wire(self):
+        """Property needed to be able to have a setter"""
+        raise ComponentException(f"Cannot get wire for component '{self.display_name}'")
+
+    @wire.setter
+    def wire(self, port: Port):
+        """Some components have a single output port, they can wired at component level"""
+        self.outports()[0].wire = port
+
+    def update(self):
+        """This function is called if a port change and that port should update its parent"""
+
+    def remove_connections(self):
+        """Remove component connections"""
+        for src_port in self.outports():
+            for dst_port in src_port.wired_ports:
+                dst_port.set_driver(None)
+
+        for dst_port in self.inports():
+            if dst_port.has_driver():
+                dst_port.get_driver().disconnect(dst_port)
+
+    def add_event(self, port: Port, value: int, delay_ns: int):
+        """Add delta cycle event"""
+        self.circuit.add_event(port, value, delay_ns)
+
+    def __str__(self):
+        comp_str = f"{self.display_name()}"
+        for port in self.inports():
+            comp_str += f"\n - I:{port.name()}={port.value}"
+        for port in self.outports():
+            comp_str += f"\n - O:{port.name()}={port.value}"
+        return comp_str
+
+    @property
+    def has_action(self) -> bool:
+        """Return True if this component is interactive"""
+        return False
+
+    @property
+    def active(self) -> bool:
+        """Return True if this component is active/activated ('on' for a switch for example)"""
+        return False
+
+    def onpress(self):
+        """What to happen for an interactive activation"""
+
+    def onrelease(self):
+        """What to happen for an interactive de-activation"""
+
+    def settings_from_dict(self, settings):
+        """Get component settings from dict"""
+        raise ComponentException(f"No setup for component '{self.display_name}'")
+
+    def settings_to_dict(self) -> dict[str, int | str | bool]:
+        """Return component settings as a dict"""
+        return copy.deepcopy(self._parameters)
+
+    @classmethod
+    def get_parameters(cls):
+        """Return parameters"""
+        return {}
+
+    def update_settings(self, settings: dict[str, int | str | bool]):
+        """Update parameters from settings dict"""
+        for setting, value in settings.items():
+            self.parameter_set(setting, value)
+            self.reconfigure()
+
+    def reconfigure(self):
+        """Update the component from the parameters"""
+
+    def get_reconfigurable_parameters(self):
+        """Return reconfigurable parameters"""
+        reconfigurable_parameters = {}
+        for parameter, parameter_dict in self.get_parameters().items():
+            if parameter_dict.get("reconfigurable", False):
+                reconfigurable_parameters[parameter] = copy.deepcopy(parameter_dict)
+                reconfigurable_parameters[parameter]["default"] = self.parameter_get(parameter)
+                if reconfigurable_parameters[parameter]["type"] == "width_pow2":
+                    reconfigurable_parameters[parameter]["type"] = int
+                    reconfigurable_parameters[parameter]["min"] = 0
+                    reconfigurable_parameters[parameter]["max"] = (
+                        2 ** self.parameter_get("width") - 1
+                    )
+        return reconfigurable_parameters
+
+
+class MultiComponent(Component):
+    """A component that holds one or several sub components"""
+
+    def __init__(self, circuit, name: str):
+        super().__init__(circuit, name)
+        self._components: list[Component] = []
+
+    def init(self):
+        super().init()
+        for component in self._components:
+            component.init()
+
+    def remove_all_components(self):
+        """Remove all sub components from multicomponent"""
+        self._components = []
+
+    def default_state(self):
+        super().default_state()
+        for component in self._components:
+            component.default_state()
+
+    def add(self, component):
+        """Add sub-component to MultiComponent"""
+        self._components.append(component)
+        component.parent = self
+
+
+class CallbackComponent(Component):
+    """
+    A component that will call a callback function upon change,
+    this is used to for example output text in stdout or update GUI
+    objects when the component change value.
+    """
+
+    def __init__(self, circuit, name: str, callback: Callable[[Component], None] | None = None):
+        super().__init__(circuit, name)
+        self._callback = callback
+
+    def set_callback(self, callback: Callable[[Component], None]):
+        """Set CallbackComponent callback function"""
+        self._callback = callback
+
+    def update(self):
+        """Call CallbackComponent callback function if available"""
+        if self._callback is not None:
+            self._callback(self)

digsim/circuit/components/atoms/_digsim_exception.py

@@ -0,0 +1,8 @@
+# Copyright (c) Fredrik Andersson, 2023-2025
+# All rights reserved
+
+"""The digsim exception base"""
+
+
+class DigsimException(Exception):
+    """The digsim exception base class"""