digsim-logic-simulator 0.22.0__py3-none-any.whl

digsim_logic_simulator-0.22.0.dist-info/METADATA

@@ -0,0 +1,140 @@
+Metadata-Version: 2.4
+Name: digsim-logic-simulator
+Version: 0.22.0
+Summary: Interactive Digital Logic Simulator
+Author-email: Fredrik Andersson <freand@gmail.com>
+Maintainer-email: Fredrik Andersson <freand@gmail.com>
+Project-URL: homepage, https://github.com/freand76/digsim
+Keywords: educational,simulation,digital
+Classifier: Development Status :: 5 - Production/Stable
+Classifier: Programming Language :: Python :: 3
+Classifier: Programming Language :: Python :: 3.10
+Classifier: Programming Language :: Python :: 3.11
+Classifier: Programming Language :: Python :: 3.12
+Classifier: Programming Language :: Python :: 3.13
+Classifier: Programming Language :: Python :: 3.14
+Classifier: Programming Language :: Python :: 3 :: Only
+Requires-Python: >=3.10
+Description-Content-Type: text/markdown
+License-File: LICENSE.md
+Requires-Dist: pyvcd==0.4.1
+Requires-Dist: pyside6==6.10.1
+Requires-Dist: pexpect==4.9.0
+Requires-Dist: pydantic==2.12.5
+Requires-Dist: qtawesome==1.4.0
+Requires-Dist: yowasp-yosys==0.60.0.0.post1055
+Dynamic: license-file
+
+# DigSim - Interactive Digital Logic Simulator
+
+![Python Version from PEP 621 TOML](https://img.shields.io/python/required-version-toml?tomlFilePath=https%3A%2F%2Fraw.githubusercontent.com%2Ffreand76%2Fdigsim%2Fmain%2Fpyproject.toml)
+![PyPI - Version](https://img.shields.io/pypi/v/digsim-logic-simulator)
+![PyPI - Downloads](https://img.shields.io/pypi/dm/digsim-logic-simulator)
+
+<p align="center">
+  <img alt="The DigSim Application" src="https://raw.githubusercontent.com/freand76/digsim/af1bf95eb16d1af19f26159a4c1e1b88565703d7/docs/images/screenshot_digsim_app.png" width=85%>
+</p>
+
+## Introduction
+
+DigSim is a python based framework for digital circuit simulation.
+The main purpose of the software is to, in an educational way, play around with digital logic (simple gates and verilog designs).
+
+When working with block design in Verilog/VHDL the simulation tools are normally fed with test stimuli (a very non-interactive way of working...)
+A block design can be synthesized and tested on an FPGA (where there are possibilities for interactivity if buttons and LED/Hex digits are available),
+but that often has a great cost in time (and sometimes money) leading to long turnaround time.
+
+I started developing DigSim to make it easy to implement and visualize the functionality of simple verlog modules.
+During development I tried to synthesize larger verilog designs, such as the classic [6502 CPU](https://en.wikipedia.org/wiki/MOS_Technology_6502),
+and even if it is slower than many other simulators it is not entirely useless.
+
+### Features
+ * Create and simulate a circuit using python code
+ * Create and simulate a circuit **interactively** using the GUI
+ * Create new components using synthesized verilog code
+ * Save simulation results in VCD files, which can be opened in for example GTKWave.
+
+## Quickstart
+
+### Install from PyPi (Option 1)
+```
+pip3 install digsim-logic-simulator
+```
+
+### Install from GitHub (Option 2)
+```
+> git clone https://github.com/freand76/digsim.git
+> cd digsim
+> python3 -m pip install .
+```
+
+### Start Interactive GUI
+
+**Prerequisites:** Install by using *Option 1* or *Option 2* above.
+
+```
+> python3 -m digsim.app
+```
+
+or
+
+```
+> digsim-logic-simulator
+```
+
+### Start using uv
+
+**Prerequisites:** Download and install [uv](https://docs.astral.sh/uv/)
+
+```
+> uvx digsim-logic-simulator
+```
+
+**Note: Ubuntu**
+
+If your Ubuntu installation gives the folloing error message:
+
+*qt.qpa.plugin: Could not load the Qt platform plugin "xcb" in "" even though it was found.*
+*This application failed to start because no Qt platform plugin could be initialized. Reinstalling the application may fix this problem.*
+
+*Available platform plugins are: vnc, wayland, wayland-egl, eglfs, offscreen, xcb, minimal, linuxfb, vkkhrdisplay, minimalegl.*
+
+Then the following package must be installed:
+```
+> apt install libxcb-cursor0
+```
+
+### Start with example circuit (example circuits are available in the github repository)
+```
+> python3 -m digsim.app --load example_circuits/counter_yosys_netlist.circuit
+```
+
+### Run example (examples are available in the github repository)
+```
+> python3 examples/example_sr.py
+```
+
+### Look at waveforms
+```
+> python3 examples/example_sr.py
+> gtkwave sr.vcd
+```
+
+### Examples of writing pytest/python test benches for synthesized verilog code
+```
+> pytest examples/pytest_tb
+```
+
+## Yosys synthesis helper tool
+
+```
+> python3 -m digsim.synth synth -i <verilog file 1> <optional verilog file 2> -o <output_file.json> -t <verilog top_module>
+```
+
+## Documentation
+
+[Documentation](https://github.com/freand76/digsim/blob/main/docs/documentation.md) on GitHub
+
+## Star History
+
+[![Star History Chart](https://api.star-history.com/svg?repos=freand76/digsim&type=Date)](https://star-history.com/#freand76/digsim&Date)

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digsim_logic_simulator-0.22.0.dist-info/WHEEL

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+Wheel-Version: 1.0
+Generator: setuptools (80.9.0)
+Root-Is-Purelib: true
+Tag: py3-none-any
+

digsim_logic_simulator-0.22.0.dist-info/entry_points.txt

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+[console_scripts]
+digsim-logic-simulator = digsim.app.cli:main

digsim_logic_simulator-0.22.0.dist-info/licenses/LICENSE.md

@@ -0,0 +1,32 @@
+The Clear BSD License
+
+Copyright (c) 2023-2024, Fredrik Andersson
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+  list of conditions and the following disclaimer.
+
+* Redistributions in binary form must reproduce the above copyright notice,
+  this list of conditions and the following disclaimer in the documentation
+  and/or other materials provided with the distribution.
+
+* Neither the name of the copyright holder nor the names of its
+  contributors may be used to endorse or promote products derived from
+  this software without specific prior written permission.
+
+NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS
+LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+-------------------------------------------------------------------------------

digsim_logic_simulator-0.22.0.dist-info/top_level.txt

@@ -0,0 +1 @@
+digsim